US20100323497A1 - Method of transferring a thin layer onto a target substrate having a coefficient of thermal expansion different from that of the thin layer - Google Patents

Method of transferring a thin layer onto a target substrate having a coefficient of thermal expansion different from that of the thin layer Download PDF

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US20100323497A1
US20100323497A1 US12817784 US81778410A US20100323497A1 US 20100323497 A1 US20100323497 A1 US 20100323497A1 US 12817784 US12817784 US 12817784 US 81778410 A US81778410 A US 81778410A US 20100323497 A1 US20100323497 A1 US 20100323497A1
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layers
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layer
interface
thin layer
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Franck Fournel
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Commissariat a l'Energie Atomique et aux Energies Alternatives
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185Joining of semiconductor bodies for junction formation
    • H01L21/187Joining of semiconductor bodies for junction formation by direct bonding

Abstract

A method of transferring a thin layer from a source substrate having a surface layer of a first material along a free surface thereof to a target substrate having at least one surface layer of a second material along a free surface thereof, where the first material differs from the second material, includes forming within the surface layer of the source substrate a weakened zone delimiting a thin layer with respect to the free surface, and assembling the free surface of the source substrate to the free surface of the target substrate in a stack of alternating layers comprising the first and second materials, so that there are, on either side of an interface formed by bringing the free surfaces into intimate contact. The cumulative thicknesses of the layers of the first material are substantially equal to the cumulative thickness of the layers of the second material, the layers having thicknesses at least equal to 50 microns and at least 1000 times the depth at which the weakened zone is formed. The thin layer is detached by applying at least partially thermal energy to fracture the weakened zone.

Description

    RELATED APPLICATIONS
  • This application claims the benefit of priority to French Patent Application No. 0954126, filed Jun. 18, 2009, which is incorporated by reference herein.
  • FIELD OF THE INVENTION
  • The invention concerns the transfer of a thin layer from a source substrate onto a target substrate having a coefficient of thermal expansion significantly different from that of the source substrate.
  • BACKGROUND
  • A conventional method for such layer transfer is known as the “Smart Cut™” method; it consists mainly in carrying out the following steps (see in particular the French Patent Application No. FR-2 681 472 or its equivalent U.S. Pat. No. 5,374,564 and its various developments and improvements):
  • creation by ionic implantation of a buried weakened zone within the source substrate, delimiting with the free surface the future thin layer to be transferred,
  • assembly of the source substrate and the target substrate at said free surface, and
  • input of thermal and/or mechanical energy to provoke a fracture in the weakened zone within the source substrate.
  • During fabrication by this “Smart Cut™” method of a heterostructure (in particular, a structure made up of at least two different materials, generally in a plurality of layers, and having a thickness typically between 1 μm and 1 cm inclusive), control of internal stresses is very important if the materials of the heterostructure have significantly different coefficients of thermal expansion and it is required to induce the fracture at a temperature significantly different from that at which bonding was effected (for example when it is required to use a heat treatment to induce some or all of the fracture in the weakened zone).
  • For example, in the case of the transfer of a film of silicon from a source substrate (of which at least a surface portion is in silicon) onto a target substrate the coefficient of thermal expansion of which is very different from that of the silicon source substrate (for example a fused silica target substrate), the two solid substrates are conventionally bonded at room temperature, for example by molecular bonding. When, to transfer the film, the choice is made to use an input of thermal energy, it is known that the bonding interface is then consolidated; however, this heat treatment also has the effect that internal stresses, which can be very high, are generated as a consequence of the difference between the coefficients of expansion on either side of this bonding interface; it follows from this that when the transfer of the silicon film is effected (in particular, when the fracture induced by the “Smart Cut™” method occurs), the two substrates (or a portion of the two substrates if the fracture does not extend over the whole area of the substrates) are brutally separated and then immediately relax. This stress jump, if it is of too high a magnitude, risks damaging one or the other of the two parts of the heterostructure separated in this way (formed, in the example considered here, by the silica substrate carrying the transferred thin film of silicon and the silicon substrate in which the fracture has been provoked).
  • There would be a benefit in being able to minimize the stress jump that occurs on the separation of a heterostructure at a temperature different from its creation temperature.
  • To minimize any such stress jump, thought may be given to creating the heterostructure at a higher temperature, preferably at least approximately at the temperature at which the fracture is subsequently to be provoked. However, when the heterostructure is produced by molecular bonding, the bonding energy decreases greatly when bonding above 200° C., although this is a low temperature at which application of the “Smart Cut™” technology can prove difficult, simply by input of thermal energy, in a silicon/fused silica system, for example (to transfer a silicon film onto a fused silica substrate); it follows from this that, when it is required to provoke fracture only by input of thermal energy, it is required in practice to proceed at a temperature much higher than 200° C. Now, if the bonding energy is too low, the stresses of thermal origin can be sufficient to provoke unsticking of the structure at the interface (rather than in the weakened zone) or at least lead to poor functioning of the “Smart Cut™” technology: the bonding interface may then not withstand the vertical pressure imposed by the development of microcavities that this method generates (on this subject see “Silicon on insulator material technology”, M. Bruel, Electron. Lett. Vol. 31-No. 14 (1995) p. 1201).
  • To minimize the stress jump it has already been proposed to bond the parts of the heterostructure under conditions such that the stress regime at the interface falls below a given threshold when this heterostructure is brought to the temperature at which it is wished to provoke the fracture in a weakened zone in one of the wafers near the bonding interface. Thus French Patent Application No. FR-2 848 336 or its equivalent U.S. Patent Publication No. 2006/0205179 proposes to effect the bonding of two wafers that have been subject beforehand to deformation. To be more precise, the above document teaches imposing a stress on the wafers at the moment of bonding at room temperature by bending the two plates before molecular bonding; if the curvature is carefully chosen, it is possible to minimize or even to eliminate internal stresses generated by thermal annealing of the heterostructure at the fracture temperature. However, to enable separation by the “Smart Cut™” method during thermal annealing of short duration, this method generally calls for bonding the structures with fairly high radii of curvature which, from the technological point of view, can prove relatively difficult to achieve on an industrial scale; moreover, the conditions of the future fracture must be known at the time that bonding is effected. On the other hand, this technology has the advantage that the molecular bonding can be effected at room temperature and thus makes it possible to have a good bonding energy at the moment of the transfer.
  • It follows from this that it is therefore possible to transfer a thin layer at a temperature as high as may be required from one of the wafers to the other wafer, the fracture occurring in the weakened zone previously formed, whereas the bonding interface between this thin layer and the wafer to which it is henceforth fixed can have a high bonding energy. It must nevertheless be noted that, on returning to room temperature, the thin layer may be stressed in traction or in compression because its coefficient of thermal expansion is different from that of the wafer to which it has been firmly attached by molecular bonding; because the target wafer is in practice more solid than the thin layer, it is hardly deformed when the temperature changes after fracture, imposing a change in the dimensions of the thin layer because of the change of temperature.
  • This kind of phenomenon had already been exploited in the case of a homostructure (in particular, a structure formed of layers or substrates in the same material); Feijoo et al. have proposed to impose a stress within a homostructure at room temperature by application of a deformation just before the formation of this homostructure by bonding (see D. Feijoo, I. Ong, K. Mitani, W. S. Yang, S. Yu and U. M. Gösele, “Prestressing of bonded wafers”, Proceedings of the 1st international symposium on semiconductor wafer bonding, Science, Technology and Applications, Vol. 92-7, The Electrochemical Society (1992) p. 230). To be more precise, in the above paper, a homostructure consists of two silicon wafers that are bonded with a certain radius of curvature (the paper states that the plates are bonded and unbonded several times during deformation). The authors propose thinning one of the silicon crystals thereafter at room temperature by mechanical means (lapping) so as to be able to impose a high stress in the thinned silicon film after return of the other plate to a plane shape.
  • It should be noted that the above document does not envisage obtaining the thin layer by fracture within one of the plates of the homostructure; a fortiori, the above document does not address in any way the problem of the separation of a heterostructure at a temperature different from the creation temperature (in fact, there would have been no particular problem with regard to a homostructure, since there is no thermal effect on the stress state at the interface).
  • SUMMARY
  • An object of the invention is to minimize the stress jump between two substrates during transfer of a thin layer from one of the substrates to the other by fracture in a previously weakened zone, even by simple input of thermal energy, at any temperature, without having to provide for stressing by deformation at the moment of bonding between the two substrates. It is evident that it might be of benefit to be able to proceed to the assembly by bonding at any temperature, for example at room temperature, and thus without having to sacrifice the bonding energy level, without having to impose deformation beforehand, and thus for example flat, and without having to know in advance the conditions of the future fracture effecting the transfer.
  • To this end, the invention proposes a method of transferring a thin layer from a source substrate of which a surface layer along a free surface is in a first material to a target substrate of which at least one surface layer along a free surface is in a second material different from the first material, wherein:
  • there is formed within the surface layer of the source substrate a weakened zone delimiting with its free surface a future thin layer,
  • the free surface of the source substrate is assembled to the free surface of the target substrate in a stack of alternating layers formed of the first and second materials so that there are layers of the first and second materials on either side of the interface formed by the assembly of said free surfaces brought into intimate contact, the cumulative thickness of the layers of the first material situated on a first side of this interface being equal to the cumulative thickness of the layers of this first material situated on the other side of this interface and the cumulative thickness of the layers of the second material situated on this first side of the interface being equal to the cumulative thickness of the layers of this second material situated on the other side of this interface, the layers having thicknesses at least equal to 50 microns and at least equal to 1000 times the depth at which the weakened zone is formed,
  • fracture in the weakened zone is provoked by input of at least partially thermal energy to detach the thin layer.
  • It is to be noted that the invention minimizes the stress jump that occurs during fracture in the weakened zone without seeking to minimize the stresses in the heterostructure; in contrast to the prior art solution that sought to minimize the stress regime on respective opposite sides of the weakened zone at the moment of fracture, the invention aims to generate stresses which are substantially the same before and after fracture: there is therefore no sudden variation of stress during fracture; it is the sharp variations of stress that are liable to degrade the layers of the heterostructure, not the absolute value of the stress.
  • According to preferred features of the invention, where appropriate in combination:
  • said stack is produced from a material such that each of the two parts situated on either side of the interface has a plane of symmetry parallel to said interface;
  • said stack is formed only of layers formed of one or the other of the first and second materials;
  • one of the parts of the stack includes between two other layers of the second material having substantially equal thicknesses a layer of the first material having a thickness substantially equal to twice the thickness of these other layers and the other part of the stack includes between two other layers formed of the first material having substantially equal thicknesses a layer of the second material having a thickness substantially equal to twice the thickness of these other layers;
  • the first part includes a double layer of the first material sandwiched between two identical layers of the second material and the other part includes a double layer of the second material sandwiched between two identical layers of the first material;
  • after fracture in the weakened zone, separation is provoked at a bonding interface within the part to which the thin layer has been transferred;
  • separation is provoked at an interface with a lower bonding energy formed within the assembly; it may be noted that the fact that this detachment is not effected on the side of the transferred film has the benefit that there is no risk of damage (in contrast to mechanical transfer);
  • the part of the stack the thin layer of which has been separated is used in a new stack after forming a new weakened zone delimiting with the free surface liberated by the fracture a future thin layer;
  • the weakened zone is formed by ionic implantation;
  • the first material is silicon.
  • BRIEF DESCRIPTION OF DRAWING
  • Objects, features and advantages of the invention emerge from the following description, given by way of illustrative and nonlimiting example with reference to the appended drawings, in which:
  • FIG. 1 is a diagram representing a stack of a first embodiment of the invention,
  • FIG. 2 is a diagram representing a stack of a second embodiment of the invention,
  • FIG. 3 consists of graphs representing the evolution of the stresses in the layers of the FIG. 1 part of the stack, above the weakened zone, as a function of temperature before and then after fracture,
  • FIG. 4 consists of graphs representing the evolution of the stresses in the layers of the FIG. 1 part of the stack, below the weakened zone, as a function of temperature before and then after fracture,
  • FIG. 5 consists of graphs representing the evolution of the stresses on either side of the source substrate on top of which is a target substrate to which a thin layer of the source substrate must be transferred as a function of temperature before and then after fracture, and
  • FIG. 6 consists of graphs representing the evolution of the stresses on either side of the target substrate to which the thin layer from FIG. 5 must be transferred as a function of temperature before and then after fracture.
  • DETAILED DESCRIPTION
  • FIGS. 1 and 2 represent two examples of stacks making it possible, according to the invention, to proceed reliably to the transfer, by input of at least partially thermal energy, of a thin layer from a target substrate to a source substrate, even when the substrates have significantly different coefficients of thermal expansion.
  • It is in fact clear that when two layers of different materials are bonded to each other and are then subjected to the input of thermal energy, this input of thermal energy generates, at the level of and parallel to the bonding interface, tensile stresses in the surface layer the coefficient of thermal expansion of which is lower and compressive stresses in the surface layers of the other layer the coefficient of thermal expansion of which is higher (the layer that expands more tends to stretch the one that expands less, and the latter tends to prevent the natural expansion of this layer that expands more).
  • As these two embodiments show, the invention aims to enable transfer of a thin layer from a first layer in a first material to another layer in a second material, these first and second materials having significantly different coefficients of thermal expansion and these layers being situated in a median position of the stack concerned. These stacks are not designed to minimize the stresses existing along the surfaces freed by the fracture at the level of a weakened zone within the first layer, but to reduce the variations at the moment of fracture of the stresses existing locally on either side of this weakened zone. In other words, the invention aims to reduce the stress jumps occurring at the moment of fracture at the same time as accepting the existence of these stresses at a non-negligible level.
  • These stacks are produced at any temperature relative to the temperature at which it is intended to provoke the fracture; the simplest way is to proceed at room temperature. Furthermore, no prestressing is intentionally applied to the layers of this stack at the moment of their assembly by bonding. Since the layers are in practice plane, the assembly is in practice carried out flat.
  • In the FIG. 1 example, the objective is to transfer a thin layer from a source layer 11 in a material A to a target layer 21 in a material B. Each of these layers has a free surface and the thin layer is to be transferred from one of these layers to the other after the respective free surfaces of these layers have been brought into intimate contact. These layers have a thickness of at least 50 microns, preferably at least 100 microns (they are thus not thin layers, but rather layers commonly referred to as “thick” layers).
  • Beforehand, a weakened layer Z has been produced at a chosen distance below the surface of the layer 11 which is then brought into intimate contact with a surface of the layer 21. This weakened layer is typically produced by implantation (in practice by ionic bombardment) of one or more species, notably implantation of hydrogen, helium, or even other gases or heavier elements. The chosen distance between the free surface of the target layer and the weakened zone is in practice at most equal to 1/100th of the thickness of that layer; the future thin layer (which is delimited between this surface and this weakened zone) preferably has a thickness of at most 1/1000th of that of the layer. FIG. 1 does not conform to this ratio for obvious reasons of legibility.
  • The layer 11 can be merely a surface layer of a source substrate formed of at least one other underlying layer; likewise, the layer 21 can be merely a surface layer of a target substrate formed of at least one other higher layer.
  • According to the invention, before the separation step during which fracture is to be provoked in the weakened layer Z, the source substrate and the target substrate are assembled at their free surfaces within a stack of alternate layers formed of the first or the second material such that, on either side of the interface formed by bringing the free surfaces into intimate contact:
  • the cumulative thickness of layers formed of the first material are substantially equal,
  • the cumulative thickness of the layers formed of the second material are substantially equal.
  • This stack is advantageously such that each of the two parts of the stack situated on either side of the interface between the layers 11 and 21 has a plane of symmetry diagrammatically represented by the chain-dotted lines X-X and Y-Y.
  • There can be thin intermediate layers between the layers in material A or material B, but the stack is preferably formed only of layers formed of one or the other of these materials A and B (if there are intermediate attachment layers, their cumulative thickness does not represent more than 1% of the total thickness of the stack).
  • To be more precise, it is clear from FIG. 1 that the stack is formed: of a lower part 10 formed of the layer 11 in material A on top of a layer 12 in material B on top of a layer 13 in material A, the layer 12 having a thickness twice that of the layer 11 and the layer 13 having the same thickness as the layer 11,
  • an upper part 20 formed of the layer 21 in material B on top of which is a layer 22 in material A on top of which is a layer 23 formed of the material B, the thickness of the layer 22 being twice that of the layer 21 and the layer 23 having the same thickness as this layer 21.
  • As a result, the layer 11 from which it is wished to transfer a thin layer to the layer 21 is sandwiched between layers (12 and 21) in material B and the layer 21 is also sandwiched between layers (11 and 22). It follows from this that, during a temperature variation after assembly, each of the layers 11 and 21 is loaded in a similar manner along its upper and lower faces, whence an approximately homogeneous stress field.
  • It follows from this that during a heat treatment applied after assembly is advantageously effected at room temperature the stresses existing in the layer 11 on either side of the weakened zone Z are similar, with the result that the fracture does not involve any stress jump in the two parts of the layer 11 separated by the fracture of sufficient magnitude to be liable to degrade one of these parts.
  • It may be noted that if the mechanical calculations developed by Z-C Feng et al. (Zhe-Chuan Feng and Hong-du Liu J; Appl. Phys. 54 (1), 1983, p. 83 “Generalized formula for curvature radius and layer stresses caused by thermal strain in semiconductor multilayer structures”), it is possible to predict the stresses that will appear within the layers 10+20 of the stack (forming a heterostructure) before and after separation by fracture in the weakened zone.
  • It may be noted that the stack may be considered to be formed of a stack of four pairs of layers A-B (starting from the bottom, the FIG. 1 stack can in fact be described as being the succession of a pair A-B, a pair B-A, a pair B-A and then a pair A-B).
  • In the FIG. 1 stack the layers 11 and 21 (and thus the layers 13 and 23) have equal thickness a=b, and the layers 12 and 22 have equal thicknesses 2 a= 2B, the breakdown into pairs A-B corresponds to pairs of layers of the same thickness and the stack may be represented as the assembly of a lower sub-stack ABBA and an upper stack BAAB, and the fracture in the weakened layer leads to the formation of a lower assembly ABBA′ and an upper assembly aBAAB (A′ representing what remains of the layer 11 after separation of the thin layer “a”).
  • The invention nevertheless applies also to the case of layers having different thicknesses, as shown diagrammatically in FIG. 2 where the thickness b is ⅔ the thickness a. Designating the layers by the same references as in FIG. 1 with the addition of a “prime” suffix, it is found that the upper intermediate layer 22′ has a thickness that is three times the thickness of the layer 21′ or 23′ and the intermediate layer 12′ has a thickness hardly greater than that of the layer 11′ or 13′.
  • The aforementioned calculations nevertheless make it possible to verify that, even with such a difference, stress fields are produced enabling fracture without stress jumps of great magnitude at the moment of fracture.
  • FIGS. 3 and 4 represent curves of variation of the stress within the various layers after assembly at room temperature during the increase in temperature for fracture heat treatment (the fracture is represented diagrammatically by an asterisk on the right-hand side of the frames of these curves) and then during return to room temperature.
  • To be more precise, FIG. 3 groups curves corresponding to each of the layers of the upper part of the FIG. 1 stack, starting from the top, in the case where the intermediate layer 22 is itself formed of two identical layers 22-1 and 22-2, and with the transferred thin layer 11 a.
  • As for FIG. 4, it groups curves corresponding to each of the layers of the lower part of the FIG. 1 stack, starting from the layer 11, in the case where the intermediate layer 12 is itself formed of two identical layers 12-1 and 12-2.
  • These curves are calculated in the following case:
  • the layers 11, 13, 22-1 and 22-2 are in silicon and have thicknesses equal to 750 microns,
  • the layers 21, 23 and 12-1 and 12-2 are in fused silica and have thicknesses of 1200 microns.
  • It is seen that, because the silicon expands more than the fused silica, a rise in temperature generates, parallel to the interface between the layers, tensile stressing of the silica by the silicon and therefore compressive stressing of the silica by the silicon; in other words, the silica layers are the seat of positive (tension) stresses along similar well-defined curves within the layers 23, 21, 12-1 and 12-2; in contrast, the silicon layers are the seat of negative (compression) stresses along similar well-defined curves within the layers 22-1, 22-2, 11 a, 11 and 13.
  • The arrows directed toward the right indicate the direction of travel of the curves during an increase in temperature and the arrows directed toward the left indicate the direction of travel of the same curves during cooling; it is seen that the same curves are traveled in the heating direction and during cooling although fracture has occurred at the maximum temperature with separation of the structure into two sub-structures.
  • In fact, the stresses are not exactly identical within the layers because a film is taken off one of the substrates, which very slightly unbalances the two sub-structures, with the result that there is a small stress jump on fracture in the weakened zone of the layer 11; however, in the example considered of an alternation of silicon and silica layers and a thin layer with a thickness of less than 1/1000th of the thickness of the silicon and silica layers, the jump is only of the order of 0.1 MPa, which does not degrade the layers (including the thin layer) at the time of fracture. This jump also influences slightly the evolution of the sag of each structure, but this changes very little (less than 0.5 micron).
  • It is interesting to note that the layers of the stack remain substantially plane during temperature variations, including during fracture, which facilitates manipulation of the layers separately or in combination (as and when they are assembled) during these heat treatments.
  • As mentioned hereinabove, the source substrate can consist of the layer 11 alone or be formed of the layers 11 and 12-1 or even layers 11 and 12 or layers 11, 12 and 13. Likewise, the target substrate can consist of the layer 21 alone, the layers 21 and 22-2 or even the layers 21 and 22 or the layers 21, 22 and 23. It is clear that in each case it is possible, possibly by adding layers, to produce the FIG. 1 (or FIG. 2) stack as a function of the relative thicknesses of the layers.
  • In the case where, after transfer and fracture, it is required to recover the target substrate with the transferred layer, it is useful to be able to detach the layer(s) added to this target substrate to form the stack.
  • To this end, this starting target substrate is advantageously assembled to the adjacent layer necessary for forming the required stack with a reduced bonding energy imparted to the bonding interface, for example by roughening one or both of the surfaces assembled in this way. Consequently, after cooling of the assembly 11 a-21-22-23 obtained after fracture, detachment at the reduced energy interface can easily be obtained, for example by inserting a blade into the interface to be freed; it is to be noted that, if this is done at room temperature, there is no stress jump at the moment of detachment. If, on the other hand, the choice is made to effect such detachment at a temperature different from room temperature (thus at a temperature different from that at which the stack was produced), the stress jump, if any, generated will have no significant consequence for the thin layer since this stress jump, if any, will take place at a face of the target substrate opposite the transferred thin layer. It may be noted that since the low-energy bonding is effected at a distance from the weakened zone, the rupture can be effectively localized to this weakened zone, provided that the low-energy bonding is nevertheless sufficient to resist the overall stresses generated at the various interfaces during the heat treatment.
  • In fact, detachment at the aforementioned bonding interface can be controlled under good conditions even if the bonding energy is not to be downgraded, since mechanical detachment remains possible up to high bonding energies such as 0.5 J/m2.
  • As for the lower part of the stack, including the source substrate, it can be re-used directly to transfer a new thin layer from the layer 11 by bonding it to a target substrate analogous to the starting one, after further weakening treatment, and adding to it the part of the stack that has been detached at the aforementioned bonding level.
  • As has also been mentioned, it is possible for attachment of the layers formed of the materials A and B to be facilitated by the interposition of attachment layers. This remains entirely valid provided that the cumulative thickness of the intermediate layers not formed of A or B remains less than about 0.1% of the thickness of the layer concerned.
  • Clearly the advantages of the invention are retained when it is wished to provoke the fracture by application of mechanical energy (fluid, blade, vibrations, ultrasound), as well as heat treatment.
  • FIGS. 5 and 6 represent, by way of comparison, curves representing the variations of the stresses along the opposed faces of a source layer and a target layer similar to the aforementioned layers 11 and 21 alone, in the absence of the additional layers 12 and 13, on the one hand, and 22 and 23, on the other hand.
  • Clearly the advantages of the invention may be obtained even in the event of a slight departure from the aforementioned dimensional conditions; thus some of these advantages are preserved up to differences of some 20% of the recommended thicknesses.
  • EXAMPLE
  • Layers of silicon and fused silica are used.
  • Four silicon substrates and four fused silica substrates are prepared by preparing the two surfaces of each substrate for molecular bonding. The two faces of one of the silicon substrates are roughened by chemical treatment with SCI (H2O/H2O2/NH4OH solution, in relative proportions 5-1-1) for 20 minutes at 70° C. The rear face of this substrate is then polished so that the bonding energy on the rear face is not downgraded.
  • Another silicon substrate is implanted with hydrogen ions at a dose of 6.1016 at/cm2 and at an energy of 76 keV. A stack B-A-A(rough)-B-A(implanted)-B-B-A is then constructed by successive molecular bonding.
  • An annealing treatment is applied for one hour at 500° C., which provokes separation of the assembly into two structures, respectively B-A-A(rough)-B-a(film of A) and A(less the thin layer)-B-B-A.
  • The required final product B-a is then detached by inserting a blade at the level of the previously roughened bonding interface of A(rough) and B-a. The FIGS. 3 and 4 curves correspond to calculations corresponding to the example described above, taking:
      • Young's modulus of silicon: 130 GPa
      • Young's modulus of silica: 70 GPa
      • Poisson's coefficient of silicon: 0.3
      • Poisson's coefficient of silica: 0.17
      • thickness of each layer of silicon: 750 microns
      • thickness of each layer of silica: 1200 microns
      • coefficient of thermal expansion of silica: 0.55.10−6
      • coefficient of thermal expansion of Si: varying between 2.4 10−6 and 4.2 10−6 along an increasing curve with the concave side facing down and toward the right, as indicated in the literature.

Claims (10)

  1. 1. A method of transferring a thin layer from a source substrate to a target substrate, wherein the source substrate includes a surface layer along a free surface thereof, the surface layer comprising a first material, and wherein the target substrate includes at least one surface layer along a free surface thereof, the one surface layer comprising a second material different from the first material, the method comprising:
    forming within the surface layer of the source substrate a weakened zone delimiting a thin layer with respect to the free surface;
    assembling the free surface of the source substrate with the free surface of the target substrate in a stack of alternating layers comprising the first and second materials so that layers of the first and second materials are on either side of an interface formed by bringing the free surfaces into intimate contact,
    wherein a cumulative thickness of the layers of the first material on a first side of the interface is substantially equal to a cumulative thickness of the layers of the first material on the other side of the interface and a cumulative thickness of the layers of the second material on the first side of the interface is substantially equal to a cumulative thickness of the layers of the second material on the other side of the interface, each of the alternating layers having thicknesses of at least 50 microns and at least 1000 times the depth at which the weakened zone is formed in the surface layer; and
    applying at least partially thermal energy to fracture the weakened zone and to detach the thin layer.
  2. 2. The method according to claim 1, wherein the alternating layers on one side of the interface comprise a first part, and the alternating layers on the other side of the interface comprise a second part, and wherein the stack of alternating layers is produced from a combination of materials, such that each of the first and second parts has a plane of symmetry parallel to the interface.
  3. 3. The method according to claim 1 or claim 2, wherein the stack of alternating layers comprises only layers formed of one or the other of the first and second materials.
  4. 4. The method according to claim 1, wherein the alternating layers on one side of the interface comprise a first part, and the layers on the other side of the interface comprise a second part, and wherein one of the first and second parts of the stack comprises two layers of the second material having substantially equal thicknesses with a layer of the first material between the two layers and having a thickness substantially equal to twice the thickness of the two layers of the second material, and the other of the first and second parts of the stack comprises two layers of the first material having substantially equal thicknesses with a layer of the second material between the two layers of the first material and having a thickness substantially equal to twice the thickness of the two layers of the first material.
  5. 5. The method according to claim 4, wherein the first part includes a double layer of the first material sandwiched between two identical layers of the second material and the second part includes a double layer of the second material sandwiched between two identical layers of the first material.
  6. 6. The method according to claim 1, wherein, after fracturing the weakened zone, a separation is provoked at a bonding interface within the part to which the thin layer has been transferred.
  7. 7. The method according to claim 6, wherein separation is provoked at an interface with a lower bonding energy formed within the assembly.
  8. 8. The method according to claim 6, wherein the part of the stack of alternating layers in which the thin layer has been separated is used in a new stack after forming a new weakened zone delimited with respect the free surface liberated by the fracture a thin layer.
  9. 9. The method according to claim 1, wherein forming the weakened zone comprises performing ionic implantation.
  10. 10. The method according to claim 1, wherein the first material comprises silicon.
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8048766B2 (en) 2003-06-24 2011-11-01 Commissariat A L'energie Atomique Integrated circuit on high performance chip
US8101503B2 (en) 1996-05-15 2012-01-24 Commissariat A L'energie Atomique Method of producing a thin layer of semiconductor material
US8309431B2 (en) 2003-10-28 2012-11-13 Commissariat A L'energie Atomique Method for self-supported transfer of a fine layer by pulsation after implantation or co-implantation
US8389379B2 (en) 2002-12-09 2013-03-05 Commissariat A L'energie Atomique Method for making a stressed structure designed to be dissociated
US8470712B2 (en) 1997-12-30 2013-06-25 Commissariat A L'energie Atomique Process for the transfer of a thin film comprising an inclusion creation step
US8664084B2 (en) 2005-09-28 2014-03-04 Commissariat A L'energie Atomique Method for making a thin-film element
US8778775B2 (en) 2006-12-19 2014-07-15 Commissariat A L'energie Atomique Method for preparing thin GaN layers by implantation and recycling of a starting substrate
US9385251B2 (en) 2012-08-27 2016-07-05 Samsung Electronics Co., Ltd. Flexible semiconductor devices and methods of manufacturing the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2961948B1 (en) * 2010-06-23 2012-08-03 Soitec Silicon On Insulator Method for processing material in a room comprises

Citations (96)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3957107A (en) * 1975-02-27 1976-05-18 The United States Of America As Represented By The Secretary Of The Air Force Thermal switch
US4006340A (en) * 1973-09-28 1977-02-01 Compagnie Industrielle Des Telecommunications Cit-Alcatel Device for the rapid depositing of oxides in thin layers which adhere well to plastic supports
US4074139A (en) * 1976-12-27 1978-02-14 Rca Corporation Apparatus and method for maskless ion implantation
US4244348A (en) * 1979-09-10 1981-01-13 Atlantic Richfield Company Process for cleaving crystalline materials
US4252837A (en) * 1976-03-23 1981-02-24 Warner-Lambert Company Blade shields
US4254590A (en) * 1978-11-13 1981-03-10 Bbc Brown Boveri & Company Limited Method for the production of a disk-shaped silicon semiconductor component with negative beveling
US4324631A (en) * 1979-07-23 1982-04-13 Spin Physics, Inc. Magnetron sputtering of magnetic materials
US4368083A (en) * 1980-02-01 1983-01-11 Commissariat A L'energie Atomique Process for doping semiconductors
US4500563A (en) * 1982-12-15 1985-02-19 Pacific Western Systems, Inc. Independently variably controlled pulsed R.F. plasma chemical vapor processing
US4508056A (en) * 1982-06-24 1985-04-02 Commissariat A L'energie Atomique Target holder with mechanical scanning
US4566403A (en) * 1985-01-30 1986-01-28 Sovonics Solar Systems Apparatus for microwave glow discharge deposition
US4567505A (en) * 1983-10-27 1986-01-28 The Board Of Trustees Of The Leland Stanford Junior University Heat sink and method of attaching heat sink to a semiconductor integrated circuit and the like
US4568563A (en) * 1983-08-02 1986-02-04 Standard Telephones And Cables Optical fibre manufacture
US4585945A (en) * 1982-12-10 1986-04-29 Commissariat A L'energie Atomique Process and apparatus for implanting particles in a solid
US4717683A (en) * 1986-09-23 1988-01-05 Motorola Inc. CMOS process
US4832253A (en) * 1987-04-03 1989-05-23 Bbc Brown Boveri Ag Method for manufacturing a laminar bond and apparatus for conducting the method
US4891329A (en) * 1988-11-29 1990-01-02 University Of North Carolina Method of forming a nonsilicon semiconductor on insulator structure
US4894709A (en) * 1988-03-09 1990-01-16 Massachusetts Institute Of Technology Forced-convection, liquid-cooled, microchannel heat sinks
US4904610A (en) * 1988-01-27 1990-02-27 General Instrument Corporation Wafer level process for fabricating passivated semiconductor devices
US4920396A (en) * 1987-04-13 1990-04-24 Nissan Motor Company, Limited CMOS having buried layer for carrier recombination
US4929566A (en) * 1989-07-06 1990-05-29 Harris Corporation Method of making dielectrically isolated integrated circuits using oxygen implantation and expitaxial growth
US4982090A (en) * 1988-02-05 1991-01-01 Gesellschaft Fur Strahlen- Und Umweltforschung Mbh (Gsf) Method and apparatus for the quantitative, depth differential analysis of solid samples with the use of two ion beams
US4996077A (en) * 1988-10-07 1991-02-26 Texas Instruments Incorporated Distributed ECR remote plasma processing and apparatus
US5013681A (en) * 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
US5015353A (en) * 1987-09-30 1991-05-14 The United States Of America As Represented By The Secretary Of The Navy Method for producing substoichiometric silicon nitride of preselected proportions
US5198371A (en) * 1990-09-24 1993-03-30 Biota Corp. Method of making silicon material with enhanced surface mobility by hydrogen ion implantation
US5200805A (en) * 1987-12-28 1993-04-06 Hughes Aircraft Company Silicon carbide:metal carbide alloy semiconductor and method of making the same
US5280819A (en) * 1990-05-09 1994-01-25 Lanxide Technology Company, Lp Methods for making thin metal matrix composite bodies and articles produced thereby
US5289247A (en) * 1991-06-28 1994-02-22 Canon Kabushiki Kaisha Image forming apparatus with changeable feed interval for continuous feed
US5300788A (en) * 1991-01-18 1994-04-05 Kopin Corporation Light emitting diode bars and arrays and method of making same
US5400458A (en) * 1993-03-31 1995-03-28 Minnesota Mining And Manufacturing Company Brush segment for industrial brushes
US5405802A (en) * 1992-01-31 1995-04-11 Canon Kabushiki Kaisha Process of fabricating a semiconductor substrate
US5494835A (en) * 1993-12-23 1996-02-27 Commissariat A L'energie Atomique Process for the production of a relief structure on a semiconductor material support
US5611316A (en) * 1993-12-28 1997-03-18 Honda Giken Kogyo Kabushiki Kaisha Gas fuel supply mechanism for gas combustion engine
US5618739A (en) * 1990-11-15 1997-04-08 Seiko Instruments Inc. Method of making light valve device using semiconductive composite substrate
US5622896A (en) * 1994-10-18 1997-04-22 U.S. Philips Corporation Method of manufacturing a thin silicon-oxide layer
US5714395A (en) * 1995-09-13 1998-02-03 Commissariat A L'energie Atomique Process for the manufacture of thin films of semiconductor material
US5741733A (en) * 1994-01-14 1998-04-21 Siemens Aktiengesellschaft Method for the production of a three-dimensional circuit arrangement
US5863832A (en) * 1996-06-28 1999-01-26 Intel Corporation Capping layer in interconnect system and method for bonding the capping layer onto the interconnect system
US5863830A (en) * 1994-09-22 1999-01-26 Commissariat A L'energie Atomique Process for the production of a structure having a thin semiconductor film on a substrate
US5877070A (en) * 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
US5880010A (en) * 1994-07-12 1999-03-09 Sun Microsystems, Inc. Ultrathin electronics
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
US5897331A (en) * 1996-11-08 1999-04-27 Midwest Research Institute High efficiency low cost thin film silicon solar cell design and method for making
US6010591A (en) * 1996-11-22 2000-01-04 Max-Planck-Gesellschaft Zur Foerderung Der Wissenschaften E.V. Method for the releasable bonding and subsequent separation of reversibly bonded and polished wafers and also a wafer structure and wafer
US6013954A (en) * 1997-03-31 2000-01-11 Nec Corporation Semiconductor wafer having distortion-free alignment regions
US6013563A (en) * 1997-05-12 2000-01-11 Silicon Genesis Corporation Controlled cleaning process
US6020252A (en) * 1996-05-15 2000-02-01 Commissariat A L'energie Atomique Method of producing a thin layer of semiconductor material
US6033974A (en) * 1997-05-12 2000-03-07 Silicon Genesis Corporation Method for controlled cleaving process
US6054370A (en) * 1998-06-30 2000-04-25 Intel Corporation Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer
US6054363A (en) * 1996-11-15 2000-04-25 Canon Kabushiki Kaisha Method of manufacturing semiconductor article
US6190998B1 (en) * 1996-05-15 2001-02-20 Commissariat A L'energie Atomique Method for achieving a thin film of solid material and applications of this method
US6197695B1 (en) * 1998-10-20 2001-03-06 Commissariat A L'energie Atomique Process for the manufacture of passive and active components on the same insulating substrate
US6198159B1 (en) * 1997-03-28 2001-03-06 Ube Industries, Ltd. Bonded wafer, process for producing same and substrate
US6200878B1 (en) * 1997-12-26 2001-03-13 Canon Kabushiki Kaisha SOI substrate processing method
US6204079B1 (en) * 1998-07-30 2001-03-20 Commissariat A L'energie Atomique Selective transfer of elements from one support to another support
US20020001221A1 (en) * 2000-06-29 2002-01-03 Shingo Hashimoto Load-less four-transistor memory cell
US20020000646A1 (en) * 2000-02-02 2002-01-03 Raytheon Company, A Delware Corporation Vacuum package fabrication of integrated circuit components
US6346458B1 (en) * 1998-12-31 2002-02-12 Robert W. Bower Transposed split of ion cut materials
US20020025604A1 (en) * 2000-08-30 2002-02-28 Sandip Tiwari Low temperature semiconductor layering and three-dimensional electronic circuits using the layering
US6362082B1 (en) * 1999-06-28 2002-03-26 Intel Corporation Methodology for control of short channel effects in MOS transistors
US6362077B1 (en) * 1998-10-16 2002-03-26 Commissariat A L'atomique Structure comprising a thin layer of material made up of conductive zones and insulating zones and a method of manufacturing such a structure
US20020048948A1 (en) * 2000-08-09 2002-04-25 Kostat Semiconductor Co., Ltd. Tape having implantable conductive lands for semiconductor packaging process and method for manufacturing the same
US6504235B2 (en) * 1997-07-25 2003-01-07 Hughes Electronics Corporation Passivation layer and process for semiconductor devices
US6513564B2 (en) * 1999-08-10 2003-02-04 Silicon Genesis Corporation Nozzle for cleaving substrates
US6529646B1 (en) * 1999-02-23 2003-03-04 Marconi Caswell Limited Optical modulator
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
US6548375B1 (en) * 2000-03-16 2003-04-15 Hughes Electronics Corporation Method of preparing silicon-on-insulator substrates particularly suited for microwave applications
US20030077885A1 (en) * 2000-05-30 2003-04-24 Bernard Aspar Embrittled substrate and method for making same
US20040009649A1 (en) * 2002-07-12 2004-01-15 Kub Francis J. Wafer bonding of thinned electronic materials and circuits to high performance substrates
US20040029358A1 (en) * 2002-08-10 2004-02-12 Park Jea-Gun Method of fabricating nano SOI wafer and nano SOI wafer fabricated by the same
US6846690B2 (en) * 2001-12-03 2005-01-25 Stmicroelectronics S.A. Integrated circuit comprising an auxiliary component, for example a passive component or a microelectromechanical system, placed above an electronic chip, and the corresponding fabrication process
US20050029224A1 (en) * 2001-04-13 2005-02-10 Bernard Aspar Detachable substrate or detachable structure and method for the production thereof
US20050042842A1 (en) * 2003-08-21 2005-02-24 Ryan Lei Germanium on insulator fabrication via epitaxial germanium bonding
US20050067377A1 (en) * 2003-09-25 2005-03-31 Ryan Lei Germanium-on-insulator fabrication utilizing wafer bonding
US6991956B2 (en) * 2002-07-09 2006-01-31 S.O.I.Tec Silicon On Insulator Technologies S.A. Methods for transferring a thin layer from a wafer having a buffer layer
US7018909B2 (en) * 2003-02-28 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Forming structures that include a relaxed or pseudo-relaxed layer on a substrate
US7029980B2 (en) * 2003-09-25 2006-04-18 Freescale Semiconductor Inc. Method of manufacturing SOI template layer
US7029548B2 (en) * 2000-07-12 2006-04-18 Commissariat A L'energie Atomique Method for cutting a block of material and forming a thin film
US20070020895A1 (en) * 2003-06-06 2007-01-25 Commissariat A L'energie Atomique Method for production of a very thin layer with thinning by means of induced self-support
US20070017438A1 (en) * 2005-07-19 2007-01-25 The Regents Of The University Of California Method of forming dislocation-free strained thin films
USRE39484E1 (en) * 1991-09-18 2007-02-06 Commissariat A L'energie Atomique Process for the production of thin semiconductor material films
US20070037363A1 (en) * 2002-11-07 2007-02-15 Bernard Aspar Method for forming a brittle zone in a substrate by co-implantation
US20070087528A1 (en) * 2002-12-28 2007-04-19 Kim Sarah E Method and structure for vertically-stacked device contact
US20070087525A1 (en) * 2005-09-01 2007-04-19 International Business Machines Corporation Method and apparatus for making coplanar isolated regions of different semiconductor materials on a substrate
US20070087526A1 (en) * 2005-10-18 2007-04-19 Nabil Chhaimi Method of recycling an epitaxied donor wafer
US20080017306A1 (en) * 2002-10-09 2008-01-24 The Board Of Trustees Of The University Of Illinoi Microfluidic systems and components
US20080020547A1 (en) * 2004-10-21 2008-01-24 Marek Kostrzewa Method Of Transferring At Least One Object Of Micrometric Or Millimetric Size By Means Of A Polymer Handle
US7348260B2 (en) * 2003-02-28 2008-03-25 S.O.I.Tec Silicon On Insulator Technologies Method for forming a relaxed or pseudo-relaxed useful layer on a substrate
US7476596B2 (en) * 2000-08-22 2009-01-13 President And Fellows Of Harvard College Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors, and fabricating such devices
US7494897B2 (en) * 2002-12-24 2009-02-24 Commissariat A L'energie Atomique Method of producing mixed substrates and structure thus obtained
US7521292B2 (en) * 2004-06-04 2009-04-21 The Board Of Trustees Of The University Of Illinois Stretchable form of single crystal silicon for high performance electronics on rubber substrates
US20100025228A1 (en) * 2006-12-19 2010-02-04 Tauzin Aurelie Method for Preparing Thin GaN Layers by Implantation and Recycling of a Starting Substrate
US7670930B2 (en) * 2006-03-29 2010-03-02 Commissariat A L 'energie Atomique Method of detaching a thin film by melting precipitates
US7883994B2 (en) * 1997-12-30 2011-02-08 Commissariat A L'energie Atomique Process for the transfer of a thin film
US7902038B2 (en) * 2001-04-13 2011-03-08 Commissariat A L'energie Atomique Detachable substrate with controlled mechanical strength and method of producing same

Family Cites Families (207)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3915757A (en) 1972-08-09 1975-10-28 Niels N Engel Ion plating method and product therefrom
US3913520A (en) 1972-08-14 1975-10-21 Precision Thin Film Corp High vacuum deposition apparatus
US3993909A (en) 1973-03-16 1976-11-23 U.S. Philips Corporation Substrate holder for etching thin films
US3901423A (en) 1973-11-26 1975-08-26 Purdue Research Foundation Method for fracturing crystalline materials
US4121334A (en) 1974-12-17 1978-10-24 P. R. Mallory & Co. Inc. Application of field-assisted bonding to the mass production of silicon type pressure transducers
US4170662A (en) 1974-11-05 1979-10-09 Eastman Kodak Company Plasma plating
US4039416A (en) 1975-04-21 1977-08-02 White Gerald W Gasless ion plating
US4028149A (en) 1976-06-30 1977-06-07 Ibm Corporation Process for forming monocrystalline silicon carbide on silicon substrates
US4108751A (en) 1977-06-06 1978-08-22 King William J Ion beam implantation-sputtering
US4179324A (en) 1977-11-28 1979-12-18 Spire Corporation Process for fabricating thin film and glass sheet laminate
JPS55104057A (en) 1979-02-02 1980-08-09 Hitachi Ltd Ion implantation device
NL179832C (en) 1979-08-02 1986-11-17 Balzers Hochvakuum Process for the application of hard, wear-resistant coatings on a substrate.
FR2506344B2 (en) 1980-02-01 1986-07-11 Commissariat Energie Atomique semiconductor doping process
US4342631A (en) 1980-06-16 1982-08-03 Illinois Tool Works Inc. Gasless ion plating process and apparatus
US4471003A (en) 1980-11-25 1984-09-11 Cann Gordon L Magnetoplasmadynamic apparatus and process for the separation and deposition of materials
FR2501727B1 (en) 1981-03-13 1983-06-03 Vide Traitement
US4361600A (en) 1981-11-12 1982-11-30 General Electric Company Method of making integrated circuits
US4412868A (en) 1981-12-23 1983-11-01 General Electric Company Method of making integrated circuits utilizing ion implantation and selective epitaxial growth
US4486247A (en) 1982-06-21 1984-12-04 Westinghouse Electric Corp. Wear resistant steel articles with carbon, oxygen and nitrogen implanted in the surface thereof
FR2537768B1 (en) 1982-12-08 1985-02-08 Commissariat Energie Atomique
DE3246480C2 (en) 1982-12-15 1989-05-24 Wacker-Chemitronic Gesellschaft Fuer Elektronik-Grundstoffe Mbh, 8263 Burghausen, De
US4468309A (en) 1983-04-22 1984-08-28 White Engineering Corporation Method for resisting galling
JPS6317243Y2 (en) 1983-11-24 1988-05-16
FR2558263B1 (en) 1984-01-12 1986-04-25 Commissariat Energie Atomique directional accelerometer and process for its manufacture by microlithography
GB2155024A (en) 1984-03-03 1985-09-18 Standard Telephones Cables Ltd Surface treatment of plastics materials
FR2563377B1 (en) 1984-04-19 1987-01-23 Commissariat Energie Atomique Process for manufacturing an insulating layer buried in a semiconductor substrate by ion implantation
US4542863A (en) 1984-07-23 1985-09-24 Larson Edwin L Pipe-thread sealing tape reel with tape retarding element
US4837172A (en) 1986-07-18 1989-06-06 Matsushita Electric Industrial Co., Ltd. Method for removing impurities existing in semiconductor substrate
US4764394A (en) 1987-01-20 1988-08-16 Wisconsin Alumni Research Foundation Method and apparatus for plasma source ion implantation
US4847792A (en) 1987-05-04 1989-07-11 Texas Instruments Incorporated Process and apparatus for detecting aberrations in production process operations
EP0293049B1 (en) 1987-05-27 1993-09-29 NobelTech Systems Aktiebolag A light detecting and light direction determining device
FR2616590B1 (en) 1987-06-15 1990-03-02 Commissariat Energie Atomique Process for manufacturing a buried insulating layer in a semiconductor substrate by ion implantation, semiconductor structure comprising this layer
US4956698A (en) 1987-07-29 1990-09-11 The United States Of America As Represented By The Department Of Commerce Group III-V compound semiconductor device having p-region formed by Be and Group V ions
US4846928A (en) 1987-08-04 1989-07-11 Texas Instruments, Incorporated Process and apparatus for detecting aberrations in production process operations
US4887005A (en) 1987-09-15 1989-12-12 Rough J Kirkwood H Multiple electrode plasma reactor power distribution system
US5138422A (en) 1987-10-27 1992-08-11 Nippondenso Co., Ltd. Semiconductor device which includes multiple isolated semiconductor segments on one chip
GB8725497D0 (en) 1987-10-30 1987-12-02 Atomic Energy Authority Uk Isolation of silicon
JP2666945B2 (en) 1988-02-08 1997-10-22 株式会社東芝 A method of manufacturing a semiconductor device
US4853250A (en) 1988-05-11 1989-08-01 Universite De Sherbrooke Process of depositing particulate material on a substrate
NL8802028A (en) 1988-08-16 1990-03-16 Philips Nv A method for manufacturing a device.
JP2670623B2 (en) 1988-09-19 1997-10-29 アネルバ株式会社 Microwave plasma processing apparatus
US4952273A (en) 1988-09-21 1990-08-28 Microscience, Inc. Plasma generation in electron cyclotron resonance
NL8900388A (en) 1989-02-17 1990-09-17 Philips Nv A method for connecting two objects.
JPH02302044A (en) 1989-05-16 1990-12-14 Fujitsu Ltd Manufacture of semiconductor device
JPH0580133B2 (en) 1989-07-25 1993-11-08 Shinetsu Handotai Kk
US4948458A (en) 1989-08-14 1990-08-14 Lam Research Corporation Method and apparatus for producing magnetically-coupled planar plasma
US5036023A (en) 1989-08-16 1991-07-30 At&T Bell Laboratories Rapid thermal processing method of making a semiconductor device
US5310446A (en) 1990-01-10 1994-05-10 Ricoh Company, Ltd. Method for producing semiconductor film
JPH0650738B2 (en) 1990-01-11 1994-06-29 株式会社東芝 Semiconductor device and manufacturing method thereof
US5034343A (en) 1990-03-08 1991-07-23 Harris Corporation Manufacturing ultra-thin wafer using a handle wafer
CN1018844B (en) 1990-06-02 1992-10-28 中国科学院兰州化学物理研究所 Antirust dry film lubricant
US5131968A (en) 1990-07-31 1992-07-21 Motorola, Inc. Gradient chuck method for wafer bonding employing a convex pressure
JPH0719739B2 (en) 1990-09-10 1995-03-06 信越半導体株式会社 Method of manufacturing a bonded wafer
DE4106288C2 (en) 1991-02-28 2001-05-31 Bosch Gmbh Robert Sensor for measuring pressures or accelerations
JP2812405B2 (en) 1991-03-15 1998-10-22 信越半導体株式会社 A method of manufacturing a semiconductor substrate
US5110748A (en) 1991-03-28 1992-05-05 Honeywell Inc. Method for fabricating high mobility thin film transistors as integrated drivers for active matrix display
US5442205A (en) 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
US5256581A (en) 1991-08-28 1993-10-26 Motorola, Inc. Silicon film with improved thickness control
JPH05235312A (en) * 1992-02-19 1993-09-10 Fujitsu Ltd Semiconductor substrate and its manufacture
US5614019A (en) 1992-06-08 1997-03-25 Air Products And Chemicals, Inc. Method for the growth of industrial crystals
US5234535A (en) * 1992-12-10 1993-08-10 International Business Machines Corporation Method of producing a thin silicon-on-insulator layer
WO1994017558A1 (en) 1993-01-29 1994-08-04 The Regents Of The University Of California Monolithic passive component
FR2715502B1 (en) 1994-01-26 1996-04-05 Commissariat Energie Atomique Structure having cavities and method of making such a structure.
FR2715501B1 (en) 1994-01-26 1996-04-05 Commissariat Energie Atomique A process for depositing semiconductor blades on a support.
FR2715503B1 (en) 1994-01-26 1996-04-05 Commissariat Energie Atomique Substrate for integrated components comprising a thin layer and its production method.
JPH0851103A (en) 1994-08-08 1996-02-20 Fuji Electric Co Ltd Method for forming thin film
US5524339A (en) 1994-09-19 1996-06-11 Martin Marietta Corporation Method for protecting gallium arsenide mmic air bridge structures
US5567654A (en) 1994-09-28 1996-10-22 International Business Machines Corporation Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging
EP0799495A4 (en) 1994-11-10 1999-11-03 Lawrence Semiconductor Researc Silicon-germanium-carbon compositions and processes thereof
DE69526485D1 (en) 1994-12-12 2002-05-29 Advanced Micro Devices Inc A process for producing a buried oxide layers
JP3381443B2 (en) * 1995-02-02 2003-02-24 ソニー株式会社 Method of separating the semiconductor layer from the substrate, a manufacturing method and a soi method of manufacturing a substrate of a semiconductor device
FR2736934B1 (en) 1995-07-21 1997-08-22 Commissariat Energie Atomique Process for manufacturing a structure with a useful layer held distance from a substrate by abutments, and uncoupling of such a layer
JP3352340B2 (en) 1995-10-06 2002-12-03 キヤノン株式会社 Semiconductor substrate and a method of manufacturing the same
FR2744285B1 (en) 1996-01-25 1998-03-06 Commissariat Energie Atomique Method transfer of a thin layer from an initial substrate to a final substrate
JP3293736B2 (en) 1996-02-28 2002-06-17 キヤノン株式会社 A manufacturing method and a bonded substrate of the semiconductor substrate
FR2747506B1 (en) 1996-04-11 1998-05-15 Commissariat Energie Atomique Method of obtaining a thin film of semiconductor material in particular comprising electronic components
US6127199A (en) 1996-11-12 2000-10-03 Seiko Epson Corporation Manufacturing method of active matrix substrate, active matrix substrate and liquid crystal display device
DE69710031D1 (en) * 1996-11-15 2002-03-14 Canon Kk A method for transferring a semiconductor layer by means of silicon-on-insulator (SOI) technology
KR100232886B1 (en) 1996-11-23 1999-12-01 김영환 Soi wafer fabricating method
DE19648759A1 (en) 1996-11-25 1998-05-28 Max Planck Gesellschaft Method of manufacturing microstructures
FR2756847B1 (en) 1996-12-09 1999-01-08 Commissariat Energie Atomique A method of separating at least two elements of a structure in contact with each other by ion implantation
CA2225131C (en) 1996-12-18 2002-01-01 Canon Kabushiki Kaisha Process for producing semiconductor article
FR2758907B1 (en) 1997-01-27 1999-05-07 Commissariat Energie Atomique Method of obtaining a thin film, including semiconductor, having a protected area of ​​the ions and involving an ion implantation step
JP3114643B2 (en) 1997-02-20 2000-12-04 日本電気株式会社 Structure and manufacturing method of a semiconductor substrate
US6251754B1 (en) * 1997-05-09 2001-06-26 Denso Corporation Semiconductor substrate manufacturing method
US6150239A (en) 1997-05-31 2000-11-21 Max Planck Society Method for the transfer of thin layers monocrystalline material onto a desirable substrate
US6054369A (en) 1997-06-30 2000-04-25 Intersil Corporation Lifetime control for semiconductor devices
WO1999001893A8 (en) 1997-06-30 1999-07-22 Max Planck Gesellschaft Method for producing layered structures on a substrate, substrate and semiconductor components produced according to said method
US6097096A (en) 1997-07-11 2000-08-01 Advanced Micro Devices Metal attachment method and structure for attaching substrates at low temperatures
US6103599A (en) 1997-07-25 2000-08-15 Silicon Genesis Corporation Planarizing technique for multilayered substrates
EP0895282A3 (en) 1997-07-30 2000-01-26 Canon Kabushiki Kaisha Method of preparing a SOI substrate by using a bonding process, and SOI substrate produced by the same
FR2767416B1 (en) 1997-08-12 1999-10-01 Commissariat Energie Atomique Process for manufacturing a thin film of solid material
FR2767604B1 (en) 1997-08-19 2000-12-01 Commissariat Energie Atomique A treatment method for the molecular bonding and takeoff of two structures
JP3697034B2 (en) 1997-08-26 2005-09-21 キヤノン株式会社 A method of manufacturing a projection having a microscopic aperture, and a probe or a multi-probe according to their
US5981400A (en) 1997-09-18 1999-11-09 Cornell Research Foundation, Inc. Compliant universal substrate for epitaxial growth
US5920764A (en) 1997-09-30 1999-07-06 International Business Machines Corporation Process for restoring rejected wafers in line for reuse as new
JP2998724B2 (en) * 1997-11-10 2000-01-11 日本電気株式会社 Method for producing a laminated soi board
FR2771852B1 (en) 1997-12-02 1999-12-31 Commissariat Energie Atomique Method selective transfer of a microstructure formed on an initial substrate to a final substrate
JP4173573B2 (en) 1997-12-03 2008-10-29 株式会社ナノテム Method for producing a porous grinder
US6418999B1 (en) 1997-12-26 2002-07-16 Cannon Kabushiki Kaisha Sample separating apparatus and method, and substrate manufacturing method
US6071795A (en) 1998-01-23 2000-06-06 The Regents Of The University Of California Separation of thin films from transparent substrates by selective optical processing
FR2774510B1 (en) 1998-02-02 2001-10-26 Soitec Silicon On Insulator substrate processing method, in particular semiconductor
FR2774797B1 (en) 1998-02-11 2000-03-10 Commissariat Energie Atomique A method of making a set several magnetic heads and all multi-head obtained by this method
CN1175498C (en) 1998-02-18 2004-11-10 佳能株式会社 Composite member, its separation method, and preparation method of semiconductor substrate by utilization thereof
JP3809733B2 (en) 1998-02-25 2006-08-16 セイコーエプソン株式会社 Peeling method of a thin film transistor
JPH11307747A (en) 1998-04-17 1999-11-05 Nec Corp Soi substrate and production thereof
US6057212A (en) 1998-05-04 2000-05-02 International Business Machines Corporation Method for making bonded metal back-plane substrates
US5909627A (en) 1998-05-18 1999-06-01 Philips Electronics North America Corporation Process for production of thin layers of semiconductor material
DE19840421C2 (en) 1998-06-22 2000-05-31 Fraunhofer Ges Forschung A process for the production of thin layers of substrate and a suitable substrate assembly for
US6118181A (en) 1998-07-29 2000-09-12 Agilent Technologies, Inc. System and method for bonding wafers
US6271101B1 (en) 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
EP0989593A3 (en) 1998-09-25 2002-01-02 Canon Kabushiki Kaisha Substrate separating apparatus and method, and substrate manufacturing method
US6276345B1 (en) 1998-12-23 2001-08-21 Kohler Co. Dual fuel system for an internal combustion engine
FR2789518B1 (en) 1999-02-10 2003-06-20 Commissariat Energie Atomique multilayer structure constraints internal Controlled and method of making such a structure
US6586841B1 (en) 2000-02-23 2003-07-01 Onix Microsystems, Inc. Mechanical landing pad formed on the underside of a MEMS device
JP3532788B2 (en) 1999-04-13 2004-05-31 シャープ株式会社 Semiconductor device and manufacturing method thereof
WO2000063965A1 (en) 1999-04-21 2000-10-26 Silicon Genesis Corporation Treatment method of cleaved film for the manufacture of substrates
JP2001015721A (en) 1999-04-30 2001-01-19 Canon Inc Separation method of composite member and manufacture of thin film
US6310387B1 (en) 1999-05-03 2001-10-30 Silicon Wave, Inc. Integrated circuit inductor with high self-resonance frequency
US6664169B1 (en) 1999-06-08 2003-12-16 Canon Kabushiki Kaisha Process for producing semiconductor member, process for producing solar cell, and anodizing apparatus
FR2796491B1 (en) 1999-07-12 2001-08-31 Commissariat Energie Atomique Method for peeling the two elements and device for its implementation
US6323108B1 (en) 1999-07-27 2001-11-27 The United States Of America As Represented By The Secretary Of The Navy Fabrication ultra-thin bonded semiconductor layers
US6287940B1 (en) 1999-08-02 2001-09-11 Honeywell International Inc. Dual wafer attachment process
FR2797347B1 (en) 1999-08-04 2001-11-23 Commissariat Energie Atomique A method of transferring a thin layer comprising a step of surfragililisation
WO2001011930A9 (en) 1999-08-10 2001-09-20 Silicon Genesis Corp A cleaving process to fabricate multilayered substrates using low implantation doses
EP1077475A3 (en) 1999-08-11 2003-04-02 Applied Materials, Inc. Method of micromachining a multi-part cavity
KR100413789B1 (en) 1999-11-01 2003-12-31 삼성전자주식회사 High vacuum packaging microgyroscope and manufacturing method thereof
DE19958803C1 (en) 1999-12-07 2001-08-30 Fraunhofer Ges Forschung Method and apparatus for handling semiconductor substrates in the processing and / or handling
JP2001196566A (en) 2000-01-07 2001-07-19 Sony Corp Semiconductor substrate and method of manufacturing the same
US6306720B1 (en) 2000-01-10 2001-10-23 United Microelectronics Corp. Method for forming capacitor of mixed-mode device
JP3975634B2 (en) * 2000-01-25 2007-09-12 信越半導体株式会社 Production method of semiconductor wafer
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US6500694B1 (en) 2000-03-22 2002-12-31 Ziptronix, Inc. Three dimensional device integration method and integrated device
EP1273035B1 (en) 2000-04-14 2012-09-12 Soitec Method for cutting out at least a thin layer in a substrate or ingot, in particular made of semiconductor material(s)
US6407929B1 (en) 2000-06-29 2002-06-18 Intel Corporation Electronic package having embedded capacitors and method of fabrication therefor
JP3440057B2 (en) 2000-07-05 2003-08-25 シャープ株式会社 Semiconductor device and manufacturing method thereof
FR2816445B1 (en) 2000-11-06 2003-07-25 Commissariat Energie Atomique Process for manufacturing a structure comprising a thin STACKED layer adhered to a target substrate
FR2818010B1 (en) 2000-12-08 2003-09-05 Commissariat Energie Atomique A method of making a thin layer involving the introduction of gaseous species
US7139947B2 (en) 2000-12-22 2006-11-21 Intel Corporation Test access port
FR2819099B1 (en) 2000-12-28 2003-09-26 Commissariat Energie Atomique Process for producing a stacked structure
US6774010B2 (en) 2001-01-25 2004-08-10 International Business Machines Corporation Transferable device-containing layer for silicon-on-insulator applications
DE10104868A1 (en) 2001-02-03 2002-08-22 Bosch Gmbh Robert Micromechanical component as well as a process for producing a micromechanical component
JP2002270553A (en) 2001-03-13 2002-09-20 Mitsubishi Gas Chem Co Inc Manufacturing method of electronic component
JP2002305293A (en) * 2001-04-06 2002-10-18 Canon Inc Method of manufacturing semiconductor member, and method of manufacturing semiconductor device
US6734762B2 (en) 2001-04-09 2004-05-11 Motorola, Inc. MEMS resonators and method for manufacturing MEMS resonators
FR2823373B1 (en) 2001-04-10 2005-02-04 Soitec Silicon On Insulator A layer of a substrate section, and METHOD
US6759282B2 (en) 2001-06-12 2004-07-06 International Business Machines Corporation Method and structure for buried circuits and devices
FR2828428B1 (en) 2001-08-07 2003-10-17 Soitec Silicon On Insulator substrates removal device and method combines
US6744114B2 (en) 2001-08-29 2004-06-01 Honeywell International Inc. Package with integrated inductor and/or capacitor
FR2830983B1 (en) 2001-10-11 2004-05-14 Commissariat Energie Atomique thin film manufacturing method comprising the microcomponents
DE10153319B4 (en) 2001-10-29 2011-02-17 austriamicrosystems AG, Schloss Premstätten microsensor
US6593212B1 (en) * 2001-10-29 2003-07-15 The United States Of America As Represented By The Secretary Of The Navy Method for making electro-optical devices using a hydrogenion splitting technique
US6947365B2 (en) 2001-11-09 2005-09-20 Via Technologies, Inc. Method for protecting phase lock loop in optical system
KR100442105B1 (en) 2001-12-03 2004-07-27 삼성전자주식회사 Method of forming soi type substrate
US6953735B2 (en) 2001-12-28 2005-10-11 Semiconductor Energy Laboratory Co., Ltd. Method for fabricating a semiconductor device by transferring a layer to a support with curvature
FR2834820B1 (en) 2002-01-16 2005-03-18 layers cleavage Method for a slice of material
FR2835097B1 (en) 2002-01-23 2005-10-14 Method optimizes transfer of a thin layer of silicon carbide on a host substrate
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6596569B1 (en) 2002-03-15 2003-07-22 Lucent Technologies Inc. Thin film transistors
US6607969B1 (en) 2002-03-18 2003-08-19 The United States Of America As Represented By The Secretary Of The Navy Method for making pyroelectric, electro-optical and decoupling capacitors using thin film transfer and hydrogen ion splitting techniques
US6767749B2 (en) 2002-04-22 2004-07-27 The United States Of America As Represented By The Secretary Of The Navy Method for making piezoelectric resonator and surface acoustic wave device using hydrogen implant layer splitting
FR2838865B1 (en) 2002-04-23 2005-10-14 Soitec Silicon On Insulator Process for manufacturing a substrate with useful layer to support high resistivity
US6632082B1 (en) 2002-05-01 2003-10-14 Colibri Corporation Lighter and method of use
US6645831B1 (en) 2002-05-07 2003-11-11 Intel Corporation Thermally stable crystalline defect-free germanium bonded to silicon and silicon dioxide
US7157119B2 (en) 2002-06-25 2007-01-02 Ppg Industries Ohio, Inc. Method and compositions for applying multiple overlying organic pigmented decorations on ceramic substrates
US6953736B2 (en) 2002-07-09 2005-10-11 S.O.I.Tec Silicon On Insulator Technologies S.A. Process for transferring a layer of strained semiconductor material
US7018910B2 (en) 2002-07-09 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Transfer of a thin layer from a wafer comprising a buffer layer
EP1403684A1 (en) 2002-09-30 2004-03-31 Corning Incorporated High-speed optical modulator
US7176108B2 (en) 2002-11-07 2007-02-13 Soitec Silicon On Insulator Method of detaching a thin film at moderate temperature after co-implantation
FR2847076B1 (en) 2002-11-07 2005-02-18 Soitec Silicon On Insulator Process for the detachment of a thin layer at moderate temperatures after co-implantation
FR2848337B1 (en) * 2002-12-09 2005-09-09 Commissariat Energie Atomique Method of producing a complex structure by assembling tensioned structures
FR2848336B1 (en) 2002-12-09 2005-10-28 Commissariat Energie Atomique Method of realization of a constraint structure destiny has to be dissociated
US20040126708A1 (en) 2002-12-31 2004-07-01 3M Innovative Properties Company Method for modifying the surface of a polymeric substrate
CN100483666C (en) 2003-01-07 2009-04-29 S.O.I.Tec绝缘体上硅技术公司 Recycling of a wafer comprising a multi-layer structure after taking-off a thin layer
US6995427B2 (en) 2003-01-29 2006-02-07 S.O.I.Tec Silicon On Insulator Technologies S.A. Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating same
US7071077B2 (en) 2003-03-26 2006-07-04 S.O.I.Tec Silicon On Insulator Technologies S.A. Method for preparing a bonding surface of a semiconductor layer of a wafer
KR20060007428A (en) 2003-05-06 2006-01-24 캐논 가부시끼가이샤 Substrate, manufacturing method therefor, and semiconductor device
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
FR2856192B1 (en) * 2003-06-11 2005-07-29 Soitec Silicon On Insulator heterogeneous structure and structure making method obtained by such a process
FR2856844B1 (en) 2003-06-24 2006-02-17 Commissariat Energie Atomique Integrated circuit chip high performance
FR2856841A1 (en) 2003-06-24 2004-12-31 Commissariat Energie Atomique Process for producing a stacked structure by transfer of a thin layer.
US20040262686A1 (en) 2003-06-26 2004-12-30 Mohamad Shaheen Layer transfer technique
FR2857953B1 (en) 2003-07-21 2006-01-13 Commissariat Energie Atomique STACKED structure, and process for the manufacture
EP1652230A2 (en) 2003-07-29 2006-05-03 S.O.I.Tec Silicon on Insulator Technologies Method for obtaining a thin high-quality layer by co-implantation and thermal annealing
US7052978B2 (en) 2003-08-28 2006-05-30 Intel Corporation Arrangements incorporating laser-induced cleaving
FR2861497B1 (en) 2003-10-28 2006-02-10 Soitec Silicon On Insulator Process for catastrophic transfer of a thin layer after co-implantation
CN100459042C (en) 2003-12-16 2009-02-04 Nxp股份有限公司 Method for forming a strained Si-channel in a MOFSET structure
US7772087B2 (en) 2003-12-19 2010-08-10 Commissariat A L'energie Atomique Method of catastrophic transfer of a thin film after co-implantation
FR2864970B1 (en) * 2004-01-09 2006-03-03 Soitec Silicon On Insulator Substrate carrier has determined coefficient of thermal expansion
WO2005078786A1 (en) 2004-01-16 2005-08-25 International Business Machines Corporation Method of forming thin sgoi wafers with high relaxation and low stacking fault defect density
KR100631922B1 (en) * 2004-02-23 2006-10-04 삼성전자주식회사 Multi-layer circuit board having improved thermal spreading performance and manufacturing method therefore
FR2868202B1 (en) 2004-03-25 2006-05-26 Commissariat Energie Atomique Method of preparing a layer of silicon dioxide by oxidation at high temperature on a substrate presenting at least the surface of the germanium or germanium alloy sicicium-.
FR2871172B1 (en) 2004-06-03 2006-09-22 Soitec Silicon On Insulator Medium hybrid epitaxy and process for its manufacturing
US6893936B1 (en) 2004-06-29 2005-05-17 International Business Machines Corporation Method of Forming strained SI/SIGE on insulator with silicon germanium buffer
FR2876220B1 (en) 2004-10-06 2007-09-28 Commissariat Energie Atomique A method for manufacture of stacked composite structures, a variety of insulating areas and / or areas of localized vertical electrical conduction.
FR2876219B1 (en) 2004-10-06 2006-11-24 Commissariat Energie Atomique A method for manufacture of stacked composite structures, a variety of insulating areas and / or areas of localized vertical electrical conduction.
DE602004011353T2 (en) * 2004-10-19 2008-05-15 S.O.I. Tec Silicon On Insulator Technologies S.A. A process for preparing a strained silicon layer on a substrate and Intermediate
FR2888400B1 (en) * 2005-07-08 2007-10-19 Soitec Silicon On Insulator Method layer Levy
FR2889887B1 (en) 2005-08-16 2007-11-09 Commissariat Energie Atomique method for transferring a thin layer on a support
FR2891281B1 (en) 2005-09-28 2007-12-28 Commissariat Energie Atomique Process for manufacturing a thin-film element.
DE602006000423T2 (en) 2006-03-31 2008-05-21 S.O.I.Tec. Silicon On Insulator Technologies S.A. A process for producing a composite material and method for selecting a wafer
EP1928020A1 (en) 2006-11-30 2008-06-04 S.O.I.TEC. Silicon on Insulator Technologies S.A. Method of manufacturing a semiconductor heterostructure
FR2922359B1 (en) 2007-10-12 2009-12-18 Commissariat Energie Atomique Method of manufacturing a micro-electronic structure involving molecular bonding
FR2925221B1 (en) 2007-12-17 2010-02-19 Commissariat Energie Atomique A method of transferring a thin layer
FR2934924B1 (en) * 2008-08-06 2011-04-22 Soitec Silicon On Insulator Process for multi implantation in a substrate.
RU128757U1 (en) 2012-12-18 2013-05-27 Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Нижегородский государственный технический университет им. Р.Е. Алексеева" НГТУ The control system state discrete source signals

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4006340A (en) * 1973-09-28 1977-02-01 Compagnie Industrielle Des Telecommunications Cit-Alcatel Device for the rapid depositing of oxides in thin layers which adhere well to plastic supports
US3957107A (en) * 1975-02-27 1976-05-18 The United States Of America As Represented By The Secretary Of The Air Force Thermal switch
US4252837A (en) * 1976-03-23 1981-02-24 Warner-Lambert Company Blade shields
US4074139A (en) * 1976-12-27 1978-02-14 Rca Corporation Apparatus and method for maskless ion implantation
US4254590A (en) * 1978-11-13 1981-03-10 Bbc Brown Boveri & Company Limited Method for the production of a disk-shaped silicon semiconductor component with negative beveling
US4324631A (en) * 1979-07-23 1982-04-13 Spin Physics, Inc. Magnetron sputtering of magnetic materials
US4244348A (en) * 1979-09-10 1981-01-13 Atlantic Richfield Company Process for cleaving crystalline materials
US4368083A (en) * 1980-02-01 1983-01-11 Commissariat A L'energie Atomique Process for doping semiconductors
US4508056A (en) * 1982-06-24 1985-04-02 Commissariat A L'energie Atomique Target holder with mechanical scanning
US4585945A (en) * 1982-12-10 1986-04-29 Commissariat A L'energie Atomique Process and apparatus for implanting particles in a solid
US4500563A (en) * 1982-12-15 1985-02-19 Pacific Western Systems, Inc. Independently variably controlled pulsed R.F. plasma chemical vapor processing
US4568563A (en) * 1983-08-02 1986-02-04 Standard Telephones And Cables Optical fibre manufacture
US4567505A (en) * 1983-10-27 1986-01-28 The Board Of Trustees Of The Leland Stanford Junior University Heat sink and method of attaching heat sink to a semiconductor integrated circuit and the like
US4566403A (en) * 1985-01-30 1986-01-28 Sovonics Solar Systems Apparatus for microwave glow discharge deposition
US4717683A (en) * 1986-09-23 1988-01-05 Motorola Inc. CMOS process
US4832253A (en) * 1987-04-03 1989-05-23 Bbc Brown Boveri Ag Method for manufacturing a laminar bond and apparatus for conducting the method
US4920396A (en) * 1987-04-13 1990-04-24 Nissan Motor Company, Limited CMOS having buried layer for carrier recombination
US5015353A (en) * 1987-09-30 1991-05-14 The United States Of America As Represented By The Secretary Of The Navy Method for producing substoichiometric silicon nitride of preselected proportions
US5200805A (en) * 1987-12-28 1993-04-06 Hughes Aircraft Company Silicon carbide:metal carbide alloy semiconductor and method of making the same
US4904610A (en) * 1988-01-27 1990-02-27 General Instrument Corporation Wafer level process for fabricating passivated semiconductor devices
US4982090A (en) * 1988-02-05 1991-01-01 Gesellschaft Fur Strahlen- Und Umweltforschung Mbh (Gsf) Method and apparatus for the quantitative, depth differential analysis of solid samples with the use of two ion beams
US4894709A (en) * 1988-03-09 1990-01-16 Massachusetts Institute Of Technology Forced-convection, liquid-cooled, microchannel heat sinks
US4996077A (en) * 1988-10-07 1991-02-26 Texas Instruments Incorporated Distributed ECR remote plasma processing and apparatus
US4891329A (en) * 1988-11-29 1990-01-02 University Of North Carolina Method of forming a nonsilicon semiconductor on insulator structure
US4929566A (en) * 1989-07-06 1990-05-29 Harris Corporation Method of making dielectrically isolated integrated circuits using oxygen implantation and expitaxial growth
US5013681A (en) * 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
US5280819A (en) * 1990-05-09 1994-01-25 Lanxide Technology Company, Lp Methods for making thin metal matrix composite bodies and articles produced thereby
US5198371A (en) * 1990-09-24 1993-03-30 Biota Corp. Method of making silicon material with enhanced surface mobility by hydrogen ion implantation
US5618739A (en) * 1990-11-15 1997-04-08 Seiko Instruments Inc. Method of making light valve device using semiconductive composite substrate
US5300788A (en) * 1991-01-18 1994-04-05 Kopin Corporation Light emitting diode bars and arrays and method of making same
US5289247A (en) * 1991-06-28 1994-02-22 Canon Kabushiki Kaisha Image forming apparatus with changeable feed interval for continuous feed
USRE39484E1 (en) * 1991-09-18 2007-02-06 Commissariat A L'energie Atomique Process for the production of thin semiconductor material films
US5405802A (en) * 1992-01-31 1995-04-11 Canon Kabushiki Kaisha Process of fabricating a semiconductor substrate
US5400458A (en) * 1993-03-31 1995-03-28 Minnesota Mining And Manufacturing Company Brush segment for industrial brushes
US5494835A (en) * 1993-12-23 1996-02-27 Commissariat A L'energie Atomique Process for the production of a relief structure on a semiconductor material support
US5611316A (en) * 1993-12-28 1997-03-18 Honda Giken Kogyo Kabushiki Kaisha Gas fuel supply mechanism for gas combustion engine
US5741733A (en) * 1994-01-14 1998-04-21 Siemens Aktiengesellschaft Method for the production of a three-dimensional circuit arrangement
US5880010A (en) * 1994-07-12 1999-03-09 Sun Microsystems, Inc. Ultrathin electronics
US5863830A (en) * 1994-09-22 1999-01-26 Commissariat A L'energie Atomique Process for the production of a structure having a thin semiconductor film on a substrate
US5622896A (en) * 1994-10-18 1997-04-22 U.S. Philips Corporation Method of manufacturing a thin silicon-oxide layer
US5714395A (en) * 1995-09-13 1998-02-03 Commissariat A L'energie Atomique Process for the manufacture of thin films of semiconductor material
US6190998B1 (en) * 1996-05-15 2001-02-20 Commissariat A L'energie Atomique Method for achieving a thin film of solid material and applications of this method
US7498234B2 (en) * 1996-05-15 2009-03-03 Commissariat A L'energie Atomique Method of producing a thin layer of semiconductor material
US6020252A (en) * 1996-05-15 2000-02-01 Commissariat A L'energie Atomique Method of producing a thin layer of semiconductor material
US5863832A (en) * 1996-06-28 1999-01-26 Intel Corporation Capping layer in interconnect system and method for bonding the capping layer onto the interconnect system
US5897331A (en) * 1996-11-08 1999-04-27 Midwest Research Institute High efficiency low cost thin film silicon solar cell design and method for making
US6054363A (en) * 1996-11-15 2000-04-25 Canon Kabushiki Kaisha Method of manufacturing semiconductor article
US6010591A (en) * 1996-11-22 2000-01-04 Max-Planck-Gesellschaft Zur Foerderung Der Wissenschaften E.V. Method for the releasable bonding and subsequent separation of reversibly bonded and polished wafers and also a wafer structure and wafer
US6198159B1 (en) * 1997-03-28 2001-03-06 Ube Industries, Ltd. Bonded wafer, process for producing same and substrate
US6013954A (en) * 1997-03-31 2000-01-11 Nec Corporation Semiconductor wafer having distortion-free alignment regions
US6013563A (en) * 1997-05-12 2000-01-11 Silicon Genesis Corporation Controlled cleaning process
US6033974A (en) * 1997-05-12 2000-03-07 Silicon Genesis Corporation Method for controlled cleaving process
US6048411A (en) * 1997-05-12 2000-04-11 Silicon Genesis Corporation Silicon-on-silicon hybrid wafer assembly
US5877070A (en) * 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
US6504235B2 (en) * 1997-07-25 2003-01-07 Hughes Electronics Corporation Passivation layer and process for semiconductor devices
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
US6200878B1 (en) * 1997-12-26 2001-03-13 Canon Kabushiki Kaisha SOI substrate processing method
US7883994B2 (en) * 1997-12-30 2011-02-08 Commissariat A L'energie Atomique Process for the transfer of a thin film
US6727549B1 (en) * 1998-06-30 2004-04-27 Intel Corporation Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer
US6054370A (en) * 1998-06-30 2000-04-25 Intel Corporation Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer
US6204079B1 (en) * 1998-07-30 2001-03-20 Commissariat A L'energie Atomique Selective transfer of elements from one support to another support
US6362077B1 (en) * 1998-10-16 2002-03-26 Commissariat A L'atomique Structure comprising a thin layer of material made up of conductive zones and insulating zones and a method of manufacturing such a structure
US6197695B1 (en) * 1998-10-20 2001-03-06 Commissariat A L'energie Atomique Process for the manufacture of passive and active components on the same insulating substrate
US6346458B1 (en) * 1998-12-31 2002-02-12 Robert W. Bower Transposed split of ion cut materials
US6529646B1 (en) * 1999-02-23 2003-03-04 Marconi Caswell Limited Optical modulator
US6362082B1 (en) * 1999-06-28 2002-03-26 Intel Corporation Methodology for control of short channel effects in MOS transistors
US6513564B2 (en) * 1999-08-10 2003-02-04 Silicon Genesis Corporation Nozzle for cleaving substrates
US20020000646A1 (en) * 2000-02-02 2002-01-03 Raytheon Company, A Delware Corporation Vacuum package fabrication of integrated circuit components
US6548375B1 (en) * 2000-03-16 2003-04-15 Hughes Electronics Corporation Method of preparing silicon-on-insulator substrates particularly suited for microwave applications
US20030077885A1 (en) * 2000-05-30 2003-04-24 Bernard Aspar Embrittled substrate and method for making same
US20020001221A1 (en) * 2000-06-29 2002-01-03 Shingo Hashimoto Load-less four-transistor memory cell
US7029548B2 (en) * 2000-07-12 2006-04-18 Commissariat A L'energie Atomique Method for cutting a block of material and forming a thin film
US20020048948A1 (en) * 2000-08-09 2002-04-25 Kostat Semiconductor Co., Ltd. Tape having implantable conductive lands for semiconductor packaging process and method for manufacturing the same
US7476596B2 (en) * 2000-08-22 2009-01-13 President And Fellows Of Harvard College Doped elongated semiconductors, growing such semiconductors, devices including such semiconductors, and fabricating such devices
US20020025604A1 (en) * 2000-08-30 2002-02-28 Sandip Tiwari Low temperature semiconductor layering and three-dimensional electronic circuits using the layering
US7902038B2 (en) * 2001-04-13 2011-03-08 Commissariat A L'energie Atomique Detachable substrate with controlled mechanical strength and method of producing same
US20050029224A1 (en) * 2001-04-13 2005-02-10 Bernard Aspar Detachable substrate or detachable structure and method for the production thereof
US6846690B2 (en) * 2001-12-03 2005-01-25 Stmicroelectronics S.A. Integrated circuit comprising an auxiliary component, for example a passive component or a microelectromechanical system, placed above an electronic chip, and the corresponding fabrication process
US6991956B2 (en) * 2002-07-09 2006-01-31 S.O.I.Tec Silicon On Insulator Technologies S.A. Methods for transferring a thin layer from a wafer having a buffer layer
US20040009649A1 (en) * 2002-07-12 2004-01-15 Kub Francis J. Wafer bonding of thinned electronic materials and circuits to high performance substrates
US20040029358A1 (en) * 2002-08-10 2004-02-12 Park Jea-Gun Method of fabricating nano SOI wafer and nano SOI wafer fabricated by the same
US20080017306A1 (en) * 2002-10-09 2008-01-24 The Board Of Trustees Of The University Of Illinoi Microfluidic systems and components
US20070037363A1 (en) * 2002-11-07 2007-02-15 Bernard Aspar Method for forming a brittle zone in a substrate by co-implantation
US7494897B2 (en) * 2002-12-24 2009-02-24 Commissariat A L'energie Atomique Method of producing mixed substrates and structure thus obtained
US20070087528A1 (en) * 2002-12-28 2007-04-19 Kim Sarah E Method and structure for vertically-stacked device contact
US7348260B2 (en) * 2003-02-28 2008-03-25 S.O.I.Tec Silicon On Insulator Technologies Method for forming a relaxed or pseudo-relaxed useful layer on a substrate
US7018909B2 (en) * 2003-02-28 2006-03-28 S.O.I.Tec Silicon On Insulator Technologies S.A. Forming structures that include a relaxed or pseudo-relaxed layer on a substrate
US20070020895A1 (en) * 2003-06-06 2007-01-25 Commissariat A L'energie Atomique Method for production of a very thin layer with thinning by means of induced self-support
US20050042842A1 (en) * 2003-08-21 2005-02-24 Ryan Lei Germanium on insulator fabrication via epitaxial germanium bonding
US20050067377A1 (en) * 2003-09-25 2005-03-31 Ryan Lei Germanium-on-insulator fabrication utilizing wafer bonding
US7029980B2 (en) * 2003-09-25 2006-04-18 Freescale Semiconductor Inc. Method of manufacturing SOI template layer
US7521292B2 (en) * 2004-06-04 2009-04-21 The Board Of Trustees Of The University Of Illinois Stretchable form of single crystal silicon for high performance electronics on rubber substrates
US20080020547A1 (en) * 2004-10-21 2008-01-24 Marek Kostrzewa Method Of Transferring At Least One Object Of Micrometric Or Millimetric Size By Means Of A Polymer Handle
US20070017438A1 (en) * 2005-07-19 2007-01-25 The Regents Of The University Of California Method of forming dislocation-free strained thin films
US20070087525A1 (en) * 2005-09-01 2007-04-19 International Business Machines Corporation Method and apparatus for making coplanar isolated regions of different semiconductor materials on a substrate
US20070087526A1 (en) * 2005-10-18 2007-04-19 Nabil Chhaimi Method of recycling an epitaxied donor wafer
US7670930B2 (en) * 2006-03-29 2010-03-02 Commissariat A L 'energie Atomique Method of detaching a thin film by melting precipitates
US20100025228A1 (en) * 2006-12-19 2010-02-04 Tauzin Aurelie Method for Preparing Thin GaN Layers by Implantation and Recycling of a Starting Substrate

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US8101503B2 (en) 1996-05-15 2012-01-24 Commissariat A L'energie Atomique Method of producing a thin layer of semiconductor material
US8609514B2 (en) 1997-12-10 2013-12-17 Commissariat A L'energie Atomique Process for the transfer of a thin film comprising an inclusion creation step
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US8389379B2 (en) 2002-12-09 2013-03-05 Commissariat A L'energie Atomique Method for making a stressed structure designed to be dissociated
US8048766B2 (en) 2003-06-24 2011-11-01 Commissariat A L'energie Atomique Integrated circuit on high performance chip
US8309431B2 (en) 2003-10-28 2012-11-13 Commissariat A L'energie Atomique Method for self-supported transfer of a fine layer by pulsation after implantation or co-implantation
US8664084B2 (en) 2005-09-28 2014-03-04 Commissariat A L'energie Atomique Method for making a thin-film element
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US9385251B2 (en) 2012-08-27 2016-07-05 Samsung Electronics Co., Ltd. Flexible semiconductor devices and methods of manufacturing the same

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