US20100308395A1 - Nonvolatile Memory Device and Method of Manufacturing the Same - Google Patents

Nonvolatile Memory Device and Method of Manufacturing the Same Download PDF

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Publication number
US20100308395A1
US20100308395A1 US12/793,336 US79333610A US2010308395A1 US 20100308395 A1 US20100308395 A1 US 20100308395A1 US 79333610 A US79333610 A US 79333610A US 2010308395 A1 US2010308395 A1 US 2010308395A1
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conductive layer
layer
selection lines
height
forming
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US12/793,336
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Jong Soon Leem
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SK Hynix Inc
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Hynix Semiconductor Inc
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Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LEEM, JONG SOON
Publication of US20100308395A1 publication Critical patent/US20100308395A1/en
Priority to US14/530,988 priority Critical patent/US9331087B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/28141—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects insulating part of the electrode is defined by a sidewall spacer, e.g. dummy spacer, or a similar technique, e.g. oxidation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region

Definitions

  • a breakdown voltage margin between the selection line and the drain contact plug or between the selection line and the source contact plug is reduced, the rate of device failure is increased, and a breakdown voltage margin between the drain contact plugs is also reduced, also resulting in device failure.
  • a deposition process and an etch process are repeatedly performed on the insulating layer to fill the space. In this case, however, manufacturing turnaround time and costs are increased because of the additional process steps.
  • the aspect ratio between selection lines is reduced by lowering the height of the selection lines. Accordingly, voids can be prevented from occurring when an interlayer dielectric is formed.
  • a method of manufacturing a nonvolatile memory device comprises forming a gate insulating layer and a first conductive layer over a semiconductor substrate that defines a first area in which selection lines will be formed and a second area in which word lines will be formed, performing an etch process to lower the height of the first conductive layer in the first area, forming a dielectric layer and a second conductive layer over the first conductive layer with a height that is different from the height of the first conductive layer, and performing a gate patterning process to form the selection lines and the word lines.
  • the method preferably further comprises, after performing the gate patterning process, forming a spacer on sidewalls of the word lines and the selection lines, forming an etch-stop layer on a surface of a structure including the spacer, the word lines, and the selection lines, and forming an interlayer dielectric over the etch-stop layer.
  • the etch process preferably is a dry etch process.
  • the etch process is preferably is performed to form a recess mask pattern, having the first area open and the second area closed, over the first conductive layer.
  • the method preferably further comprises forming a buffer layer over the first conductive layer before forming the recess mask pattern.
  • An aspect ratio between the selection lines preferably is reduced as much as a reduction in the height of the first conductive layer in the first area.
  • a nonvolatile memory device comprises selection lines and word lines formed by sequentially stacking a gate insulating layer, a first conductive layer, a dielectric layer, and a second conductive layer over a semiconductor substrate.
  • the height of the first conductive layer of the selection lines is lower than the height of the first conductive layer of the word lines.
  • the first conductive layer and the second conductive layer of the selection lines preferably are interconnected through contact holes.
  • FIGS. 1A to 1F are cross-sectional views showing a nonvolatile memory device and a method of manufacturing the same according to an exemplary embodiment of this disclosure.
  • FIG. 2 is a plan view showing a known nonvolatile memory device and the nonvolatile memory device of this disclosure.
  • FIGS. 1A to 1F are cross-sectional views showing a nonvolatile memory device and a method of manufacturing the same according to an exemplary embodiment of this disclosure.
  • a gate insulating layer 102 for electron tunneling and a first conductive layer 104 for floating gates are formed over a semiconductor substrate 100 .
  • the gate insulating layer 102 preferably comprises an oxide layer.
  • the first conductive layer 104 preferably comprises a doped polysilicon layer or may be formed by stacking an undoped polysilicon layer and a doped polysilicon layer.
  • a buffer layer 106 and a recess mask pattern 108 are formed over the first conductive layer 104 .
  • the buffer layer 106 is used to protect the surface of the conductive layer 104 when the recess mask pattern 108 is formed or removed and preferably comprises an oxide layer.
  • a recess process of lowering the height of part of the first conductive layer 104 is performed using the recess mask pattern 108 .
  • the recess process is described in detail below.
  • the buffer layer 106 exposed through the recess mask pattern 108 is patterned to form buffer patterns 106 a .
  • an etch process is performed on the exposed first conductive layer 104 , thereby lowering the height of the first conductive layer 104 .
  • the etch process can be a dry or wet etch process, but preferably is a dry etch process in order to minimize the loss of the first conductive layer 104 . Accordingly, the height H 2 of the first conductive layer 104 in the first area S in which selection lines will be formed is lower than the height H 1 of the first conductive layer 104 in the second area W in which word lines will be formed.
  • a dielectric layer 110 and a second conductive layer 112 for control gates are formed on the entire surface of the first conductive layer 104 .
  • the dielectric layer 110 preferably comprises an oxide layer or is formed by stacking a nitride layer and an oxide layer.
  • Contact holes C are formed in the first area in which selection lines will be formed so that the first conductive layer 104 and the second conductive layer 112 are electrically coupled together.
  • the second conductive layer 112 preferably comprises a doped polysilicon layer.
  • a hard mask layer 114 and a photoresist pattern 116 for gate patterning are formed over the second conductive layer 112 .

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

A method of manufacturing a nonvolatile memory device comprises forming a gate insulating layer and a first conductive layer over a semiconductor substrate that defines a first area in which selection lines will be formed and a second area in which word lines will be formed, performing an etch process to lower a height of the first conductive layer in the first area, forming a dielectric layer and a second conductive layer over the first conductive layer with a height that is different from the height of the first conductive layer, and performing a gate patterning process to form the selection lines and the word lines.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • Priority to Korean patent application number 10-2009-0050439 filed on Jun. 8, 2009, the entire disclosure of which is incorporated by reference herein, is claimed.
    • BACKGROUND
  • An exemplary embodiment relates generally to a nonvolatile memory device and a method of manufacturing the same and, more particularly, to a nonvolatile memory device and a method of manufacturing the same, in which the height of selection lines is lower than the height of word lines, thereby being capable of preventing voids from occurring between the selection lines when an interlayer dielectric is formed.
  • In a nonvolatile memory device having a string structure, to reduce the size of the string, the size of cells, the size of selection lines, and the size of a space between the selection lines is reduced. With the size of the space between the selection lines being reduced, the gap-fill margin of an insulating layer for filling the space is reduced. Accordingly, in a process of forming the insulating layer, voids may be generated in the space portion. If drain contact holes or source contact holes are formed with the voids present, it is difficult to obtain contact holes of a desired form. Furthermore, a breakdown voltage margin between the selection line and the drain contact plug or between the selection line and the source contact plug is reduced, the rate of device failure is increased, and a breakdown voltage margin between the drain contact plugs is also reduced, also resulting in device failure. To prevent the occurrence of the voids, a deposition process and an etch process are repeatedly performed on the insulating layer to fill the space. In this case, however, manufacturing turnaround time and costs are increased because of the additional process steps.
    • BRIEF SUMMARY
  • In accordance with an exemplary embodiment, the aspect ratio between selection lines is reduced by lowering the height of the selection lines. Accordingly, voids can be prevented from occurring when an interlayer dielectric is formed.
  • A method of manufacturing a nonvolatile memory device according to an aspect of the disclosure comprises forming a gate insulating layer and a first conductive layer over a semiconductor substrate that defines a first area in which selection lines will be formed and a second area in which word lines will be formed, performing an etch process to lower the height of the first conductive layer in the first area, forming a dielectric layer and a second conductive layer over the first conductive layer with a height that is different from the height of the first conductive layer, and performing a gate patterning process to form the selection lines and the word lines.
  • The method preferably further comprises, after performing the gate patterning process, forming a spacer on sidewalls of the word lines and the selection lines, forming an etch-stop layer on a surface of a structure including the spacer, the word lines, and the selection lines, and forming an interlayer dielectric over the etch-stop layer.
  • The etch process preferably is a dry etch process.
  • The etch process is preferably is performed to form a recess mask pattern, having the first area open and the second area closed, over the first conductive layer.
  • The method preferably further comprises forming a buffer layer over the first conductive layer before forming the recess mask pattern.
  • An aspect ratio between the selection lines preferably is reduced as much as a reduction in the height of the first conductive layer in the first area.
  • A nonvolatile memory device according to another aspect of the disclosure comprises selection lines and word lines formed by sequentially stacking a gate insulating layer, a first conductive layer, a dielectric layer, and a second conductive layer over a semiconductor substrate. Here, the height of the first conductive layer of the selection lines is lower than the height of the first conductive layer of the word lines.
  • The first conductive layer and the second conductive layer of the selection lines preferably are interconnected through contact holes.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1A to 1F are cross-sectional views showing a nonvolatile memory device and a method of manufacturing the same according to an exemplary embodiment of this disclosure; and
  • FIG. 2 is a plan view showing a known nonvolatile memory device and the nonvolatile memory device of this disclosure.
    •  DESCRIPTION OF EMBODIMENTS
  • Hereinafter, an exemplary embodiment of the disclosure will be described in detail with reference to the accompanying drawings. The drawing figures are provided to allow those having ordinary skill in the art to understand the scope of the embodiment of the disclosure.
  • FIGS. 1A to 1F are cross-sectional views showing a nonvolatile memory device and a method of manufacturing the same according to an exemplary embodiment of this disclosure.
  • Referring to FIG. 1A, a gate insulating layer 102 for electron tunneling and a first conductive layer 104 for floating gates are formed over a semiconductor substrate 100. The gate insulating layer 102 preferably comprises an oxide layer. The first conductive layer 104 preferably comprises a doped polysilicon layer or may be formed by stacking an undoped polysilicon layer and a doped polysilicon layer. A buffer layer 106 and a recess mask pattern 108 are formed over the first conductive layer 104. The buffer layer 106 is used to protect the surface of the conductive layer 104 when the recess mask pattern 108 is formed or removed and preferably comprises an oxide layer. The recess mask pattern 108 is formed to open a first area S in which selection lines will be formed and to close a second area W in which word lines will be formed. The recess mask pattern 108 preferably comprises an SiON layer or an Si3N4 layer. Here, the recess mask pattern 108 preferably is formed using an etchant in which CHF3 and O2 are mixed.
  • Referring to FIG. 1B, a recess process of lowering the height of part of the first conductive layer 104 is performed using the recess mask pattern 108. The recess process is described in detail below. The buffer layer 106 exposed through the recess mask pattern 108 is patterned to form buffer patterns 106 a. Next, an etch process is performed on the exposed first conductive layer 104, thereby lowering the height of the first conductive layer 104. The etch process can be a dry or wet etch process, but preferably is a dry etch process in order to minimize the loss of the first conductive layer 104. Accordingly, the height H2 of the first conductive layer 104 in the first area S in which selection lines will be formed is lower than the height H1 of the first conductive layer 104 in the second area W in which word lines will be formed.
  • Referring to FIG. 1C, after the recess mask pattern 108 and the buffer patterns 106 a are removed, a dielectric layer 110 and a second conductive layer 112 for control gates are formed on the entire surface of the first conductive layer 104. The dielectric layer 110 preferably comprises an oxide layer or is formed by stacking a nitride layer and an oxide layer. Contact holes C are formed in the first area in which selection lines will be formed so that the first conductive layer 104 and the second conductive layer 112 are electrically coupled together. The second conductive layer 112 preferably comprises a doped polysilicon layer. Next, a hard mask layer 114 and a photoresist pattern 116 for gate patterning are formed over the second conductive layer 112.
  • Referring to FIG. 1D, an etch process using the photoresist pattern 116 is performed to etch the hard mask layer 114, thereby forming hard mask patterns (not shown). An etch process using the hard mask patterns is performed to pattern the second conductive layer 112, the dielectric layer 110, and the first conductive layer 104, thereby forming the second conductive patterns 112 a, dielectric patterns 110 a, and first conductive patterns 104 a. Consequently, the word lines WL and the selection lines SL are formed. Next, an ion implantation process is performed to form impurity ion implantation areas 100 a in the semiconductor substrate 100 exposed between the word lines WL and the selection lines SL. Next, the photoresist pattern 116 and the hard mask patterns (not shown) are removed. Accordingly, the height of the selection lines WL becomes lower than that of the word lines WL.
  • Referring to FIG. 1E, a spacer 118 is formed on the sidewalls of the word lines WL and the selection lines SL. The spacer 118 preferably comprises an oxide layer. An etch-stop layer 120 is formed on the entire surface of the word lines WL, the selection lines SL, and the exposed gate insulating layer 102, including the spacer 118. The etch-stop layer 120 preferably comprises a nitride layer.
  • Referring to FIG. 1F, an interlayer dielectric 122 is formed over the etch-stop layer 120. The interlayer dielectric 122 preferably comprises an oxide layer, for example, a TEOS (tetra ethyl ortho silicate) layer.
  • As described above, the distance between the selection lines SL remains intact, but the height of the selection lines SL is lowered. Accordingly, the aspect ratio of a space between neighboring selection lines SL can be reduced, and so voids are not generated in the interlayer dielectric 122 in the space between the selection lines SL.
  • FIG. 2 is a plan view showing a known nonvolatile memory device and the nonvolatile memory device of this disclosure. This drawing shows that contact plugs DC are formed in active areas A between the selection lines SL after the interlayer dielectric 122 shown in FIG. 1F are formed.
  • As shown in FIG. 2, the known nonvolatile memory device has a high probability that voids V will occur because the height of the selection lines SL is not lowered unlike the nonvolatile memory device of this disclosure. When the voids V are generated, a bridge can occur between neighboring contact plugs DC or between the contact plug DC and the selection line SL.
  • In this disclosure, however, the occurrence of voids can be prevented because the aspect ratio between the contact plugs DC and between the contact plug DC and the selection line SL can be reduced by lowering the height of the selection line SL. Since the occurrence of voids is prevented as described above, a bridge can be prevented from occurring. Accordingly, a reduction in the reliability of the nonvolatile memory device can be prevented. Furthermore, since the occurrence of a void can be easily prevented, the number of processes of forming the interlayer dielectric needs not to be increased. Accordingly, the manufacturing turnaround time and costs can be reduced.
  • In accordance with this disclosure, the aspect ratio between the selection lines is reduced by lowering the height of the selection lines. Accordingly, when the interlayer dielectric is formed, the occurrence of voids can be prevented. Consequently, a breakdown voltage margin between the selection line and the drain contact plug, between the selection line and the source contact plug, and between the drain contact plugs can be guaranteed, so device failure can be prevented.
  • Furthermore, the manufacturing turnaround time and costs can be reduced because a deposition process and an etch process for the interlayer dielectric need not to be performed several times.

Claims (8)

1. A method of manufacturing a nonvolatile memory device, the method comprising:
forming a gate insulating layer and a first conductive layer over first and second areas defined in a semiconductor substrate, wherein selection lines having sidewalls will be formed in the first area and word lines having sidewalls will be formed in the second area;
performing an etch process to lower a height of the first conductive layer in the first area;
forming a dielectric layer and a second conductive layer over the first conductive layer with a height that is different from the height of the conductive layer; and
performing a gate patterning process to form the selection lines and the word lines in the first and second areas, respectively.
2. The method of claim 1, further comprising:
after performing the gate patterning process,
forming a spacer on the sidewalls of the word lines and the selection lines;
forming an etch-stop layer on a surface of a structure including the spacer, the word lines, and the selection lines; and
forming an interlayer dielectric over the etch-stop layer.
3. The method of claim 1, wherein the etch process is a dry etch process.
4. The method of claim 1, comprising performing the etch process to form a recess mask pattern, having the first area open and the second area closed, over the first conductive layer.
5. The method of claim 4, further comprising forming a buffer layer over the first conductive layer before forming the recess mask pattern.
6. The method of claim 1, wherein an aspect ratio between the selection lines is reduced as much as a reduction in the height of the first conductive layer in the first area.
7. A nonvolatile memory device, comprising:
selection lines and word lines formed by sequentially stacking a gate insulating layer, a first conductive layer, a dielectric layer, and a second conductive layer over a semiconductor substrate,
wherein a height of the first conductive layer of the selection lines is lower than a height of the first conductive layer of the word lines.
8. The nonvolatile memory device of claim 7, wherein the first conductive layer and the second conductive layer of the selection lines are interconnected through contact holes.
US12/793,336 2009-06-08 2010-06-03 Nonvolatile Memory Device and Method of Manufacturing the Same Abandoned US20100308395A1 (en)

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US10699960B2 (en) * 2018-06-27 2020-06-30 Taiwan Semiconductor Manufacturing Co., Ltd. Methods for improving interlayer dielectric layer topography

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US20070126028A1 (en) * 2005-12-06 2007-06-07 Masaaki Higashitani Low resistance void-free contacts
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KR101166613B1 (en) 2012-07-18
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