US20100288536A1 - Ceramic circuit board and method of making the same - Google Patents

Ceramic circuit board and method of making the same Download PDF

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Publication number
US20100288536A1
US20100288536A1 US12/800,291 US80029110A US2010288536A1 US 20100288536 A1 US20100288536 A1 US 20100288536A1 US 80029110 A US80029110 A US 80029110A US 2010288536 A1 US2010288536 A1 US 2010288536A1
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United States
Prior art keywords
heat
layer
ceramic
dissipating
ceramic substrate
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Abandoned
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US12/800,291
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English (en)
Inventor
Wen-Chung Chiang
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Tong Hsing Electronic Industries Ltd
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High Conduction Scientific Co Ltd
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Assigned to HIGH CONDUCTION SCIENTIFIC CO., LTD. reassignment HIGH CONDUCTION SCIENTIFIC CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHIANG, WEN-CHUNG
Publication of US20100288536A1 publication Critical patent/US20100288536A1/en
Assigned to TONG HSING ELECTRONIC INDUSTRIES, LTD. reassignment TONG HSING ELECTRONIC INDUSTRIES, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HIGH CONDUCTION SCIENTIFIC CO., LTD.
Priority to US13/862,298 priority Critical patent/US9125335B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/858—Means for heat extraction or cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49107—Connecting at different heights on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10416—Metallic blocks or heatsinks completely inserted in a PCB
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/8506—Containers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
    • Y10T156/1056—Perforating lamina
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
    • Y10T156/1056—Perforating lamina
    • Y10T156/1057—Subsequent to assembly of laminae
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49128—Assembling formed circuit to base

Definitions

  • This invention relates to a ceramic circuit board, more particularly to a ceramic circuit board including a heat-dissipating unit and to a method of making the same.
  • a conventional ceramic circuit board is a ceramic-copper plate that is formed by eutectic-bonding a ceramic substrate made of, e.g., Al 2 O 3 , AlN, TiO 2 , ZrO 2 , ZnO, 2MgO.SiO 2 , or BaTiO 3 , and copper foils using direct copper bonding (DCB).
  • the ceramic substrate has electrical insulating ability, thereby being able to insulate a plurality of electronic components disposed on the conventional ceramic circuit board.
  • a conventional ceramic circuit board 1 is shown, and a method of making the same includes (A) providing a ceramic substrate 10 , and first and second copper foils 11 , 12 , (B) eutectic-bonding the first and second copper foils 11 , 12 respectively to top and bottom surfaces of the ceramic substrate 10 , and (C) patterning the first copper foil 11 to form two spaced apart conducting portions 111 .
  • the ceramic circuit board 1 is used for packaging an electronic component such as a horizontally structured light emitting diode (LED) 91 .
  • the ceramic substrate 10 is formed by virtue of a conventional ceramic-making process (e.g., tape casting, slip casting, or pressing).
  • the ceramic substrate 10 made by the conventional ceramic-making process has a thickness larger than 0.2 mm such that the ceramic substrate 10 is too thick for the horizontally structured LED 91 in terms of heat-dissipation.
  • the ceramic substrate 10 is unable to efficiently transfer heat generated by the horizontally structured LED 91 , thereby reducing the service life of the electronic component and adversely affecting the efficiency of the electronic component.
  • the object of the present invention is to provide a ceramic circuit board that can overcome the aforesaid drawbacks of the prior art, and a method of making the same.
  • a ceramic circuit board for use in packaging an electronic element includes a ceramic-copper plate, and a heat-dissipating unit that is adapted for dissipating heat from the electronic element.
  • the ceramic-copper plate includes a ceramic substrate that has opposite first and second surfaces, and a through-hole formed through the first and second surfaces, a top copper pattern that overlies the first surface of the ceramic substrate and that has at least two conducting portions spaced apart from each other, and a bottom copper layer that underlies the second surface of the ceramic substrate.
  • the heat-dissipating unit includes a heat-dissipating layer that is disposed in the through-hole of the ceramic substrate above the bottom copper layer and that has a thermal conductivity larger than that of the ceramic substrate.
  • a method of making a ceramic circuit board for use in packaging an electronic element comprises: (a) providing a ceramic-copper plate that includes top and bottom copper layers, a ceramic substrate between the top and bottom copper layers, and a through-hole formed in the ceramic substrate; and (b) providing a heat-dissipating unit on the bottom copper layer and within the through-hole for dissipating heat from the electronic element.
  • FIG. 1 shows consecutive steps of making a conventional ceramic circuit board
  • FIG. 2 is a schematic fragmentary sectional view to illustrate a conventional ceramic circuit board adapted for packaging a horizontally structured light emitting diode;
  • FIG. 3 is a schematic fragmentary sectional view to illustrate the first preferred embodiment of a ceramic circuit board according to the present invention, which is used for packaging a horizontally structured light emitting diode;
  • FIG. 4 shows consecutive steps of the first preferred embodiment of a method for making the ceramic circuit board shown in FIG. 3 ;
  • FIG. 5 shows consecutive steps of the second preferred embodiment of a method for making the ceramic circuit board shown in FIG. 3 ;
  • FIG. 6 is a schematic fragmentary sectional view to illustrate the second preferred embodiment of a ceramic circuit board according to this invention, which is used for packaging a vertically structured light emitting diode;
  • FIG. 7 shows consecutive steps of the third preferred embodiment of a method for making the ceramic circuit board shown in FIG. 6 .
  • the first preferred embodiment of a ceramic circuit board according to the present invention is adapted to be electrically connected to at least one electronic element, such as a horizontally structured light emitting diode (LED) 91 , and includes a ceramic-copper plate and a heat-dissipating unit 5 .
  • LED horizontally structured light emitting diode
  • the ceramic-copper plate includes a ceramic substrate 2 that has opposite first and second surfaces 21 , 22 , and a through-hole 20 formed through the first and second surfaces 21 , 22 , a top copper pattern 3 that overlies the first surface 21 of the ceramic substrate 2 and that has two conducting portions 32 spaced apart from each other, and a bottom copper layer 4 that underlies the second surface 22 of the ceramic substrate 2 .
  • the top copper pattern 3 further has a gap 31 that separates the two conducting portions 32 and that completely exposes the through-hole 20 of the ceramic substrate 2 . It should be noted that the top copper pattern 3 might have more than two conducting portions 32 spaced apart from each other so as to be electrically connected to a plurality of electronic elements.
  • the heat-dissipating unit 5 is adapted for dissipating heat from the electronic element (e.g., the horizontally structured LED 91 ), and includes a heat-dissipating layer 51 that is disposed in the through-hole 20 of the ceramic substrate 2 above the bottom copper layer 4 .
  • the heat-dissipating unit 5 further includes a ceramic layer 52 that lies between the heat-dissipating layer 51 and the bottom copper layer 4 of the ceramic-copper plate.
  • the ceramic layer 52 may be made from Al 2 O 3 , AlN, or TiO 2 .
  • the ceramic layer 52 is not required.
  • the ceramic layer 52 is required.
  • the heat-dissipating layer 51 has a thermal conductivity larger than that of the ceramic substrate 2 of the ceramic-copper plate, and the ceramic layer 52 of the heat-dissipating unit 5 has a thickness (d) smaller than a thickness (D) of the ceramic substrate 2 of the ceramic-copperplate.
  • the thickness (D) of the ceramic substrate 2 of the ceramic-copper plate is larger than 0.2 mm.
  • the thickness (d) of the ceramic layer 52 ranges from 0.02 mm to 0.2 mm.
  • the thermal conductivity of the heat-dissipating layer 51 is larger than 170 Wm ⁇ 1 K ⁇ 1 .
  • the heat-dissipating layer 51 may be made of copper having a thermal conductivity of about 401 Wm ⁇ 1 K ⁇ 1 , a Cu/W alloy having a thermal conductivity of about 209 Wm ⁇ 1 K ⁇ 1 , or a Cu/Mo alloy having a thermal conductivity of about 184 Wm ⁇ 1 K ⁇ 1 .
  • the ceramic layer 52 of the heat-dissipating unit 5 may be formed by a thermal spraying technique or a plasma spraying technique.
  • the heat-dissipating layer 51 in this embodiment is made of copper.
  • the ceramic layer 52 of the heat-dissipating unit 5 and the bottom copper layer 4 of the ceramic-copper plate are sinter-bonded (e.g., eutectic bonding) to each other by virtue of a heat treatment at a temperature, which is lower than the melting point of copper (about 1083° C.) and higher than the eutectic temperature of the copper-copper oxide eutectic (about 1065° C.).
  • a method of making the ceramic circuit board includes: (a) providing the ceramic-copper plate that includes a top copper layer 3 ′ and the bottom copper layer 4 , the ceramic substrate 2 between the top and bottom copper layers 3 ′ 4 , and the through-hole 20 formed in the ceramic substrate 2 ; and (b) providing the heat-dissipating unit 5 on the bottom copper layer 4 and within the through-hole 20 for dissipating heat from the electronic element.
  • the first preferred embodiment of the method according to the present invention is conducted to make the ceramic circuit board as shown in FIG. 3 , and step (a) thereof includes: (a1) forming the through-hole 20 that extends through the first and second surfaces 21 , 22 of the ceramic substrate 2 ; (a2) sinter-bonding the top and bottom copper layers 3 ′, 4 respectively to the first and second surfaces 21 , 22 of the ceramic substrate 2 after step (a1); and (a3) patterning the top copper layer 3 ′ to form the two conducting portions 32 , and the gap 31 that separates the two conducting portions 32 and that completely expose the through-hole 20 after step (a2).
  • the heat-dissipating unit 5 is provided on the bottom copper layer 4 in the through-hole 20 of the ceramic substrate 2 via a sinter-bonding process.
  • step (a1) may be performed using CO 2 laser having power larger than 100 W so as to cut the ceramic substrate 2 , thereby forming the through-hole 20 .
  • Step (a1) of the first preferred embodiment of the method is suitable to form the through-hole 20 that has a small size.
  • a cross-section of the through-hole 20 may be square, circular, or polygonal. If the size of the through-hole 20 is unduly large, the ceramic substrate 2 may be damaged since both of the top and bottom copper layers 3 ′, 4 may go through expansion and contraction during step (a2) such that both of the top and bottom copper layers 3 ′, 4 may exert thermal stress on the ceramic substrate 2 , and the top copper layer 3 ′ may be deformed such that the quality of the top copper pattern 3 may be influenced. Consequently, preferably, the first preferred embodiment of the method is conducted to form the through-hole 20 having the size that is approximately smaller than 5 mm.
  • step (a) thereof includes: (a1) sinter-bonding the top copper layer 3 ′ to the first surface 21 of the ceramic substrate 2 ; (a2) patterning the top copper layer 3 ′ to form the two conducting portions 32 and the gap 31 that separates the two conducting portions 32 after step (a1); (a3) forming the through-hole 20 in the ceramic substrate 2 after step (a2); and (a4) sinter-bonding the bottom copper layer 4 to the second surface 22 of the ceramic substrate 2 opposite to the first surface 21 through the heat treatment after step (a3).
  • step (b) of the second preferred embodiment of the method the heat-dissipating unit 5 is provided on thebottomcopper layer 4 in the through-hole 20 of the ceramic substrate 2 via a sinter-bonding process.
  • steps (a4) and (b) are conducted together after step (a3).
  • step (a2) formation of the top copper pattern 3
  • step (a3) formation of the through-hole 20
  • thermal stress exerted by the top copper pattern 3 and the bottom copper layer 4 is smaller than the aforementioned thermal stress exerted by the larger top copper layer 3 ′ and the bottom copper layer 4 . Therefore, step (a3) of the second preferred embodiment of the method is suitable to form the through-hole 20 having a larger size compared to step (a2) of the first preferred embodiment of the method.
  • the second preferred embodiment of the method is conducted to form the through-hole 20 having the size larger than 5 mm.
  • the larger through-hole 20 formed by virtue of the second preferred embodiment of the method is able to accommodate the larger heat-dissipating unit 5 .
  • the heat generated by the electronic element e.g., the horizontally structured LED 91 as shown in FIG. 3
  • the heat generated by the electronic element can be more efficiently dissipated.
  • the second preferred embodiment of the ceramic circuit board according to the present invention is similar to the first preferred embodiment except that the gap 31 of the top copper pattern 3 partially exposes the through-hole 20 of the ceramic substrate 2 and that one of the conducting portions 32 of the top copper pattern 3 contacts the heat-dissipating layer 51 of the heat-dissipating unit 5 . Namely, the heat-dissipating layer 51 is hidden between the top copper pattern 3 and the bottom copper layer 4 .
  • the second preferred embodiment of the ceramic circuit board of this invention is adapted for both of the horizontally structured LED 91 (see FIG. 3 ) and a vertically structured LED 92 .
  • step (a) thereof includes: (a1) forming the through-hole 20 extending through the opposite first and second surfaces 21 , 22 of the ceramic substrate 2 ; (a2) sinter-bonding the top and bottom copper layers 3 ′, 4 respectively to the first and second surfaces 21 , 22 of the ceramic substrate 2 via the heat treatment after step (a1); and (a3) patterning the top copper layer 3 ′ to form the two conducting portions 32 .
  • Step (b) of the third preferred embodiment of the method includes sinter-bonding the heat-dissipating unit 5 to the bottom copper layer 4 in the through-hole 20 of the ceramic substrate 2 simultaneously with step (a2) via the heat treatment.
  • steps (a2) and (b) are conducted together, the heat-dissipating unit 5 is sinter-bonded to both of the top and bottom copper layers 3 ′, 4 .
  • the ceramic circuit board of this invention is able to efficiently dissipate the heat from the electronic element, thereby increasing the service life and the efficiency of the electronic element.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structure Of Printed Boards (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Led Device Packages (AREA)
US12/800,291 2009-05-15 2010-05-11 Ceramic circuit board and method of making the same Abandoned US20100288536A1 (en)

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TW098116190 2009-05-15

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100258838A1 (en) * 2009-04-13 2010-10-14 High Conduction Scientific Co., Ltd. Packaging substrate device, method for making the packaging substrate device, and packaged light emitting device
US20130213473A1 (en) * 2012-02-21 2013-08-22 Atomic Energy Council - Institute Of Nuclear Energy Research Composite substrate with high thermal conductivity
EP2621256A4 (en) * 2010-11-30 2017-04-26 Rayben Technologies (Zhu Hai) Ltd Printed circuit board with insulated micro radiator
US20170303404A1 (en) * 2016-04-13 2017-10-19 Shunsin Technology (Zhong Shan) Limited Manufacturing method for circuit board based on copper ceramic substrate
US20180098414A1 (en) * 2016-09-30 2018-04-05 Astec International Limited Heat sink assemblies for surface mounted devices
WO2018091230A1 (de) * 2016-11-16 2018-05-24 Epcos Ag Leistungsmodul mit verringerter defektanfälligkeit und verwendung desselben
US10043960B2 (en) * 2011-11-15 2018-08-07 Cree, Inc. Light emitting diode (LED) packages and related methods
US20210050278A1 (en) * 2018-01-24 2021-02-18 Mitsubishi Materials Corporation Method of manufacturing power module substrate board and ceramic-copper bonded body
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US12170239B2 (en) * 2020-01-16 2024-12-17 Semiconductor Components Industries, Llc Direct bonded copper substrates fabricated using silver sintering
CN113225901A (zh) * 2021-05-12 2021-08-06 四川锐宏电子科技有限公司 一种多层厚膜陶瓷基电路板及其制备工艺

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