US20100044712A1 - Thin-film transistor substrate and method of manufacturing the same - Google Patents
Thin-film transistor substrate and method of manufacturing the same Download PDFInfo
- Publication number
- US20100044712A1 US20100044712A1 US12/605,647 US60564709A US2010044712A1 US 20100044712 A1 US20100044712 A1 US 20100044712A1 US 60564709 A US60564709 A US 60564709A US 2010044712 A1 US2010044712 A1 US 2010044712A1
- Authority
- US
- United States
- Prior art keywords
- layer
- gate
- electrode
- disposed
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 57
- 239000010409 thin film Substances 0.000 title claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 title description 14
- 239000003990 capacitor Substances 0.000 claims abstract description 74
- 238000003860 storage Methods 0.000 claims abstract description 65
- 238000009413 insulation Methods 0.000 claims abstract description 55
- 229910052751 metal Inorganic materials 0.000 claims abstract description 49
- 239000002184 metal Substances 0.000 claims abstract description 49
- 239000010410 layer Substances 0.000 claims description 222
- 239000012044 organic layer Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 27
- 238000000034 method Methods 0.000 description 26
- 239000004065 semiconductor Substances 0.000 description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 7
- 229910052750 molybdenum Inorganic materials 0.000 description 7
- 239000011733 molybdenum Substances 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 239000011651 chromium Substances 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052779 Neodymium Inorganic materials 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910052804 chromium Inorganic materials 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 230000002708 enhancing effect Effects 0.000 description 3
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000012780 transparent material Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 1
- -1 for example Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Definitions
- the present invention relates to a thin-film transistor (TFT) substrate. More particularly, the present invention relates to a TFT substrate and a method of manufacturing the TFT substrate.
- TFT thin-film transistor
- a liquid crystal display (LCD) apparatus includes a thin-film transistor (TFT) substrate, a color filter substrate facing the TFT substrate, and a liquid crystal layer disposed between the TFT substrate and the color filter substrate.
- TFT thin-film transistor
- the TFT substrate has a plurality of pixels, each of which includes a TFT section and storage capacitor section, so that each pixel may be independently driven.
- enhancing the aperture ratio becomes very important because the display apparatus should have high resolution within a relatively small area.
- the most important factors for the aperture ratio include the area of the storage capacitor section and the adoption of fine lines.
- the thickness of a gate insulation layer may be reduced or the gate insulation layer may have a double-layered structure of silicon oxide (SiO 2 ) and silicon nitride (SiN x ).
- the gate insulation layer may become unreliable and vulnerable to electrostatic charges.
- SiO 2 may remain under a channel of a TFT and therefore, may deteriorate the TFT even though the capacitance of the storage capacitor section increases.
- the present invention provides a thin-film transistor (TFT) substrate that may be capable of enhancing an aperture ratio without deteriorating the TFT.
- TFT thin-film transistor
- the present invention also provides a method of manufacturing the TFT substrate.
- the present invention discloses a TFT substrate including a gate wiring, a capacitor dielectric layer, a gate insulation layer, an active pattern, a data wiring, a protection layer, and a pixel electrode.
- the gate wiring is disposed on the substrate.
- the gate wiring includes a gate electrode, a lower storage electrode, and a gate metal pad.
- the capacitor dielectric layer is disposed on the lower storage electrode.
- the gate insulation layer is disposed on the substrate.
- the active pattern includes an active layer and a dummy active layer disposed on the gate insulation layer in a gate electrode region and a gate metal pad region, respectively.
- the data wiring includes a source electrode, a drain electrode, an upper storage electrode, and a data metal pad.
- the source and drain electrodes are disposed on the active layer such that the source and drain electrodes are spaced apart from each other.
- a portion of the upper storage electrode is disposed on the capacitor dielectric layer exposed through a first contact hole in the gate insulation layer.
- the data metal pad is directly connected to the gate metal pad through a second contact hole in the gate insulation layer and the dummy active layer.
- the protection layer is disposed on the substrate.
- the pixel electrode is disposed on the protection layer and connected to the drain electrode.
- the present invention also discloses a method of manufacturing a TFT substrate including forming a gate wiring and a capacitor dielectric layer through a patterning process using one mask.
- the gate wiring including a gate electrode and a lower storage electrode is formed on a substrate.
- the capacitor dielectric layer is formed on the lower storage electrode.
- a gate insulation layer and an active layer are formed on the substrate.
- the gate insulation layer has a first contact hole in a capacitor dielectric layer region.
- the active layer is formed on the gate insulation layer to cover the gate electrode.
- a data wiring including a source electrode, a drain electrode, and an upper storage electrode is formed.
- the source and drain electrodes are disposed on the active layer such that the source and drain electrodes are spaced apart from each other.
- a portion of the upper storage electrode is disposed on the capacitor dielectric layer exposed through the first contact hole.
- a protection layer is formed on the substrate and then, a pixel electrode is formed on the protection layer. The pixel electrode is connected to the drain electrode.
- FIG. 1 is a layout showing a portion of a thin-film transistor (TFT) substrate according to an exemplary embodiment of the present invention.
- TFT thin-film transistor
- FIG. 2 is a cross-sectional view showing the TFT section, the storage capacitor section, and the pad section of FIG. 1 .
- FIG. 3 , FIG. 4 , FIG. 5 , FIG. 6 , FIG. 7 , FIG. 8 , FIG. 9 , FIG. 10 , FIG. 11 , FIG. 12 , FIG. 13 , FIG. 14 , and FIG. 15 are cross-sectional views showing a method of manufacturing the TFT substrate in FIG. 2 .
- first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
- Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.
- FIG. 1 is a layout showing a portion of a thin-film transistor (TFT) substrate according to an exemplary embodiment of the present invention
- FIG. 2 is a cross-sectional view showing the TFT section, the storage capacitor section, and the pad section of FIG. 1 .
- TFT thin-film transistor
- a TFT substrate 100 includes a gate wiring 200 , a capacitor dielectric layer 300 , a gate insulation layer 400 , an active layer 500 , and a data wiring 600 .
- the gate wiring 200 is formed on a substrate 110 .
- the gate wiring 200 includes a gate line 210 , a gate electrode 220 , and a lower storage electrode 230 .
- the substrate 110 may include a transparent and dielectric material, for example, glass or plastic.
- the gate wiring 200 may include, for example, aluminum (Al), molybdenum (Mo), neodymium (Nd), chromium (Cr), tantalum (Ta), titanium (Ti), tungsten (W), copper (Cu), silver (Ag), or an alloy thereof. These may be used alone or in combination.
- the gate wiring 200 may include more than one layer having different physical and chemical characteristics.
- the gate wiring 200 may have a two-layer structure of aluminum (Al) and molybdenum (Mo) to reduce electric resistance.
- the gate lines 210 may extend, for example, along a horizontal direction, when viewed on a plane, to define lower and upper portions of pixel P.
- the gate electrode 220 is connected to the gate line 210 .
- the gate electrode 220 defines a gate terminal of a TFT section TFT formed in the pixel P.
- the lower storage electrode 230 is isolated from the gate line 210 and the gate electrode 220 . In other words, the lower storage electrode 230 is insulated from the gate line 210 and the gate electrode 220 .
- the lower storage electrode 230 defines a lower electrode of a storage capacitor section Cst.
- the lower storage electrode 230 overlaps an upper storage electrode 640 .
- the lower storage electrode 230 may partially overlap a data line 610 to increase the capacitance of the storage capacitor section Cst.
- the lower storage electrode 230 receives a reference voltage.
- the capacitor dielectric layer 300 is formed on the lower storage electrode 230 .
- the capacitor dielectric layer 300 separates the lower storage electrode 230 from the upper storage electrode 640 so that the lower and upper storage electrodes 230 and 640 may define the storage capacitor section Cst.
- the capacitor dielectric layer 300 includes silicon oxide (SiO 2 ) having a higher dielectric constant than silicon nitride (SiN x ). Additionally, the capacitor dielectric layer 300 may have a thickness of no more than about 1,000 ⁇ to increase the capacitance of the storage capacitor section Cst. For example, the capacitor dielectric layer 300 may have a thickness of about 500 ⁇ to about 1,000 ⁇ .
- the gate insulation layer 400 is formed on the substrate 110 having the gate wiring 200 and the capacitor dielectric layer 300 formed thereon.
- the gate insulation layer 400 protects and insulates the gate wiring 200 from other conductors.
- the gate insulation layer 400 may include, for example, SiN x .
- the gate insulation layer 400 may be thicker than the capacitor dielectric layer 300 .
- the gate insulation layer 400 may have a thickness of about 4,000 ⁇ to about 4,500 ⁇ .
- the gate insulation layer 400 has a first contact hole 410 exposing a portion of the capacitor dielectric layer 300 .
- the active layer 500 is formed on the gate insulation layer 400 to cover the gate electrode 220 .
- the active layer 500 includes a semiconductor layer 510 and an ohmic contact layer 520 .
- the active layer 500 may include, for example, amorphous silicon (a-Si), and the ohmic contact layer 520 may include, for example, amorphous silicon (n+a-Si) having an n-type dopant doped therein in a high concentration.
- the data wiring 600 is formed on the gate insulation layer 400 having the active layer 500 formed thereon.
- the data wiring 600 includes the data line 610 , a source electrode 620 , a drain electrode 630 , and the upper storage electrode 640 .
- the data wiring 600 may include, for example, aluminum (Al), molybdenum (Mo), neodymium (Nd), chromium (Cr), tantalum (Ta), titanium (Ti), tungsten (W), copper (Cu), silver (Ag), and an alloy thereof.
- the data wiring 600 may have more than one layer having different characteristics.
- the data wiring 600 may have a three-layer structure of molybdenum (Mo), aluminum (Al), and molybdenum (Mo) stacked in that order.
- the data line 610 extends along a direction that crosses the direction of the gate lines 210 .
- the data line 610 may extend along a vertical direction, when viewed on a plane, to define left and right portions of the pixel P.
- the source and drain electrodes 620 and 630 are formed on the active layer 500 such that the source and drain electrodes 620 and 630 are spaced apart from each other.
- the source electrode 620 is connected to the data line 610 , to define a source terminal of the TFT section TFT.
- the drain electrode 630 is spaced apart from the source electrode 620 to define a drain terminal of the TFT section TFT.
- the upper storage electrode 640 is connected to the drain electrode 630 of the TFT section TFT.
- the upper storage electrode 640 overlaps the lower storage electrode 230 .
- a center portion of the upper storage electrode 640 is disposed on the capacitor dielectric layer 300 , which is exposed through the first contact hole 410 of the gate insulation layer 400 .
- the storage capacitor section Cst has an increased capacitance because the capacitor dielectric layer 300 , which may include SiO 2 having lower dielectric constant than SiN x that may be included in the gate insulation layer 400 and which may be thinner than the gate insulation layer 400 , is disposed between the lower and upper storage electrodes 230 and 640 , so that capacitance of the storage capacitor section Cst may be increased. If the capacitance is increased, the area of the storage capacitor section Cst may be reduced, so that the aperture ratio may be enhanced.
- the capacitor dielectric layer 300 which may include SiO 2 having lower dielectric constant than SiN x that may be included in the gate insulation layer 400 and which may be thinner than the gate insulation layer 400 , is disposed between the lower and upper storage electrodes 230 and 640 , so that capacitance of the storage capacitor section Cst may be increased. If the capacitance is increased, the area of the storage capacitor section Cst may be reduced, so that the aperture ratio may be enhanced.
- the TFT substrate 100 may further include a protection layer 700 formed on the substrate 110 having the data wiring 600 formed thereon.
- the protection layer 700 protects and insulates the TFT section TFT and the storage capacitor section Cst.
- the protection layer 700 may include, for example, SiN x , and may have a thickness of about 1,500 ⁇ to about 2,000 ⁇ .
- the TFT substrate 100 may further include an organic layer 750 formed on the protection layer 700 .
- the organic layer 750 planarizes a surface of the TFT substrate 100 .
- the TFT substrate 100 may further include a pixel electrode 800 formed on the protection layer 700 or the organic layer 750 in each pixel P.
- the pixel electrode 800 includes a transparent and conductive material, through which light can be transmitted.
- the pixel electrode 800 may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), etc.
- the pixel electrode 800 is connected to the drain electrode 630 through a third contact hole 760 formed through the protection layer 700 and the organic layer 750 .
- the TFT section TFT applies a data voltage, which is transferred through the data line 610 , to the pixel electrode 800 when the TFT section TFT receives a gate voltage through the gate wiring 210 .
- the storage capacitor section Cst maintains the data voltage of the pixel electrode 800 during one frame.
- the TFT substrate 100 may further include a pad section 900 through which a driver chip (not shown) for driving the TFT substrate 100 is connected to the TFT substrate 100 .
- the pad section 900 includes a gate metal pad 910 and a data metal pad 920 .
- the gate metal pad 910 may be formed from the same layer as the gate wiring 200
- the data metal pad 920 may be formed from the same layer as the data wiring 600 .
- the pad section 900 may further include a dummy active layer 570 formed from the same layer as the active layer 500 .
- the data metal pad 920 may be directly connected to the gate metal pad 910 through a second contact hole 420 formed through the gate insulation layer 400 and the dummy active layer 570 .
- connection reliability may be enhanced.
- the pad section 900 may further include a pad electrode 930 formed from the same layer as the pixel electrode 800 .
- the pad electrode 930 is connected to the data metal pad 920 through a fourth contact hole 770 formed through the protection layer 700 and the organic layer 750 .
- FIG. 3 , FIG. 4 , FIG. 5 , FIG. 6 , FIG. 7 , FIG. 8 , FIG. 9 , FIG. 10 , FIG. 11 , FIG. 12 , FIG. 13 , FIG. 14 , and FIG. 15 are cross-sectional views showing a method of manufacturing the TFT substrate in FIG. 2 .
- the gate wiring 200 including the gate electrode 220 and the lower storage electrode 230 , and the capacitor dielectric layer 300 disposed on the lower storage electrode 230 may be simultaneously formed through one mask process.
- FIG. 3 , FIG. 4 , FIG. 5 , FIG. 6 , and FIG. 7 are cross-sectional views showing a process of manufacturing the gate wiring and the capacitor dielectric layer.
- a gate metal layer 250 and a preliminary capacitor dielectric layer 310 are sequentially formed on the substrate 110 .
- the gate metal layer 250 may be formed through a sputtering process
- the preliminary capacitor dielectric layer 310 may be formed through a chemical vapor deposition (CVD) process.
- the gate metal layer 250 may include, for example, aluminum (Al), molybdenum (Mo), neodymium (Nd), chromium (Cr), tantalum (Ta), titanium (Ti), tungsten (W), copper (Cu), silver (Ag), or an alloy thereof. These may be used alone or in combination.
- the gate metal layer 250 may include two or more layers having different physical and chemical characteristics.
- the gate metal layer 250 may have a two-layer structure of aluminum (Al) and molybdenum (Mo) to reduce electric resistance.
- the preliminary capacitor dielectric layer 310 may include, for example, SiO 2 and may have a thickness of about 500 ⁇ to about 1,000 ⁇ .
- a first photoresist pattern PR 1 is formed on the preliminary capacitor dielectric layer 310 .
- the first photoresist pattern PR 1 may be formed such that the first photoresist pattern PR 1 in a capacitor dielectric layer region is thicker than the first photoresist pattern PR 1 in a gate electrode region.
- the different thicknesses of the first photoresist pattern PR 1 may be obtained by one process through a slit mask or a half-tone mask.
- the first photoresist pattern PR 1 is also formed in a gate metal pad region.
- the first photoresist pattern PR 1 in the gate metal pad region may have substantially the same thickness as that of the first photoresist pattern PR 1 in the gate electrode region.
- the preliminary capacitor dielectric layer 310 and the gate metal layer 250 are patterned using the first photoresist pattern PR 1 to form the gate wiring 200 including the gate electrode 220 and the lower storage electrode 230 , and the gate metal pad 910 .
- an etch-back process may be performed to reduce the thickness of the first photoresist pattern PR 1 by a predetermined thickness. As a result, the first photoresist patterns PR 1 in the gate electrode region and the gate metal pad region are removed, and the thinner first photoresist pattern PR 1 in the lower storage electrode region remains.
- the preliminary capacitor dielectric layer 310 is patterned using the thinner first photoresist pattern PR 1 in the lower storage electrode region. Then, the preliminary capacitor dielectric layer 310 in the gate electrode layer region and the gate metal pad region is removed, and the preliminary capacitor dielectric layer 310 in the lower storage electrode region remains to form the capacitor dielectric layer 300 .
- the first photoresist pattern PR 1 remaining on the capacitor dielectric layer 300 is removed.
- the capacitor dielectric layer 300 may be self-aligned on the lower storage electrode 230 .
- the gate metal layer 250 is patterned, an undercut of the gate metal layer 250 is generated under the capacitor dielectric layer 300 .
- the preliminary capacitor dielectric layer 310 is patterned, a side of the preliminary capacitor layer 310 may be etched so that the area of the capacitor dielectric layer 300 becomes no larger than the area of the lower storage electrode 230 .
- the gate insulation layer 400 and the active layer 500 are formed on the substrate 110 having the gate wiring 200 , the capacitor dielectric layer 300 and the gate metal pad 910 formed thereon.
- FIG. 8 , FIG. 9 , and FIG. 10 are cross-sectional views showing a process of forming the gate insulation layer and the active layer.
- the gate insulation layer 400 , a preliminary semiconductor layer 550 including amorphous silicon (a-Si), and a preliminary ohmic contact layer 560 including amorphous silicon (n+a-Si) having an n-type dopant doped therein are sequentially formed on the substrate 110 having the gate wiring 200 , the capacitor dielectric layer 300 , and the gate metal pad 910 formed thereon.
- the gate insulation layer 400 , the preliminary semiconductor layer 550 , and the preliminary ohmic contact layer 560 may be formed through, for example, a CVD method.
- the preliminary semiconductor layer 550 and the preliminary ohmic contact layer 560 are simultaneously patterned to form the active layer 500 disposed on the gate insulation layer 400 in the gate electrode region.
- the dummy active layer 570 may be formed on the gate insulation layer 400 in the gate metal pad region through a process of forming the active layer 500 .
- the first contact hole 410 is formed through the gate insulation layer 400 .
- the first contact hole 410 is formed in the capacitor dielectric layer region to expose the capacitor dielectric layer 300 .
- the second contact hole 420 is formed through the gate insulation layer 400 and the dummy active layer 570 in the gate metal pad region through a process of forming the first contact hole 410 .
- the gate insulation layer 400 , the active layer 500 , and the dummy active layer 570 having the first and second contact holes 410 and 420 may be formed through processes using two masks. However, the gate insulation layer 400 , the active layer 500 , and the dummy active layer 570 having the first and second contact holes 410 and 420 may be formed through a process using one mask.
- FIG. 11 , FIG. 12 , and FIG. 13 are cross-sectional views showing a process of manufacturing the gate insulation layer and the active pattern according to another exemplary embodiment of the present invention.
- a second photoresist pattern PR 2 is formed on the substrate 110 having the gate insulation layer 400 , the preliminary semiconductor layer 550 , and the preliminary ohmic contact layer 560 sequentially formed thereon as shown in FIG. 8 .
- the second photoresist pattern PR 2 is formed such that the second photoresist pattern PR 2 is opened in the capacitor dielectric layer region and has an increased thickness in the active layer region. Additionally, the second photoresist pattern PR 2 is opened in the gate metal pad region.
- the second photoresist pattern PR 2 may be formed such that the second photoresist pattern PR 2 is relatively thicker in the dummy active layer region like in the active layer region.
- the second photoresist pattern PR 2 having a different thickness may be formed through one process using a slit mask or a half-tone mask.
- the preliminary ohmic contact layer 560 , the preliminary semiconductor layer 550 and the gate insulation layer 400 in the capacitor dielectric layer region are patterned using the second photoresist pattern PR 2 .
- the preliminary ohmic contact layer 560 , the preliminary semiconductor layer 550 and the gate insulation layer 400 in the gate metal pad region may be simultaneously patterned.
- the first contact hole 410 exposing the capacitor dielectric layer and the second contact hole 420 exposing the gate metal pad 910 are formed through the gate insulation layer 400 .
- an etch-back process may be performed to reduce the thickness of the second photoresist pattern PR 2 by a predetermined thickness. Then, the second photoresist pattern PR 2 having a reduced thickness remains only in the active layer region and the dummy active layer region, and the second photoresist pattern PR 2 in the remaining regions is removed.
- the preliminary ohmic contact layer 560 and the preliminary semiconductor layer 550 are patterned using the second photoresist pattern PR 2 having a reduced thickness through the etch-back process. As a result, the preliminary ohmic contact layer 560 and the preliminary semiconductor layer 550 remain only in the active layer region and the dummy active layer region to form the active layer 500 and the dummy active layer 570 .
- the second photoresist pattern PR 2 having a reduced thickness is removed.
- the data wiring 600 including the source electrode 620 , the drain electrode 630 , and the upper storage electrode 640 is formed on the substrate 110 having the gate insulation layer 400 and the active layer 500 formed thereon.
- the source and drain electrodes 620 and 630 are disposed on the active layer 500 such that the source and drain electrodes 620 and 630 are spaced apart from each other.
- a portion of the upper storage electrode 640 is disposed on the capacitor dielectric layer 300 exposed through the first contact hole 410 formed through the gate insulation layer 400 .
- the data metal pad 920 is formed through a process of forming the data wiring 600 .
- the data metal pad 920 may be directly connected to the gate metal pad 910 through the second contact hole 420 formed through the gate insulation layer 400 and the dummy active layer 570 .
- the protection layer 700 is formed on the substrate 110 having the data wiring 600 formed thereon.
- the protection layer 700 protects and insulates the data wiring 600 .
- the protection layer 700 may include, for example, SiN x .
- the organic layer 750 may be formed on the protection layer 700 to planarize a surface of the TFT substrate 100 .
- the third contact hole 760 exposing a portion of the drain electrode 630 is formed through the protection layer 700 and the organic layer 750 through a process using a mask process. Additionally, the fourth contact hole 770 exposing the data metal pad 920 is formed through a process of forming the third contact hole 760 .
- the pixel electrode 800 is formed on the organic layer 750 .
- the pixel electrode 800 is connected to the drain electrode 630 via the third contact hole 760 formed through the protection layer 700 and the organic layer 750 .
- the pad electrode 930 may be formed through the process of forming the pixel electrode 800 .
- the pad electrode 930 is connected to the data metal pad 920 through the fourth contact hole 770 formed through the protection layer 700 and the organic layer 750 .
- the pixel electrode 800 and the pad electrode 930 are formed on the protection layer 700 .
- a capacitor dielectric layer including silicon oxide and being relatively thin is disposed between lower and upper storage electrodes defining a storage capacitor section, so that the capacitance of the storage capacitor section may be enhanced without deteriorating TFT characteristics. Furthermore, the area of the storage capacitor section may be reduced by as much as the capacitance of the storage capacitor section is increased to enhance the aperture ratio.
- the gate insulation layer in the capacitor dielectric layer region may be removed, so that no additional process may be required, thereby reducing manufacturing costs and enhancing productivity.
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Nonlinear Science (AREA)
- Manufacturing & Machinery (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Optics & Photonics (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
- This application is a divisional of U.S. patent application Ser. No. 11/944,010, filed on Nov. 21, 2007 and claims priority from and the benefit of Korean Patent Application No. 10-2006-0125231, filed on Dec. 11, 2006, which are hereby incorporated by reference for all purposes as if fully set forth herein.
- 1. Field of the Invention
- The present invention relates to a thin-film transistor (TFT) substrate. More particularly, the present invention relates to a TFT substrate and a method of manufacturing the TFT substrate.
- 2. Discussion of the Background
- A liquid crystal display (LCD) apparatus includes a thin-film transistor (TFT) substrate, a color filter substrate facing the TFT substrate, and a liquid crystal layer disposed between the TFT substrate and the color filter substrate.
- The TFT substrate has a plurality of pixels, each of which includes a TFT section and storage capacitor section, so that each pixel may be independently driven.
- In a display apparatus for a mobile electronic apparatus, enhancing the aperture ratio becomes very important because the display apparatus should have high resolution within a relatively small area. The most important factors for the aperture ratio include the area of the storage capacitor section and the adoption of fine lines.
- In order to reduce the area of the storage capacitor section, the thickness of a gate insulation layer may be reduced or the gate insulation layer may have a double-layered structure of silicon oxide (SiO2) and silicon nitride (SiNx).
- However, when the thickness of a gate insulation layer is excessively reduced, the gate insulation layer may become unreliable and vulnerable to electrostatic charges. When the gate insulation layer has the double-layered structure of SiO2 and SiNx, SiO2 may remain under a channel of a TFT and therefore, may deteriorate the TFT even though the capacitance of the storage capacitor section increases.
- The present invention provides a thin-film transistor (TFT) substrate that may be capable of enhancing an aperture ratio without deteriorating the TFT.
- The present invention also provides a method of manufacturing the TFT substrate.
- Additional features of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention.
- The present invention discloses a TFT substrate including a gate wiring, a capacitor dielectric layer, a gate insulation layer, an active pattern, a data wiring, a protection layer, and a pixel electrode. The gate wiring is disposed on the substrate. The gate wiring includes a gate electrode, a lower storage electrode, and a gate metal pad. The capacitor dielectric layer is disposed on the lower storage electrode. The gate insulation layer is disposed on the substrate. The active pattern includes an active layer and a dummy active layer disposed on the gate insulation layer in a gate electrode region and a gate metal pad region, respectively. The data wiring includes a source electrode, a drain electrode, an upper storage electrode, and a data metal pad. The source and drain electrodes are disposed on the active layer such that the source and drain electrodes are spaced apart from each other. A portion of the upper storage electrode is disposed on the capacitor dielectric layer exposed through a first contact hole in the gate insulation layer. The data metal pad is directly connected to the gate metal pad through a second contact hole in the gate insulation layer and the dummy active layer. The protection layer is disposed on the substrate. The pixel electrode is disposed on the protection layer and connected to the drain electrode.
- The present invention also discloses a method of manufacturing a TFT substrate including forming a gate wiring and a capacitor dielectric layer through a patterning process using one mask. The gate wiring including a gate electrode and a lower storage electrode is formed on a substrate. The capacitor dielectric layer is formed on the lower storage electrode. A gate insulation layer and an active layer are formed on the substrate. The gate insulation layer has a first contact hole in a capacitor dielectric layer region. The active layer is formed on the gate insulation layer to cover the gate electrode. A data wiring including a source electrode, a drain electrode, and an upper storage electrode is formed. The source and drain electrodes are disposed on the active layer such that the source and drain electrodes are spaced apart from each other. A portion of the upper storage electrode is disposed on the capacitor dielectric layer exposed through the first contact hole. A protection layer is formed on the substrate and then, a pixel electrode is formed on the protection layer. The pixel electrode is connected to the drain electrode.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the principles of the invention.
-
FIG. 1 is a layout showing a portion of a thin-film transistor (TFT) substrate according to an exemplary embodiment of the present invention. -
FIG. 2 is a cross-sectional view showing the TFT section, the storage capacitor section, and the pad section ofFIG. 1 . -
FIG. 3 ,FIG. 4 ,FIG. 5 ,FIG. 6 ,FIG. 7 ,FIG. 8 ,FIG. 9 ,FIG. 10 ,FIG. 11 ,FIG. 12 ,FIG. 13 ,FIG. 14 , andFIG. 15 are cross-sectional views showing a method of manufacturing the TFT substrate inFIG. 2 . - The invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.
- It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numbers refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
- It will be understood that, although the terms first, second, third etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
- Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
- The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
- Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.
- Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
- Hereinafter, exemplary embodiments of the present invention will be explained in detail with reference to the accompanying drawings.
-
FIG. 1 is a layout showing a portion of a thin-film transistor (TFT) substrate according to an exemplary embodiment of the present invention, andFIG. 2 is a cross-sectional view showing the TFT section, the storage capacitor section, and the pad section ofFIG. 1 . - Referring to
FIG. 1 andFIG. 2 , aTFT substrate 100 includes agate wiring 200, acapacitor dielectric layer 300, agate insulation layer 400, anactive layer 500, and adata wiring 600. - The
gate wiring 200 is formed on asubstrate 110. Thegate wiring 200 includes agate line 210, agate electrode 220, and alower storage electrode 230. - The
substrate 110 may include a transparent and dielectric material, for example, glass or plastic. - The
gate wiring 200 may include, for example, aluminum (Al), molybdenum (Mo), neodymium (Nd), chromium (Cr), tantalum (Ta), titanium (Ti), tungsten (W), copper (Cu), silver (Ag), or an alloy thereof. These may be used alone or in combination. Thegate wiring 200 may include more than one layer having different physical and chemical characteristics. For example, thegate wiring 200 may have a two-layer structure of aluminum (Al) and molybdenum (Mo) to reduce electric resistance. - The gate lines 210 may extend, for example, along a horizontal direction, when viewed on a plane, to define lower and upper portions of pixel P.
- The
gate electrode 220 is connected to thegate line 210. Thegate electrode 220 defines a gate terminal of a TFT section TFT formed in the pixel P. - The
lower storage electrode 230 is isolated from thegate line 210 and thegate electrode 220. In other words, thelower storage electrode 230 is insulated from thegate line 210 and thegate electrode 220. Thelower storage electrode 230 defines a lower electrode of a storage capacitor section Cst. Thelower storage electrode 230 overlaps anupper storage electrode 640. Thelower storage electrode 230 may partially overlap adata line 610 to increase the capacitance of the storage capacitor section Cst. Thelower storage electrode 230 receives a reference voltage. - The
capacitor dielectric layer 300 is formed on thelower storage electrode 230. Thecapacitor dielectric layer 300 separates thelower storage electrode 230 from theupper storage electrode 640 so that the lower andupper storage electrodes - In order to increase the capacitance of the storage capacitor section Cst, the
capacitor dielectric layer 300 includes silicon oxide (SiO2) having a higher dielectric constant than silicon nitride (SiNx). Additionally, thecapacitor dielectric layer 300 may have a thickness of no more than about 1,000 Å to increase the capacitance of the storage capacitor section Cst. For example, thecapacitor dielectric layer 300 may have a thickness of about 500 Å to about 1,000 Å. - The
gate insulation layer 400 is formed on thesubstrate 110 having thegate wiring 200 and thecapacitor dielectric layer 300 formed thereon. Thegate insulation layer 400 protects and insulates thegate wiring 200 from other conductors. Thegate insulation layer 400 may include, for example, SiNx. Thegate insulation layer 400 may be thicker than thecapacitor dielectric layer 300. For example, thegate insulation layer 400 may have a thickness of about 4,000 Å to about 4,500 Å. - The
gate insulation layer 400 has afirst contact hole 410 exposing a portion of thecapacitor dielectric layer 300. - The
active layer 500 is formed on thegate insulation layer 400 to cover thegate electrode 220. Theactive layer 500 includes asemiconductor layer 510 and anohmic contact layer 520. Theactive layer 500 may include, for example, amorphous silicon (a-Si), and theohmic contact layer 520 may include, for example, amorphous silicon (n+a-Si) having an n-type dopant doped therein in a high concentration. - The
data wiring 600 is formed on thegate insulation layer 400 having theactive layer 500 formed thereon. Thedata wiring 600 includes thedata line 610, asource electrode 620, adrain electrode 630, and theupper storage electrode 640. - The data wiring 600 may include, for example, aluminum (Al), molybdenum (Mo), neodymium (Nd), chromium (Cr), tantalum (Ta), titanium (Ti), tungsten (W), copper (Cu), silver (Ag), and an alloy thereof. The data wiring 600 may have more than one layer having different characteristics. For example, the data wiring 600 may have a three-layer structure of molybdenum (Mo), aluminum (Al), and molybdenum (Mo) stacked in that order.
- The
data line 610 extends along a direction that crosses the direction of the gate lines 210. Thedata line 610 may extend along a vertical direction, when viewed on a plane, to define left and right portions of the pixel P. - The source and drain
electrodes active layer 500 such that the source and drainelectrodes source electrode 620 is connected to thedata line 610, to define a source terminal of the TFT section TFT. Thedrain electrode 630 is spaced apart from thesource electrode 620 to define a drain terminal of the TFT section TFT. - The
upper storage electrode 640 is connected to thedrain electrode 630 of the TFT section TFT. Theupper storage electrode 640 overlaps thelower storage electrode 230. A center portion of theupper storage electrode 640 is disposed on thecapacitor dielectric layer 300, which is exposed through thefirst contact hole 410 of thegate insulation layer 400. - As described above, the storage capacitor section Cst has an increased capacitance because the
capacitor dielectric layer 300, which may include SiO2 having lower dielectric constant than SiNx that may be included in thegate insulation layer 400 and which may be thinner than thegate insulation layer 400, is disposed between the lower andupper storage electrodes - The
TFT substrate 100 may further include aprotection layer 700 formed on thesubstrate 110 having the data wiring 600 formed thereon. Theprotection layer 700 protects and insulates the TFT section TFT and the storage capacitor section Cst. Theprotection layer 700 may include, for example, SiNx, and may have a thickness of about 1,500 Å to about 2,000 Å. - The
TFT substrate 100 may further include anorganic layer 750 formed on theprotection layer 700. Theorganic layer 750 planarizes a surface of theTFT substrate 100. - The
TFT substrate 100 may further include apixel electrode 800 formed on theprotection layer 700 or theorganic layer 750 in each pixel P. Thepixel electrode 800 includes a transparent and conductive material, through which light can be transmitted. Thepixel electrode 800 may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), etc. - The
pixel electrode 800 is connected to thedrain electrode 630 through athird contact hole 760 formed through theprotection layer 700 and theorganic layer 750. - The TFT section TFT applies a data voltage, which is transferred through the
data line 610, to thepixel electrode 800 when the TFT section TFT receives a gate voltage through thegate wiring 210. The storage capacitor section Cst maintains the data voltage of thepixel electrode 800 during one frame. - The
TFT substrate 100 may further include apad section 900 through which a driver chip (not shown) for driving theTFT substrate 100 is connected to theTFT substrate 100. - The
pad section 900 includes agate metal pad 910 and adata metal pad 920. Thegate metal pad 910 may be formed from the same layer as thegate wiring 200, and thedata metal pad 920 may be formed from the same layer as thedata wiring 600. Thepad section 900 may further include a dummyactive layer 570 formed from the same layer as theactive layer 500. - The
data metal pad 920 may be directly connected to thegate metal pad 910 through asecond contact hole 420 formed through thegate insulation layer 400 and the dummyactive layer 570. When thedata metal pad 920 is directly connected to thegate metal pad 910, connection reliability may be enhanced. - The
pad section 900 may further include apad electrode 930 formed from the same layer as thepixel electrode 800. Thepad electrode 930 is connected to thedata metal pad 920 through afourth contact hole 770 formed through theprotection layer 700 and theorganic layer 750. - Hereinafter, a method of manufacturing the TFT substrate in
FIG. 1 andFIG. 2 will be explained. -
FIG. 3 ,FIG. 4 ,FIG. 5 ,FIG. 6 ,FIG. 7 ,FIG. 8 ,FIG. 9 ,FIG. 10 ,FIG. 11 ,FIG. 12 ,FIG. 13 ,FIG. 14 , andFIG. 15 are cross-sectional views showing a method of manufacturing the TFT substrate inFIG. 2 . - In
FIG. 2 , thegate wiring 200 including thegate electrode 220 and thelower storage electrode 230, and thecapacitor dielectric layer 300 disposed on thelower storage electrode 230 may be simultaneously formed through one mask process. -
FIG. 3 ,FIG. 4 ,FIG. 5 ,FIG. 6 , andFIG. 7 are cross-sectional views showing a process of manufacturing the gate wiring and the capacitor dielectric layer. - Referring to
FIG. 2 andFIG. 3 , agate metal layer 250 and a preliminarycapacitor dielectric layer 310 are sequentially formed on thesubstrate 110. For example, thegate metal layer 250 may be formed through a sputtering process, and the preliminarycapacitor dielectric layer 310 may be formed through a chemical vapor deposition (CVD) process. - The
gate metal layer 250 may include, for example, aluminum (Al), molybdenum (Mo), neodymium (Nd), chromium (Cr), tantalum (Ta), titanium (Ti), tungsten (W), copper (Cu), silver (Ag), or an alloy thereof. These may be used alone or in combination. Thegate metal layer 250 may include two or more layers having different physical and chemical characteristics. For example, thegate metal layer 250 may have a two-layer structure of aluminum (Al) and molybdenum (Mo) to reduce electric resistance. - The preliminary
capacitor dielectric layer 310 may include, for example, SiO2 and may have a thickness of about 500 Å to about 1,000 Å. - Referring to
FIG. 2 andFIG. 4 , a first photoresist pattern PR1 is formed on the preliminarycapacitor dielectric layer 310. The first photoresist pattern PR1 may be formed such that the first photoresist pattern PR1 in a capacitor dielectric layer region is thicker than the first photoresist pattern PR1 in a gate electrode region. The different thicknesses of the first photoresist pattern PR1 may be obtained by one process through a slit mask or a half-tone mask. - The first photoresist pattern PR1 is also formed in a gate metal pad region. The first photoresist pattern PR1 in the gate metal pad region may have substantially the same thickness as that of the first photoresist pattern PR1 in the gate electrode region.
- Referring to
FIG. 4 andFIG. 5 , the preliminarycapacitor dielectric layer 310 and thegate metal layer 250 are patterned using the first photoresist pattern PR1 to form thegate wiring 200 including thegate electrode 220 and thelower storage electrode 230, and thegate metal pad 910. - Referring to
FIG. 6 , an etch-back process may be performed to reduce the thickness of the first photoresist pattern PR1 by a predetermined thickness. As a result, the first photoresist patterns PR1 in the gate electrode region and the gate metal pad region are removed, and the thinner first photoresist pattern PR1 in the lower storage electrode region remains. - Referring to
FIG. 6 andFIG. 7 , the preliminarycapacitor dielectric layer 310 is patterned using the thinner first photoresist pattern PR1 in the lower storage electrode region. Then, the preliminarycapacitor dielectric layer 310 in the gate electrode layer region and the gate metal pad region is removed, and the preliminarycapacitor dielectric layer 310 in the lower storage electrode region remains to form thecapacitor dielectric layer 300. - Then, the first photoresist pattern PR1 remaining on the
capacitor dielectric layer 300 is removed. - As described above, when the
gate wiring 200 including thegate electrode 220 and thelower storage electrode 230, and thecapacitor dielectric layer 300 are simultaneously formed through the same patterning process using one mask, thecapacitor dielectric layer 300 may be self-aligned on thelower storage electrode 230. When thegate metal layer 250 is patterned, an undercut of thegate metal layer 250 is generated under thecapacitor dielectric layer 300. However, when the preliminarycapacitor dielectric layer 310 is patterned, a side of thepreliminary capacitor layer 310 may be etched so that the area of thecapacitor dielectric layer 300 becomes no larger than the area of thelower storage electrode 230. - Then, the
gate insulation layer 400 and theactive layer 500 are formed on thesubstrate 110 having thegate wiring 200, thecapacitor dielectric layer 300 and thegate metal pad 910 formed thereon. -
FIG. 8 ,FIG. 9 , andFIG. 10 are cross-sectional views showing a process of forming the gate insulation layer and the active layer. - Referring to
FIG. 8 , thegate insulation layer 400, apreliminary semiconductor layer 550 including amorphous silicon (a-Si), and a preliminaryohmic contact layer 560 including amorphous silicon (n+a-Si) having an n-type dopant doped therein are sequentially formed on thesubstrate 110 having thegate wiring 200, thecapacitor dielectric layer 300, and thegate metal pad 910 formed thereon. Thegate insulation layer 400, thepreliminary semiconductor layer 550, and the preliminaryohmic contact layer 560 may be formed through, for example, a CVD method. - Referring to
FIG. 8 andFIG. 9 , thepreliminary semiconductor layer 550 and the preliminaryohmic contact layer 560 are simultaneously patterned to form theactive layer 500 disposed on thegate insulation layer 400 in the gate electrode region. The dummyactive layer 570 may be formed on thegate insulation layer 400 in the gate metal pad region through a process of forming theactive layer 500. - Referring to
FIG. 10 , thefirst contact hole 410 is formed through thegate insulation layer 400. Thefirst contact hole 410 is formed in the capacitor dielectric layer region to expose thecapacitor dielectric layer 300. Thesecond contact hole 420 is formed through thegate insulation layer 400 and the dummyactive layer 570 in the gate metal pad region through a process of forming thefirst contact hole 410. - The
gate insulation layer 400, theactive layer 500, and the dummyactive layer 570 having the first and second contact holes 410 and 420 may be formed through processes using two masks. However, thegate insulation layer 400, theactive layer 500, and the dummyactive layer 570 having the first and second contact holes 410 and 420 may be formed through a process using one mask. -
FIG. 11 ,FIG. 12 , andFIG. 13 are cross-sectional views showing a process of manufacturing the gate insulation layer and the active pattern according to another exemplary embodiment of the present invention. - Referring to
FIG. 2 andFIG. 11 , a second photoresist pattern PR2 is formed on thesubstrate 110 having thegate insulation layer 400, thepreliminary semiconductor layer 550, and the preliminaryohmic contact layer 560 sequentially formed thereon as shown inFIG. 8 . - The second photoresist pattern PR2 is formed such that the second photoresist pattern PR2 is opened in the capacitor dielectric layer region and has an increased thickness in the active layer region. Additionally, the second photoresist pattern PR2 is opened in the gate metal pad region. The second photoresist pattern PR2 may be formed such that the second photoresist pattern PR2 is relatively thicker in the dummy active layer region like in the active layer region. The second photoresist pattern PR2 having a different thickness may be formed through one process using a slit mask or a half-tone mask.
- Then, the preliminary
ohmic contact layer 560, thepreliminary semiconductor layer 550 and thegate insulation layer 400 in the capacitor dielectric layer region are patterned using the second photoresist pattern PR2. The preliminaryohmic contact layer 560, thepreliminary semiconductor layer 550 and thegate insulation layer 400 in the gate metal pad region may be simultaneously patterned. As a result, thefirst contact hole 410 exposing the capacitor dielectric layer and thesecond contact hole 420 exposing thegate metal pad 910 are formed through thegate insulation layer 400. - Referring to
FIG. 11 andFIG. 12 , an etch-back process may be performed to reduce the thickness of the second photoresist pattern PR2 by a predetermined thickness. Then, the second photoresist pattern PR2 having a reduced thickness remains only in the active layer region and the dummy active layer region, and the second photoresist pattern PR2 in the remaining regions is removed. - Referring to
FIG. 12 andFIG. 13 , the preliminaryohmic contact layer 560 and thepreliminary semiconductor layer 550 are patterned using the second photoresist pattern PR2 having a reduced thickness through the etch-back process. As a result, the preliminaryohmic contact layer 560 and thepreliminary semiconductor layer 550 remain only in the active layer region and the dummy active layer region to form theactive layer 500 and the dummyactive layer 570. - Then, the second photoresist pattern PR2 having a reduced thickness is removed.
- As described above, when the process of forming the
active layer 500 and the dummyactive layer 570 and the process of forming the first and second contact holes 410 and 420 through thegate insulation layer 400 are simultaneously performed using one mask, manufacturing costs may be reduced and productivity may be enhanced. - Referring to
FIG. 14 , the data wiring 600 including thesource electrode 620, thedrain electrode 630, and theupper storage electrode 640 is formed on thesubstrate 110 having thegate insulation layer 400 and theactive layer 500 formed thereon. - The source and drain
electrodes active layer 500 such that the source and drainelectrodes upper storage electrode 640 is disposed on thecapacitor dielectric layer 300 exposed through thefirst contact hole 410 formed through thegate insulation layer 400. - The
data metal pad 920 is formed through a process of forming the data wiring 600. Thedata metal pad 920 may be directly connected to thegate metal pad 910 through thesecond contact hole 420 formed through thegate insulation layer 400 and the dummyactive layer 570. - Referring to
FIG. 15 , theprotection layer 700 is formed on thesubstrate 110 having the data wiring 600 formed thereon. Theprotection layer 700 protects and insulates thedata wiring 600. Theprotection layer 700 may include, for example, SiNx. - The
organic layer 750 may be formed on theprotection layer 700 to planarize a surface of theTFT substrate 100. - Then, the
third contact hole 760 exposing a portion of thedrain electrode 630 is formed through theprotection layer 700 and theorganic layer 750 through a process using a mask process. Additionally, thefourth contact hole 770 exposing thedata metal pad 920 is formed through a process of forming thethird contact hole 760. - Referring again to
FIG. 2 , thepixel electrode 800 is formed on theorganic layer 750. Thepixel electrode 800 is connected to thedrain electrode 630 via thethird contact hole 760 formed through theprotection layer 700 and theorganic layer 750. - Additionally, the
pad electrode 930 may be formed through the process of forming thepixel electrode 800. Thepad electrode 930 is connected to thedata metal pad 920 through thefourth contact hole 770 formed through theprotection layer 700 and theorganic layer 750. - When the
organic layer 750 is not formed, thepixel electrode 800 and thepad electrode 930 are formed on theprotection layer 700. - According to the TFT substrate and the method of manufacturing the TFT substrate described above, a capacitor dielectric layer including silicon oxide and being relatively thin is disposed between lower and upper storage electrodes defining a storage capacitor section, so that the capacitance of the storage capacitor section may be enhanced without deteriorating TFT characteristics. Furthermore, the area of the storage capacitor section may be reduced by as much as the capacitance of the storage capacitor section is increased to enhance the aperture ratio.
- Additionally, when a contact hole for connecting the data metal pad to the gate metal pad is formed through the gate insulation layer, the gate insulation layer in the capacitor dielectric layer region may be removed, so that no additional process may be required, thereby reducing manufacturing costs and enhancing productivity.
- It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Claims (5)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/605,647 US7888674B2 (en) | 2006-12-11 | 2009-10-26 | Thin-film transistor substrate and method of manufacturing the same |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2006-0125231 | 2006-12-11 | ||
KR1020060125231A KR101353269B1 (en) | 2006-12-11 | 2006-12-11 | Thin film transistor substrate and method for manufacturing the same |
US11/944,010 US7608493B2 (en) | 2006-12-11 | 2007-11-21 | Thin-film transistor substrate and method of manufacturing the same |
US12/605,647 US7888674B2 (en) | 2006-12-11 | 2009-10-26 | Thin-film transistor substrate and method of manufacturing the same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/944,010 Division US7608493B2 (en) | 2006-12-11 | 2007-11-21 | Thin-film transistor substrate and method of manufacturing the same |
Publications (2)
Publication Number | Publication Date |
---|---|
US20100044712A1 true US20100044712A1 (en) | 2010-02-25 |
US7888674B2 US7888674B2 (en) | 2011-02-15 |
Family
ID=39496903
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/944,010 Active 2028-01-03 US7608493B2 (en) | 2006-12-11 | 2007-11-21 | Thin-film transistor substrate and method of manufacturing the same |
US12/605,647 Active US7888674B2 (en) | 2006-12-11 | 2009-10-26 | Thin-film transistor substrate and method of manufacturing the same |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/944,010 Active 2028-01-03 US7608493B2 (en) | 2006-12-11 | 2007-11-21 | Thin-film transistor substrate and method of manufacturing the same |
Country Status (2)
Country | Link |
---|---|
US (2) | US7608493B2 (en) |
KR (1) | KR101353269B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8674359B2 (en) | 2010-06-09 | 2014-03-18 | Samsung Display Co., Ltd. | TFT, array substrate for display apparatus including TFT, and methods of manufacturing TFT and array substrate |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI358820B (en) * | 2008-02-29 | 2012-02-21 | Chunghwa Picture Tubes Ltd | Active device array substrate and fabrication meth |
KR101432126B1 (en) * | 2008-07-23 | 2014-08-21 | 삼성디스플레이 주식회사 | Organic Light Emitting Display |
KR101540341B1 (en) | 2008-10-17 | 2015-07-30 | 삼성전자주식회사 | Panel structure, display device comprising the panel structure and manufacturing methods thereof |
TWI383232B (en) * | 2009-03-19 | 2013-01-21 | Au Optronics Corp | Thin film transistor array substrate |
KR101724558B1 (en) * | 2010-04-19 | 2017-04-10 | 삼성디스플레이 주식회사 | Thin film transistor array panel and method for manufacturing the same |
JP2012204548A (en) * | 2011-03-24 | 2012-10-22 | Sony Corp | Display device and manufacturing method therefor |
KR102198029B1 (en) * | 2012-06-15 | 2021-01-05 | 소니 주식회사 | Display device, semiconductor device and method for manufacturing display device |
CN103413811B (en) * | 2013-07-23 | 2016-04-13 | 北京京东方光电科技有限公司 | Array base palte and manufacture method, display unit |
CN104617132B (en) * | 2014-12-31 | 2017-05-10 | 深圳市华星光电技术有限公司 | Low-temperature polycrystalline silicon thin film transistor and manufacturing method thereof |
KR20180066945A (en) | 2016-12-09 | 2018-06-20 | 삼성디스플레이 주식회사 | Display device |
KR20210002285A (en) * | 2019-06-28 | 2021-01-07 | 삼성디스플레이 주식회사 | Display apparatus and the manufacturing method thereof |
CN111710727A (en) | 2020-06-12 | 2020-09-25 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6038003A (en) * | 1997-06-11 | 2000-03-14 | Lg. Philips Lcd Co., Ltd. | Liquid crystal display and method of manufacturing the same |
US6674495B1 (en) * | 1999-09-30 | 2004-01-06 | Samsung Electronics Co., Ltd. | Thin film transistor array panel for a liquid crystal display and methods for manufacturing the same |
US7112512B2 (en) * | 2003-11-26 | 2006-09-26 | Hannstar Display Corporation | Method of manufacturing liquid crystal display |
US20070262347A1 (en) * | 2006-05-10 | 2007-11-15 | Chun-Gi You | Display substrate, method for manufacturing the same and display apparatus having the same |
US7351623B2 (en) * | 2004-05-27 | 2008-04-01 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display device and fabricating method thereof |
US7563627B2 (en) * | 2003-10-30 | 2009-07-21 | Lg Display Co., Ltd. | Method of manufacturing thin film transistor array substrate |
US7580088B2 (en) * | 2001-10-22 | 2009-08-25 | Samsung Electronics Co., Ltd. | Contact for semiconductor and display devices |
-
2006
- 2006-12-11 KR KR1020060125231A patent/KR101353269B1/en not_active IP Right Cessation
-
2007
- 2007-11-21 US US11/944,010 patent/US7608493B2/en active Active
-
2009
- 2009-10-26 US US12/605,647 patent/US7888674B2/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6038003A (en) * | 1997-06-11 | 2000-03-14 | Lg. Philips Lcd Co., Ltd. | Liquid crystal display and method of manufacturing the same |
US6674495B1 (en) * | 1999-09-30 | 2004-01-06 | Samsung Electronics Co., Ltd. | Thin film transistor array panel for a liquid crystal display and methods for manufacturing the same |
US7580088B2 (en) * | 2001-10-22 | 2009-08-25 | Samsung Electronics Co., Ltd. | Contact for semiconductor and display devices |
US7563627B2 (en) * | 2003-10-30 | 2009-07-21 | Lg Display Co., Ltd. | Method of manufacturing thin film transistor array substrate |
US7112512B2 (en) * | 2003-11-26 | 2006-09-26 | Hannstar Display Corporation | Method of manufacturing liquid crystal display |
US7351623B2 (en) * | 2004-05-27 | 2008-04-01 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display device and fabricating method thereof |
US20070262347A1 (en) * | 2006-05-10 | 2007-11-15 | Chun-Gi You | Display substrate, method for manufacturing the same and display apparatus having the same |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8674359B2 (en) | 2010-06-09 | 2014-03-18 | Samsung Display Co., Ltd. | TFT, array substrate for display apparatus including TFT, and methods of manufacturing TFT and array substrate |
Also Published As
Publication number | Publication date |
---|---|
US7888674B2 (en) | 2011-02-15 |
US7608493B2 (en) | 2009-10-27 |
KR20080053541A (en) | 2008-06-16 |
US20080135845A1 (en) | 2008-06-12 |
KR101353269B1 (en) | 2014-01-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7888674B2 (en) | Thin-film transistor substrate and method of manufacturing the same | |
US7851920B2 (en) | Wire structure, method for fabricating wire, thin film transistor substrate, and method for fabricating thin film transistor substrate | |
US7435629B2 (en) | Thin film transistor array panel and a manufacturing method thereof | |
US7649583B2 (en) | Semiconductor structure and fabricating method thereof for liquid crystal display device | |
US7336324B2 (en) | Array substrate for liquid crystal display device and fabricating method thereof | |
US8759833B2 (en) | Thin film transistor array panel and method of manufacturing the same | |
US8492190B2 (en) | Method for manufacturing display panel | |
US7638373B2 (en) | Method of manufacturing a thin-film transistor substrate | |
US20090224257A1 (en) | Thin film transistor panel and manufacturing method of the same | |
US7616267B2 (en) | Pixel structure for flat panel display | |
US8405082B2 (en) | Thin film transistor array substrate and manufacturing method thereof | |
US7504661B2 (en) | Thin film transistor substrate and fabricating method thereof | |
US7525624B2 (en) | Liquid crystal display device and fabricating method thereof | |
US20120126233A1 (en) | Thin film transistor array panel and method for manufacturing the same | |
KR20090077117A (en) | Display substrate and method of manufacturing the same | |
US20070262347A1 (en) | Display substrate, method for manufacturing the same and display apparatus having the same | |
US20100006844A1 (en) | Thin-film transistor array panel and method of fabricating the same | |
US8624246B2 (en) | Display device and method of manufacturing the same | |
JP2002190598A (en) | Thin-film transistor array substrate and method of manufacturing the same | |
US8111342B2 (en) | Display substrate, method of manufacturing the same and display device using the display substrate | |
US7541225B2 (en) | Method of manufacturing a thin film transistor array panel that includes using chemical mechanical polishing of a conductive film to form a pixel electrode connected to a drain electrode | |
KR20070109162A (en) | Thin film transistor substrate and method of manufacturig the same | |
KR20080045961A (en) | Thin film transistor substrate and metod of fabricating the same | |
KR20080109107A (en) | Display substrate and method of manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: SAMSUNG DISPLAY CO., LTD., KOREA, REPUBLIC OF Free format text: CHANGE OF NAME;ASSIGNOR:SAMSUNG ELECTRONICS CO., LTD.;REEL/FRAME:028859/0773 Effective date: 20120403 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552) Year of fee payment: 8 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |