US20090148970A1 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
US20090148970A1
US20090148970A1 US12/255,312 US25531208A US2009148970A1 US 20090148970 A1 US20090148970 A1 US 20090148970A1 US 25531208 A US25531208 A US 25531208A US 2009148970 A1 US2009148970 A1 US 2009148970A1
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Prior art keywords
photoresist
forming
semiconductor layer
conductive film
semiconductor
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US12/255,312
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Kunio Hosoya
Saishi Fujikawa
Yoko Chiba
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Orange SA
Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Assigned to SEMICONDUCTOR ENERGY LABORATORY CO., LTD. reassignment SEMICONDUCTOR ENERGY LABORATORY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHIBA, YOKO, FUJIKAWA, SAISHI, HOSOYA, KUNIO
Publication of US20090148970A1 publication Critical patent/US20090148970A1/en
Assigned to ORANGE reassignment ORANGE CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: FRANCE TELECOM
Priority to US14/282,593 priority Critical patent/US9564517B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0316—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral bottom-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to a method for manufacturing semiconductor devices, in particular, a method for manufacturing active matrix display devices.
  • liquid crystal display devices utilizing, as switching elements, TFTs each formed using amorphous silicon have been often used as display devices which have been widely used, such as liquid crystal televisions, displays of personal computers, and cellular phones.
  • a technique by which a TFT is formed using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention.
  • the TFT has been widely applied to electronic devices such as ICs and electro-optical devices and particularly developed as a switching element of an image display device.
  • Patent Document 1 Japanese Patent Application No. 2000-131719
  • Patent Document 2 Japanese Patent Application No. 2003-45893
  • FIGS. 10A to 10E are structural views illustrating a conventional TFT using amorphous silicon.
  • a gate electrode 501 is formed over a glass substrate 500 by a photolithography step using a first photomask ( FIG. 10A ).
  • a gate insulating film 502 , an i-type amorphous silicon layer 503 , and an n + -type amorphous silicon layer 504 are formed.
  • the i-type amorphous silicon layer 503 and the n + -type amorphous silicon layer 504 form an island region by a photolithography step using a second photomask ( FIG. 10B ).
  • a source electrode 508 and a drain electrode 509 are formed by a photolithography step using a third photomask. At that time, a photoresist formed by the third photomask is successively utilized to etch the n + -type amorphous silicon layer so that a channel region 505 , a source region 506 , and a drain region 507 are formed.
  • a protective film 510 is formed, and a contact hole through which a contact with a pixel electrode 511 is made is formed by a photolithography step using a fourth photomask ( FIG. 1C ).
  • ITO Indium tin oxide
  • the pixel electrode 511 is formed by a photolithography step using a fifth photomask ( FIGS. 10D and 10E ).
  • Photolithography steps using a photomask includes application of a photoresist, pre-baking, a step of light exposure using a metal photomask, a step of development, post-baking, a step of etching, a step of resist separation, and the like.
  • steps such as a step of cleaning and a step of inspection are included in the photolithography steps.
  • performing the conventional process using five photomasks means that the steps are repeated five times, which is a significant factor in the decrease in throughput in the manufacturing process or the increase in manufacturing cost.
  • reduction in number of photomasks means reduction in manufacturing time and manufacturing cost and thus has been anticipated.
  • reduction in number of photomasks has been a major object. Further, reduction in number of steps is another object.
  • the present invention adopts a channel-etched bottom gate TFT structure in which a photoresist is selectively exposed to light by rear surface exposure utilizing a gate wiring to form a desirably patterned photoresist, and further, in which a halftone mask or a gray-tone mask is used as a multi-tone mask. Further, the present invention includes a step of lifting off using a halftone mask or a gray-tone mask and a step of performing a reflow process on a photoresist.
  • the step of lifting off is a method in which a pattern other than a target pattern is formed of a photoresist or the like over a substrate, a target thin film is formed, and then an unnecessary portion which overlaps with the photoresist and the photoresist are removed together so that the target pattern is left.
  • the reflow process is a step of processing a photoresist over a substrate by heat treatment or chemical treatment.
  • a method for manufacturing a semiconductor device includes the steps of forming a first conductive film over a substrate; etching the first conductive film using a first photoresist to form a gate electrode; forming a gate insulating film over the gate electrode; forming a first semiconductor layer (e.g. an i-type semiconductor layer) over the gate insulating film; forming a second semiconductor layer including the impurity element imparting one conductivity type (e.g.
  • n + -type semiconductor layer over the first semiconductor layer; performing rear surface exposure to form a second photoresist; etching the first semiconductor layer and the second semiconductor layer to form a first semiconductor island and a second semiconductor island using the second photoresist; forming a second conductive film over the second semiconductor island; forming a third photoresist using a multi-tone mask; etching the second conductive film, the second semiconductor island, and the first semiconductor island using the third photoresist; ashing the third photoresist; etching the second conductive film using the third photoresist having been ashed to form a source electrode and a drain electrode; etching the second semiconductor island and the first semiconductor island using the third photoresist having been ashed to form a channel region, a source region, and a drain region; forming an insulating film over the source electrode and the drain electrode; forming a contact hole in the insulating film using a fourth photoresist; forming a conductive film over the insulating film
  • a method for manufacturing a semiconductor device includes the steps of forming a first conductive film over a substrate; etching the first conductive film using a first photoresist to form a gate electrode; forming a gate insulating film over the gate electrode; forming a first semiconductor layer (e.g. an i-type semiconductor layer) over the gate insulating film; forming a second semiconductor layer including the impurity element imparting one conductivity type (e.g.
  • n + -type semiconductor layer over the first semiconductor layer; performing rear surface exposure to form a second photoresist; etching the first semiconductor layer and the second semiconductor layer to form a first semiconductor island and a second semiconductor island using the second photoresist; forming a second conductive film over the second semiconductor layer; forming a third photoresist using a first multi-tone mask; etching the second conductive film, the second semiconductor layer, and the first semiconductor layer using the third photoresist; ashing the third photoresist; etching the second conductive film using the third photoresist having been ashed to form a source electrode and a drain electrode; etching the second semiconductor layer and the first semiconductor layer using the third photoresist having been ashed to form a channel region, a source region, and a drain region; forming a fourth photoresist using a second multi-tone mask; forming a contact hole in the gate insulating film using the fourth photoresist; ashing the fourth photoresist;
  • a TFT can be manufactured using four or three photomasks and thus manufacturing time and cost can be reduced.
  • a self-aligning step is performed and thus a step of aligning the photomask is not required. In the self-aligning step, it doesn't occur that the photomask is out of position; therefore, a margin for misalignment is not required and a more refined pattern can be formed. Further, a channel region is protected from light from external by a gate electrode, so that an increase of a leakage current when the TFT is off can be suppressed.
  • the TFT is entirely covered with an insulating film and thus reliability of elements can be improved. That is, an end portion of a source electrode can be surely covered so that a TFT can be prevented from being contaminated.
  • An i-type amorphous silicon layer, an n + -type amorphous silicon layer, a source metal, and a drain metal are etched all at once by the conventional halftone technique. Therefore, the i-type amorphous silicon layer is connected between the elements.
  • an i-type amorphous silicon layer and an n + -type amorphous silicon layer are formed into an island region by using a photoresist patterned desirably by rear surface exposure; therefore, the i-type amorphous silicon layer is cut and thus the elements can be more surely separated from each other.
  • FIGS. 1A to 1E are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention
  • FIGS. 2A to 2D are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention
  • FIGS. 3A to 3C are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention.
  • FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention
  • FIGS. 5A and 5B are a top plan view and a cross-sectional view illustrating a method for manufacturing a semiconductor device of the present invention, respectively;
  • FIGS. 6A to 6E are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention.
  • FIGS. 7A to 7D are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention.
  • FIGS. 8A to 8C are cross-sectional views illustrating a method for manufacturing a semiconductor device of the present invention.
  • FIGS. 9A to 9D are cross-sectional views each illustrating a periphery of a pixel portion of a semiconductor device of the present invention.
  • FIGS. 11A to 11C are diagrams each illustrating a semiconductor device of the present invention.
  • the present invention relates to a semiconductor device manufactured using four or three photomasks to reduce the number of steps in the conventional process using five photomasks and a manufacturing method thereof.
  • a photoresist is selectively exposed to light by rear surface exposure using a gate wiring material as a photomask to obtain a desired pattern so that an island region is formed. Further, a channel region, a source region, a drain region, a source wiring, and a drain wiring are formed by a halftone exposure technique. Although a halftone exposure technique is used in this embodiment mode, a gray tone exposure technique may be used. The combination of the features enables the process using four photomasks which is fewer than five photomasks used for the conventional process. Further, by using a halftone exposure technique, the process using three photomasks becomes possible.
  • a metal film is stacked over a glass substrate 100 by a sputtering method.
  • the glass substrate is allowable as long as it has a light transmitting property.
  • Barium borosilicate glass or aluminoborosilicate glass which is typified by the No. 7059 or No. 1737 glass manufactured by Corning Inc., may be used.
  • a light-transmitting substrate such as a quartz substrate or a plastic substrate may be used.
  • a first photomask is used to form a desired photoresist and then the metal film is etched, so that a gate electrode 101 and a gate wiring are formed.
  • an insulating film 102 is to form the gate insulating film 102 later and formed to have, for example, a single-layer structure of a silicon nitride film, a silicon oxide film, or a silicon oxynitride film or a layered structure of any of the above films. It is needless to say that the material of the gate insulating film is not limited to the above materials and may have a single-layer or layered structure using any other insulating film such as a tantalum oxide film.
  • the i-type amorphous silicon layer 103 and the n + -type amorphous silicon layer 104 are to form a channel region, a source region, and a drain region later.
  • the i-type amorphous silicon layer 103 is a non-doped layer which does not contain an impurity imparting conductivity.
  • the i-type amorphous silicon layer 103 may contain a very small amount of impurities.
  • the n + -type amorphous silicon layer 104 is a semiconductor film containing an impurity element imparting one conductivity type, in particular, an n-type semiconductor layer containing phosphorus at high concentration.
  • light transmits the i-type amorphous silicon layer 103 and the n + -type amorphous silicon layer 104 to expose the photoresist 121 .
  • the i-type amorphous silicon layer 103 and the n + -type amorphous silicon layer 104 are etched to form an i-type amorphous silicon island 123 and an n + -type amorphous silicon island 124 as shown in FIG. 1D .
  • a self-aligning step is performed and thus a step of aligning the photomask is not required, so that etching can be performed in a self-aligned manner while the photoresist pattern after exposure is not misaligned.
  • a metal film 105 is formed over an entire surface of the substrate.
  • the metal film 105 is to form a source electrode, a drain electrode, and a source wiring later.
  • the material of the metal film 105 is allowable as long as it is a metal material which can provide ohmic contact with the n + -type amorphous silicon island 124 , and an element selected from aluminum, chromium, tantalum, and titanium, an alloy containing any of the above elements as its component, an alloy film combining any of the above elements, and the like are given.
  • the photoresist 1 is subjected to ashing treatment to be processed such that the shape of the photoresist 1 is like that of a photoresist 2 of FIG. 2C . That is, the part of the photoresist, which has been formed thin, is exposed.
  • the photoresist 2 which has been processed by ashing is used to etch the metal film 105 so that the source electrode 110 and the drain electrode 111 are formed. Similarly, the photoresist 2 is used to etch the n + -type amorphous silicon island 124 and the i-type amorphous silicon island 123 so that a channel region 107 , a source region 108 , and a drain region 109 are formed.
  • the i-type amorphous silicon layer which overlaps with the gate electrode 101 with the gate insulating film 102 interposed therebetween forms a channel formation region 107 . After that, the photoresist 2 is removed by separation.
  • an insulating film is formed over an entire surface of the substrate to serve as a protective film 112 .
  • the insulating film serving as the protective film may be a silicon nitride film, a silicon oxide film, or a stack of the films.
  • the silicon nitride film is particularly preferred because of high passivation performance thereof.
  • ITO is formed over an entire surface of the substrate, a desired photoresist is formed using a fourth photomask, and a pixel electrode 113 is formed using the photoresist.
  • ITO is used as a pixel electrode material in this embodiment mode, tin oxide, indium oxide, nickel oxide, zinc oxide, or a compound of any of the above may be used as a transparent conductive material, for example.
  • FIG. 5A illustrates a top plan view of the TFT of this embodiment mode. Note that the same reference numerals are used for the parts corresponding to those in FIGS. 1A to 1E , FIGS. 2A to 2D , and FIGS. 3A to 3C .
  • FIG. 5B corresponds to a cross sectional view taken along line A-A′ in FIG. 5A .
  • the photoresist 4 is processed by ashing to form a photoresist 5 .
  • the photoresist 6 is processed by ashing to form a photoresist 7 .
  • FIG. 7C the photoresist 7 and portions of the transparent conductive film 312 formed on the photoresist 7 are removed together by a step of lifting off, so that a pixel electrode 313 and a wiring 320 are formed.
  • a protective film 314 is formed over an entire surface of the substrate by a CVD method.
  • An insulating film which serves as the protective film may be a silicon nitride film, a silicon oxide film, or a stack of them. A silicon nitride film is particularly preferred because of high passivation performance thereof.
  • the protective film 314 is etched using the photoresist 9 formed by slightly extending an end portion of the photoresist 8 outward and thus reducing the photoresist 8 in thickness, so that the pixel electrode 313 is partly exposed.
  • the exposed region forms a pixel region.
  • the end portion of the photoresist 8 is extended slightly outward. Therefore, the protective film 324 after etching is extended so that outer sides of the end portions of the source electrode and the drain electrode can be protected.
  • a TFT or an electrode in a lower layer can be more surely protected.
  • the contact hole 321 can be surely protected by the protective film 325 .
  • FIG. 8C is a view in the case where an LCD panel is manufactured using a TFT substrate in FIG. 8B .
  • a counter substrate 319 is provided to face the glass substrate 100 over which TFTs are formed.
  • the counter substrate 319 is provided with a color filter 318 .
  • a liquid crystal 315 and a spacer 316 are provided between the glass substrate 100 and the counter substrate 319 and are sealed with a sealant 317 .
  • inverted-staggered n-channel TFTs can be completed through the photolithography process using three photomasks. Then, they are arranged in matrix corresponding to pixels so that a pixel portion is formed, which can be a substrate for fabricating an active matrix electrooptic device.
  • a semiconductor device can be manufactured by the process using four or three photomasks, in which the number of photomasks is reduced and the number of steps is also reduced, as compared to the conventional process using five photomasks.
  • FIGS. 11A to 11C illustrate a television set, a portable information terminal (such as a mobile computer, a cellular phone, a mobile game console, or an electronic book), and a laptop computer, respectively, as examples of a semiconductor device and an electronic appliance of the present invention.
  • a portable information terminal such as a mobile computer, a cellular phone, a mobile game console, or an electronic book
  • a laptop computer respectively, as examples of a semiconductor device and an electronic appliance of the present invention.
  • FIG. 11A illustrates a display device including a housing 1001 , a display portion 1002 , speakers 1003 , a video input terminal 1004 , a supporting base 1005 , and the like.
  • the display device is manufactured using TFTs formed by the manufacturing method described in any of the aforementioned embodiment modes for the display portion 1002 and a driver circuit thereof.
  • the display device a liquid crystal display device, a light emitting device, and the like are given.
  • the display device includes all display devices for information display, such as those for computers, television broadcasting reception, and advertisement display. According to the present invention, an inexpensive and highly reliable display device can be realized.
  • a cellular phone illustrated in FIG. 11B includes control switches 2001 , a display portion 2002 , and the like. According to the present invention, an inexpensive and highly reliable cellular phone can be realized.
  • FIG. 11C illustrates a laptop personal computer including a main body 3001 , a display portion 3002 , and the like. According to the present invention, an inexpensive and highly reliable laptop personal computer can be realized.

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Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090101906A1 (en) * 2007-10-23 2009-04-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
US20090111198A1 (en) * 2007-10-23 2009-04-30 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20090142867A1 (en) * 2007-12-03 2009-06-04 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20090152559A1 (en) * 2007-12-03 2009-06-18 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of thin film transistor and manufacturing method of display device
US20090224249A1 (en) * 2008-03-05 2009-09-10 Semiconductor Energy Laboratory Co., Ltd. Method For Manufacturing EL Display Device
US20100047974A1 (en) * 2008-08-21 2010-02-25 Joo Soo Lim Method of manufacturing thin film transistor array substrate
US20100105162A1 (en) * 2008-10-24 2010-04-29 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20100102322A1 (en) * 2008-10-28 2010-04-29 Hitachi Displays, Ltd. Display device and method of manufacturing the same
US20100102315A1 (en) * 2008-10-24 2010-04-29 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20100105164A1 (en) * 2008-10-24 2010-04-29 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20100210078A1 (en) * 2009-02-13 2010-08-19 Semiconductor Energy Laboratory Co., Ltd. Manufacturing Method of Semiconductor Device
US20110031498A1 (en) * 2009-08-07 2011-02-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US20110165740A1 (en) * 2007-12-18 2011-07-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor Device and Method For Manufacturing Semiconductor Device
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US20130113044A1 (en) * 2009-10-09 2013-05-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8643018B2 (en) 2009-07-18 2014-02-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising a pixel portion and a driver circuit
US8741702B2 (en) 2008-10-24 2014-06-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8912040B2 (en) 2008-10-22 2014-12-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20160062198A1 (en) * 2014-08-29 2016-03-03 Century Technology (Shenzhen) Corporation Limited Display panel and manufacturing method thereof
US20170200745A1 (en) * 2016-01-11 2017-07-13 Boe Technology Group Co., Ltd. Thin film transistor, method for fabricating the same, array substrate, and display device
US10002949B2 (en) 2009-11-06 2018-06-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102148195B (zh) 2010-04-26 2013-05-01 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法

Citations (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4409134A (en) * 1980-03-03 1983-10-11 Shunpei Yamazaki Photoelectric conversion semiconductor and manufacturing method thereof
US5530265A (en) * 1993-08-12 1996-06-25 Semiconductor Energy Laboratory Co., Ltd. Insulated gate semiconductor device and process for fabricating the same
US5757444A (en) * 1992-04-28 1998-05-26 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same
US6008065A (en) * 1995-11-21 1999-12-28 Samsung Electronics Co., Ltd. Method for manufacturing a liquid crystal display
US6372560B1 (en) * 1999-04-01 2002-04-16 Hannstar Display Corp. Simplified process for forming thin film transistor matrix for liquid crystal display
US6485997B2 (en) * 1999-12-22 2002-11-26 Hyundai Display Technology, Inc. Method for manufacturing fringe field switching mode liquid crystal display device
US6493048B1 (en) * 1998-10-21 2002-12-10 Samsung Electronics Co., Ltd. Thin film transistor array panel for a liquid crystal display and a method for manufacturing the same
US6635581B2 (en) * 2001-06-08 2003-10-21 Au Optronics, Corp. Method for forming a thin-film transistor
US6797982B2 (en) * 2000-08-28 2004-09-28 Sharp Kabushiki Kaisha Active matrix substrate and display device
US20040263706A1 (en) * 2003-06-30 2004-12-30 Lg.Philips Lcd Co., Ltd. Array substrate for LCD device having double-layered metal structure and manufacturing method thereof
US20060024895A1 (en) * 2004-07-27 2006-02-02 Samsung Electronics Co., Ltd. Thin film transistor array panel and manufacturing method thereof
US7023021B2 (en) * 2000-02-22 2006-04-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
US20060275710A1 (en) * 2005-06-02 2006-12-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20060290867A1 (en) * 2005-06-27 2006-12-28 Ahn Byung C Liquid crystal display and fabricating method thereof
US20070001225A1 (en) * 2005-06-30 2007-01-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
US20070002249A1 (en) * 2005-06-30 2007-01-04 Yoo Soon S Liquid crystal display device and fabricating method thereof
US20070023790A1 (en) * 2005-07-29 2007-02-01 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US20070037070A1 (en) * 2005-08-12 2007-02-15 Semiconductor Energy Laboratory Co., Ltd. Light exposure mask and method for manufacturing semiconductor device using the same
US20070085475A1 (en) * 2005-10-17 2007-04-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US7223643B2 (en) * 2000-08-11 2007-05-29 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US20070126969A1 (en) * 2005-12-05 2007-06-07 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device
US20070139571A1 (en) * 2005-10-14 2007-06-21 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
US20070148936A1 (en) * 2005-12-28 2007-06-28 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US20070146592A1 (en) * 2005-12-28 2007-06-28 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
US20070146591A1 (en) * 2005-12-05 2007-06-28 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device
US20070222936A1 (en) * 2006-03-07 2007-09-27 Ming-Hung Shih Method for fabricating pixel array substrate
US7348198B2 (en) * 2004-12-04 2008-03-25 Lg.Philips Lcd Co., Ltd. Liquid crystal display device and fabricating method thereof
US7553712B2 (en) * 2006-02-22 2009-06-30 Au Optronics Corp. Method for manufacturing a bottom substrate of a liquid crystal display
US7824939B2 (en) * 2007-10-23 2010-11-02 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing display device comprising separated and electrically connected source wiring layers
US8148730B2 (en) * 2007-10-23 2012-04-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0311744A (ja) 1989-06-09 1991-01-21 Citizen Watch Co Ltd 薄膜トランジスタの製造方法
JP5408829B2 (ja) * 1999-12-28 2014-02-05 ゲットナー・ファンデーション・エルエルシー アクティブマトリックス基板の製造方法
CN1267780C (zh) * 2002-11-11 2006-08-02 Lg.飞利浦Lcd有限公司 用于液晶显示器的阵列基板及其制造方法
TWI262470B (en) * 2004-12-24 2006-09-21 Quanta Display Inc Method of fabricating a pixel structure of a thin film transistor liquid crystal display
KR101107682B1 (ko) * 2004-12-31 2012-01-25 엘지디스플레이 주식회사 표시 소자용 박막 트랜지스터 기판 및 그 제조 방법
US7588970B2 (en) 2005-06-10 2009-09-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP5105811B2 (ja) 2005-10-14 2012-12-26 株式会社半導体エネルギー研究所 表示装置
KR101201972B1 (ko) * 2006-06-30 2012-11-15 삼성디스플레이 주식회사 박막 트랜지스터 어레이 기판 및 이의 제조 방법
TWI328880B (en) * 2007-01-31 2010-08-11 Au Optronics Corp Method for fabricating a pixel structure of a liquid crystal display device
US8059236B2 (en) * 2007-02-15 2011-11-15 Au Optronics Corporation Method for producing reflective layers in LCD display

Patent Citations (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4409134A (en) * 1980-03-03 1983-10-11 Shunpei Yamazaki Photoelectric conversion semiconductor and manufacturing method thereof
US5757444A (en) * 1992-04-28 1998-05-26 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same
US7554616B1 (en) * 1992-04-28 2009-06-30 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and method of driving the same
US5530265A (en) * 1993-08-12 1996-06-25 Semiconductor Energy Laboratory Co., Ltd. Insulated gate semiconductor device and process for fabricating the same
US6008065A (en) * 1995-11-21 1999-12-28 Samsung Electronics Co., Ltd. Method for manufacturing a liquid crystal display
US6493048B1 (en) * 1998-10-21 2002-12-10 Samsung Electronics Co., Ltd. Thin film transistor array panel for a liquid crystal display and a method for manufacturing the same
US6372560B1 (en) * 1999-04-01 2002-04-16 Hannstar Display Corp. Simplified process for forming thin film transistor matrix for liquid crystal display
US6485997B2 (en) * 1999-12-22 2002-11-26 Hyundai Display Technology, Inc. Method for manufacturing fringe field switching mode liquid crystal display device
US7023021B2 (en) * 2000-02-22 2006-04-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of manufacturing the same
US7223643B2 (en) * 2000-08-11 2007-05-29 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US6797982B2 (en) * 2000-08-28 2004-09-28 Sharp Kabushiki Kaisha Active matrix substrate and display device
US7126157B2 (en) * 2000-08-28 2006-10-24 Sharp Kabushiki Kaisha Active matrix substrate, method of making the substrate, and display device
US8304297B2 (en) * 2000-08-28 2012-11-06 Sharp Kabushiki Kaisha Active matrix substrate, method of making the substrate, and display device
US7829391B2 (en) * 2000-08-28 2010-11-09 Sharp Kabushiki Kaisha Active matrix substrate, method of making the substrate, and display device
US7696516B2 (en) * 2000-08-28 2010-04-13 Sharp Kabushiki Kaisha Active matrix substrate, method of making the substrate, and display device
US7459723B2 (en) * 2000-08-28 2008-12-02 Sharp Kabushiki Kaisha Active matrix substrate, method of making the substrate, and display device
US6635581B2 (en) * 2001-06-08 2003-10-21 Au Optronics, Corp. Method for forming a thin-film transistor
US20040263706A1 (en) * 2003-06-30 2004-12-30 Lg.Philips Lcd Co., Ltd. Array substrate for LCD device having double-layered metal structure and manufacturing method thereof
US20060024895A1 (en) * 2004-07-27 2006-02-02 Samsung Electronics Co., Ltd. Thin film transistor array panel and manufacturing method thereof
US7348198B2 (en) * 2004-12-04 2008-03-25 Lg.Philips Lcd Co., Ltd. Liquid crystal display device and fabricating method thereof
US7671367B2 (en) * 2004-12-04 2010-03-02 Lg Display Co., Ltd. Liquid crystal display device and fabricating method thereof
US20060275710A1 (en) * 2005-06-02 2006-12-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20060290867A1 (en) * 2005-06-27 2006-12-28 Ahn Byung C Liquid crystal display and fabricating method thereof
US20070002249A1 (en) * 2005-06-30 2007-01-04 Yoo Soon S Liquid crystal display device and fabricating method thereof
US20070001225A1 (en) * 2005-06-30 2007-01-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method of the same
US20070023790A1 (en) * 2005-07-29 2007-02-01 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US20070037070A1 (en) * 2005-08-12 2007-02-15 Semiconductor Energy Laboratory Co., Ltd. Light exposure mask and method for manufacturing semiconductor device using the same
US20070139571A1 (en) * 2005-10-14 2007-06-21 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
US20070085475A1 (en) * 2005-10-17 2007-04-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20070146591A1 (en) * 2005-12-05 2007-06-28 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device
US20070126969A1 (en) * 2005-12-05 2007-06-07 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device
US20070146592A1 (en) * 2005-12-28 2007-06-28 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method thereof
US20070148936A1 (en) * 2005-12-28 2007-06-28 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US7553712B2 (en) * 2006-02-22 2009-06-30 Au Optronics Corp. Method for manufacturing a bottom substrate of a liquid crystal display
US20070222936A1 (en) * 2006-03-07 2007-09-27 Ming-Hung Shih Method for fabricating pixel array substrate
US7824939B2 (en) * 2007-10-23 2010-11-02 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing display device comprising separated and electrically connected source wiring layers
US8148730B2 (en) * 2007-10-23 2012-04-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device

Cited By (56)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090101906A1 (en) * 2007-10-23 2009-04-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
US20090111198A1 (en) * 2007-10-23 2009-04-30 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8148730B2 (en) 2007-10-23 2012-04-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
US8048697B2 (en) 2007-10-23 2011-11-01 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing an LCD device employing a reduced number of photomasks including bottom and top gate type devices
US20110065221A1 (en) * 2007-10-23 2011-03-17 Semiconductor Energy Laboratory Co., Ltd. Method for Manufacturing an LCD Device Employing a Reduced Number of Photomasks Including Bottom and Top Gate Type Devices
US9006050B2 (en) 2007-10-23 2015-04-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
US7842528B2 (en) 2007-10-23 2010-11-30 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing an LCD device employing a reduced number of photomasks
US7993991B2 (en) 2007-12-03 2011-08-09 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of thin film transistor and manufacturing method of display device
US8268654B2 (en) 2007-12-03 2012-09-18 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing LCD with reduced mask count
US8895333B2 (en) 2007-12-03 2014-11-25 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device with pixel electrode over gate electrode of thin film transistor
US20090142867A1 (en) * 2007-12-03 2009-06-04 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20090152559A1 (en) * 2007-12-03 2009-06-18 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of thin film transistor and manufacturing method of display device
US20110165740A1 (en) * 2007-12-18 2011-07-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor Device and Method For Manufacturing Semiconductor Device
US8951849B2 (en) * 2007-12-18 2015-02-10 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device including layer containing yttria-stabilized zirconia
US20090224249A1 (en) * 2008-03-05 2009-09-10 Semiconductor Energy Laboratory Co., Ltd. Method For Manufacturing EL Display Device
US8101442B2 (en) 2008-03-05 2012-01-24 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing EL display device
US20100047974A1 (en) * 2008-08-21 2010-02-25 Joo Soo Lim Method of manufacturing thin film transistor array substrate
US8008139B2 (en) * 2008-08-21 2011-08-30 Lg Display Co., Ltd. Method of manufacturing thin film transistor array substrate
US9691789B2 (en) 2008-10-22 2017-06-27 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US10211240B2 (en) 2008-10-22 2019-02-19 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8912040B2 (en) 2008-10-22 2014-12-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US9853069B2 (en) 2008-10-22 2017-12-26 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US9373525B2 (en) 2008-10-22 2016-06-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US9123751B2 (en) 2008-10-24 2015-09-01 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8980685B2 (en) 2008-10-24 2015-03-17 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing thin film transistor using multi-tone mask
US8242494B2 (en) 2008-10-24 2012-08-14 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing thin film transistor using multi-tone mask
US20100105162A1 (en) * 2008-10-24 2010-04-29 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8343799B2 (en) 2008-10-24 2013-01-01 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20100102315A1 (en) * 2008-10-24 2010-04-29 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20100105164A1 (en) * 2008-10-24 2010-04-29 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8236635B2 (en) 2008-10-24 2012-08-07 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8878178B2 (en) 2008-10-24 2014-11-04 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8686417B2 (en) 2008-10-24 2014-04-01 Semiconductor Energy Laboratory Co., Ltd. Oxide semiconductor device formed by using multi-tone mask
US8729546B2 (en) 2008-10-24 2014-05-20 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8741702B2 (en) 2008-10-24 2014-06-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8258024B2 (en) * 2008-10-28 2012-09-04 Hitachi Displays, Ltd. Display device and method of manufacturing the same
US20100102322A1 (en) * 2008-10-28 2010-04-29 Hitachi Displays, Ltd. Display device and method of manufacturing the same
US8143170B2 (en) 2009-02-13 2012-03-27 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
US20100210078A1 (en) * 2009-02-13 2010-08-19 Semiconductor Energy Laboratory Co., Ltd. Manufacturing Method of Semiconductor Device
US8643018B2 (en) 2009-07-18 2014-02-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising a pixel portion and a driver circuit
US8384085B2 (en) 2009-08-07 2013-02-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US8324626B2 (en) 2009-08-07 2012-12-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US9954005B2 (en) 2009-08-07 2018-04-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device comprising oxide semiconductor layer
US20110031498A1 (en) * 2009-08-07 2011-02-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US9171867B2 (en) 2009-08-07 2015-10-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8759132B2 (en) 2009-08-07 2014-06-24 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US20130113044A1 (en) * 2009-10-09 2013-05-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9865742B2 (en) * 2009-10-09 2018-01-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US10290742B2 (en) 2009-10-09 2019-05-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including oxide semiconductor layer
US10002949B2 (en) 2009-11-06 2018-06-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US20120049169A1 (en) * 2010-08-24 2012-03-01 Bong-Ju Kim Organic light-emitting display device and method of manufacturing the same
US8530268B2 (en) * 2010-08-24 2013-09-10 Samsung Display Co., Ltd. Organic light-emitting display device and method of manufacturing the same
US20160062198A1 (en) * 2014-08-29 2016-03-03 Century Technology (Shenzhen) Corporation Limited Display panel and manufacturing method thereof
US9904125B2 (en) * 2014-08-29 2018-02-27 Century Technology (Shenzhen) Corporation Limited Display panel and manufacturing method thereof
US20170200745A1 (en) * 2016-01-11 2017-07-13 Boe Technology Group Co., Ltd. Thin film transistor, method for fabricating the same, array substrate, and display device
US10355022B2 (en) * 2016-01-11 2019-07-16 Boe Technology Group Co., Ltd. Thin film transistor, method for fabricating the same, array substrate, and display device

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