US20090134453A1 - Non-Volatile Memory Device with Improved Immunity to Erase Saturation and Method for Manufacturing Same - Google Patents

Non-Volatile Memory Device with Improved Immunity to Erase Saturation and Method for Manufacturing Same Download PDF

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Publication number
US20090134453A1
US20090134453A1 US12/275,888 US27588808A US2009134453A1 US 20090134453 A1 US20090134453 A1 US 20090134453A1 US 27588808 A US27588808 A US 27588808A US 2009134453 A1 US2009134453 A1 US 2009134453A1
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Prior art keywords
dielectric
layer
control gate
volatile memory
memory device
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US12/275,888
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Bogdan Govoreanu
Hongyu Yu
Hag-Ju Cho
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Interuniversitair Microelektronica Centrum vzw IMEC
Samsung Electronics Co Ltd
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Interuniversitair Microelektronica Centrum vzw IMEC
Samsung Electronics Co Ltd
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Priority to US12/275,888 priority Critical patent/US20090134453A1/en
Assigned to INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW (IMEC), SAMSUNG ELECTRONICS CO. LTD. reassignment INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW (IMEC) ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHO, HAG-JU, GOVOREANU, BOGDAN, YU, HONGYU
Publication of US20090134453A1 publication Critical patent/US20090134453A1/en
Assigned to INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW (IMEC), SAMSUNG ELECTRONICS CO. LTD. reassignment INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW (IMEC) CORRECTIVE ASSIGNMENT TO CORRECT THE COUNTRY FOR ASSIGNEE SAMSUNG ELECTRONICS CO. LTD. PREVIOUSLY RECORDED ON REEL 021996 FRAME 0057. ASSIGNOR(S) HEREBY CONFIRMS THE COUNTRY FOR ASSIGNEE SAMSUNG ELECTRONICS CO. LTD. IS REPUBLIC OF KOREA. Assignors: CHO, HAG-JU, GOVOREANU, BOGDAN, YU, HONGYU
Assigned to IMEC reassignment IMEC CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW (IMEC)
Priority to US13/080,562 priority patent/US8119511B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane

Definitions

  • the present invention relates to a non-volatile memory device and a method for manufacturing a non-volatile memory device.
  • Erase saturation refers to the inability to erase a floating gate memory cell by removing charge from the floating gate to the Si channel through the tunnel oxide. This effect occurs because the parasitic current injected from the control gate towards the floating gate through the interpoly dielectric.
  • the same problem arises in charge trapping non-volatile memory cells in which charge is stored in a charge trapping gate and the upper dielectric is called the blocking dielectric.
  • a way to avoid erase saturation consists in using high-k dielectrics with high-workfunction metal gates.
  • metal gates are difficult to integrate in a conventional process flow.
  • they show a tendency to change the effective workfunction towards midgap, when deposited on some dielectric materials, likely consequence of the inherent thermal steps following their deposition.
  • Use of a p-type poly-silicon control gate as is a trend nowadays, may be compromised by this so-called Fermi level pinning (FLP) effect.
  • FLP Fermi level pinning
  • using a p-type poly-Si may require application of a higher erase voltage, in order to compensate for possible polysilicon depletion effect.
  • non-volatile memory device with improved immunity to erase saturation and a method for manufacturing such a non-volatile memory device.
  • a preferred embodiment provides a non-volatile memory device having a stacked structure comprising a substrate with a channel between two doped regions, a first dielectric on top of the channel, a charge storage medium on top of the first dielectric, a second dielectric on top of the charge storage medium and a control gate on top of the second dielectric.
  • the first dielectric is the so-called tunnel dielectric, which is provided for enabling tunnelling of electrons or holes towards or from the charge storage medium.
  • the charge storage medium can be a conductive floating gate or a charge trapping layer, i.e. a layer with discrete charge storage sites.
  • the second dielectric on top of the charge storage medium can be the interpoly dielectric (in the case of a floating gate) or the blocking dielectric (in the case of a charge trapping layer).
  • control gate or at least a bottom layer thereof which is in contact with the second dielectric, is constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k (i.e. k>k SiO2 ) materials after full device fabrication.
  • second dielectric or at least a top layer thereof which separates the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate.
  • the top layer is constructed in the second dielectric in an additional step before applying the control gate.
  • the second dielectric or an upper part thereof is constructed in a high-k material of the specified group and the mentioned reduction in work-function is counteracted by nitridation of this high-k material before applying the control gate.
  • This nitridation is preferably performed by means of a Decoupled Plasma Nitridation (DPN) step or an ammonia anneal step.
  • DPN Decoupled Plasma Nitridation
  • the result of the nitridation is that the material properties of the high-k material at least at the interface with the control gate are altered, in such a way that a reduction in the work-function of the material of the control gate at the interface no longer occurs or is at least partially suppressed.
  • the nitridation step has the effect that at least a top layer is created in the second dielectric which is in nitrided high-k material, i.e. no longer in the specified group of high-k materials.
  • the layer thickness of the high-k material and the nitridation step may also be chosen such that substantially the whole layer of high-k material is nitrided or even the whole of the second dielectric is made up of the nitrided high-k material.
  • An additional advantage of this nitridation step is that the trap density in the high-k layer can be decreased, which may improve the retention ability of the non-volatile memory device.
  • the second dielectric may also comprise a high-k layer, which may be in a high-k material of the specified group, with a capping layer on top, which is in a high-k material not belonging to the specified group.
  • the capping layer is preferably in AlN or AlON. This capping layer is a thin additional layer separating the control gate from the rest of the second dielectric to avoid the mentioned reduction in work-function.
  • high-k materials comprised in the specified group according to the invention are Al2O3, HfSiO, HfAlO and HfLaO.
  • the second dielectric may be or is even preferably partly constructed in one of these materials, with the exception of the top layer at the interface with the control gate.
  • the material of the control gate or at least its bottom layer is preferably chosen such that its work-function is above (i.e. higher than) the work-function of the material of the channel.
  • Suitable constructions are for example:
  • FIG. 1 shows a first embodiment of a non-volatile memory device.
  • FIG. 2 shows a second embodiment of a non-volatile memory device.
  • FIG. 3 shows a third embodiment of a non-volatile memory device.
  • FIG. 4 shows current-voltage characteristics illustrating the shift in work-function of an electrode material due to nitridation of an upper part of an high-k dielectric on which the electrode material is to be deposited of a non-volatile memory device of a second embodiment.
  • FIG. 5 shows the decrease in defect-assisted tunnelling by increasing the work-function of the gate electrode of a non-volatile memory device according to a first and a second embodiment.
  • FIGS. 1-3 show three exemplary embodiments of non-volatile memory cells 10 , 20 , 30 according to the invention, each comprising a substrate with a channel 1 in between two doped regions 11 (source and drain), a first dielectric 2 on top of the channel 1 , a silicon floating gate 3 on top of the insulating layer 2 , a second dielectric 4 , 41 , 42 - 43 on top of the silicon floating gate 3 and a control gate 5 on top of the second dielectric.
  • the first dielectric is the so-called tunnel dielectric and the second dielectric is the so-called interpoly dielectric.
  • Each of the layers 2 - 5 may in itself be a single layer or a stack of different layers having substantially the same functionality as the respective single layer which the stack replaces.
  • Contacts 12 are provided at the doped regions 11 , at the bottom of the substrate 1 and on top of the control gate 5 .
  • the embodiments may also be applied in charge trapping non-volatile memory cells in which charge is stored in a charge trapping gate, such as for example a nitride layer, and the upper dielectric 4 , 41 , 42 - 43 is called the blocking dielectric.
  • a charge trapping gate such as for example a nitride layer
  • the upper dielectric 4 , 41 , 42 - 43 is called the blocking dielectric.
  • an area of interest is the interface 6 between the second dielectric 4 , 41 , 42 - 43 and the control gate 5 .
  • a group of high-k materials is considered which are suitable for use in the dielectric in view of their high k-value, but which are to be avoided directly underneath this interface 6 , i.e. at the top of the second dielectric, in view of the fact that the control gate 5 is constructed in a material which has a predefined high work-function and shows a tendency to reduce its work-function when in contact with one of these considered high-k materials after full device fabrication. This tendency is also known in the art as Fermi level pinning in the case of a p-type semiconductor gate 5 .
  • parasitic current injected from the top gate 5 to the storage region 3 is reduced, hence allowing to erase deeper (i.e. remove more of the charge stored in the floating or charge trapping gate 3 ) and enlarge the Program/Erase window.
  • the reduction in the work-function is avoided by selecting a predetermined high-k material for the second dielectric 4 outside the considered group of high-k materials.
  • the whole of the second dielectric 4 is constructed in this predetermined high-k material.
  • the second dielectric is constructed in one of the high-k materials of the group, e.g. Al2O3, HfSiO or HfAlO, but the reduction in the work-function at the interface 6 is avoided by introducing a post-deposition nitridation step to alter the material properties of the high-k material (in such a way that in the end the material in fact no longer belongs to the specified group).
  • this embodiment has the advantage that the high-k materials of the considered group are not excluded from use in the second dielectric: they can be used as long as the top layer at the interface 6 is adequately nitrided.
  • a further advantage of the nitridation step is that the trap density in the high-k layer 4 can be reduced, presumably improving the retention ability of the non-volatile memory cell 20 .
  • the nitridation can be carried out by e.g. using a Decoupled Plasma Nitridation (DPN) or an ammonia anneal.
  • DPN Decoupled Plasma Nitridation
  • ammonia anneal an ammonia anneal.
  • a particular case where this method can be used is for interpoly or blocking dielectric stacks 41 containing Al2O3.
  • the Fermi level pinning is better stabilized towards the Si valence band edge.
  • the p-type-like character of a metal control gate 5 can be better maintained at the dielectric/gate interface.
  • the metal control gate 5 can be realized with a material such as TaN, TiN, TiCN, TaCN, etc . . . .
  • the method is even more effective when used in conjunction with HfAlOx-based interpoly or blocking dielectrics 41 or even other dielectric materials that show Fermi level pinning towards midgap or the Si conduction band edge (n-type-like). These materials may include, e.g. HfSiOx, HfO2, etc.
  • HfSiOx e.g. HfSiOx
  • HfO2 e.g.
  • the nitridation can prevent penetration of B from the poly gate, while for the case of a metal gate 5 it potentially also improves the thermal stability of the interpoly/gate stack.
  • the second dielectric comprises a high-k layer 42 , which may be in one of the materials of the group, topped by a thin dielectric capping layer 43 to avoid the reduction in work-function at the interface 6 .
  • the capping layer is in a high-k material such as for example AlN or AlON or other.
  • the capping layer is preferably in a range of up to 2 nm.
  • This capping layer can be used in conjunction with Al2O3-based interpoly/blocking dielectrics, HfAlOx-based dielectrics or other high-k dielectric materials that show a tendency to pin towards the Si conduction band edge (n-type), such as for example HfSiOx, HfO2, or other, and in conjunction with gates 5 as mentioned above with respect to the second embodiment.
  • n-type Si conduction band edge
  • an AlN material is a preferred material for the capping layer 43 since it has a dielectric constant of around 8 .
  • a high-k material such as HfAlOx- (or other high-k with similar dielectric constants)
  • EOT effective oxide thickness
  • the stack 42 - 43 can be redesigned so as to match the EOT specifications.
  • AlN is reported to have large band offsets to Si (as a reference level), e.g. more than 3 eV for the conduction band offset, which means that it has intrinsically good isolation properties.
  • addition of an AlN capping layer is able to control the Fermi level pinning, while its introduction is compatible with stringent retention requirements.
  • FIG. 4 shows measured Id-Vg curves on pMOS devices having a polysilicon electrode and their corresponding transconductance for:
  • FIG. 5 shows the effect of the invention on the energy band diagram from a floating gate 3 (n+-Si) over an interpoly dielectric 4 to a metal gate (MG) 5 during an erase operation.
  • ⁇ W is the reduction in work-function which would occur if the interpoly dielectric 4 would be constructed in one of the high-k materials of the considered group without the nitridation step or the introduction of the capping layer. It is clear that by avoiding this ⁇ W, tunnelling currents from the control gate to the floating gate are suppressed. If defects having a constant trap energy level Et, are present in the interpoly dielectric 4 , then the tunnel-to-trap distance, i.e.
  • the distance in which carriers must travel from the metal gate 5 into the interpoly dielectric 4 before reaching a charge trap at this energy level Et decreases with decreasing work-function of the metal gate 5 . If a higher work-function of the control gate 5 can be obtained or preserved, shallow charge traps, i.e. charge traps having an energy level Et near the conduction band of the dielectric 4 , are less accessible thereby reducing the current from the metal gate 5 through the dielectric 4 towards the floating or charge storage gate 3 .
  • top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. The terms so used are interchangeable under appropriate circumstances and the embodiments described herein can operate in other orientations than described or illustrated herein.

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EP07121292A EP2063459A1 (en) 2007-11-22 2007-11-22 Interpoly dielectric for a non-volatile memory device with a metal or p-type control gate
US99013007P 2007-11-26 2007-11-26
US12/275,888 US20090134453A1 (en) 2007-11-22 2008-11-21 Non-Volatile Memory Device with Improved Immunity to Erase Saturation and Method for Manufacturing Same

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US8119511B2 (en) 2007-11-22 2012-02-21 Imec Non-volatile memory device with improved immunity to erase saturation and method for manufacturing same
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