US20080288806A1 - Clock generation circuit and semiconductor memory apparatus having the same - Google Patents

Clock generation circuit and semiconductor memory apparatus having the same Download PDF

Info

Publication number
US20080288806A1
US20080288806A1 US11/878,904 US87890407A US2008288806A1 US 20080288806 A1 US20080288806 A1 US 20080288806A1 US 87890407 A US87890407 A US 87890407A US 2008288806 A1 US2008288806 A1 US 2008288806A1
Authority
US
United States
Prior art keywords
clock
selection signal
selection
semiconductor memory
memory apparatus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US11/878,904
Other versions
US7953998B2 (en
Inventor
Jong Ho Kang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Assigned to HYNIX SEMICONDUCTOR INC. reassignment HYNIX SEMICONDUCTOR INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KANG, JONG-HO
Publication of US20080288806A1 publication Critical patent/US20080288806A1/en
Application granted granted Critical
Publication of US7953998B2 publication Critical patent/US7953998B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used

Definitions

  • the present invention relates to a semiconductor memory apparatus, and in particular, to a clock generation circuit and a semiconductor memory apparatus having the same.
  • a semiconductor memory apparatus includes a data output unit 10 that outputs data Data in response to a clock clk, and a data input unit 20 that receives the data Data in response to the clock clk.
  • the clock clk is commonly input to the data output unit 10 and the data input unit 20 . Further, the clock clk is used by other circuits of the semiconductor memory apparatus. Accordingly, as the number of internal circuits of the semiconductor memory apparatus that use the clock clk becomes large, the clock clk may be distorted from the original waveform.
  • a high-speed semiconductor memory apparatus requires an increase in clock frequency. Accordingly, a semiconductor memory apparatus using a high-frequency clock is sensitive to the clock as compared with a semiconductor memory apparatus using a low-frequency clock. Therefore, the semiconductor memory apparatus using a high-frequency clock needs to use a stable clock free from distortion. For example, when the data output unit 10 and the data input unit 20 operate in response to a low-frequency clock, the clock used in the past can be used.
  • Embodiments of the present invention provide a clock generation circuit that outputs a clock or an internal clock.
  • Embodiments of the present invention provide a semiconductor memory apparatus that selectively uses one clock of a plurality of clocks according to a clock frequency or a user's intention.
  • a clock generation circuit of a semiconductor memory apparatus includes an internal clock generation unit that receives a clock and generates an internal clock, and a clock selection unit that selectively outputs the clock or the internal clock in response to a selection signal.
  • a semiconductor memory apparatus includes a clock generation unit that receives a clock and generates an internal clock, selectively outputs the clock or the internal clock as a first selection clock in response to a first selection signal, and selectively outputs the clock or the internal clock as a second selection clock in response to a second selection signal, a data output unit that outputs data in response to the first selection clock, and a data input unit that receives data in response to the second selection clock.
  • FIG. 1 is a block diagram of a semiconductor memory apparatus according to the related art
  • FIG. 2 is a block diagram of a semiconductor memory apparatus according to an embodiment of the present invention.
  • FIG. 3 is a circuit diagram showing a clock generation unit shown in FIG. 2 ;
  • FIG. 4 is a block diagram of a semiconductor memory apparatus according to another embodiment of the present invention.
  • an internal clock includes a PLL (Phase Locked Loop) clock or a DLL (Delay Locked Loop) clock.
  • PLL Phase Locked Loop
  • DLL Delay Locked Loop
  • a clock generation circuit and a semiconductor memory apparatus using the same will be described utilizing the PLL clock, but the invention is not limited thereto.
  • the internal clock may be the DLL clock.
  • a semiconductor memory apparatus includes a clock generation unit 100 , a data output unit 10 , and a data input unit 20 .
  • the clock generation unit 100 receives the clock clk to generate a PLL (Phase Locked Loop) clock.
  • the clock generation unit 100 selectively outputs the clock clk or the PLL clock as a first selection clock clk_sel 1 in response to a first selection signal.
  • the first selection signal may be a read selection signal read_sel.
  • the clock generation unit 100 selectively outputs the clock clk or the PLL clock as a second selection clock clk_sel 2 in response to a second selection signal.
  • the second selection signal may be a write selection signal write_sel.
  • the data output unit 10 outputs data Data in response to the first selection clock clk_sel 1 .
  • the data input unit 20 receives the data Data in response to the second selection clock clk_sel 2 .
  • FIG. 3 is a circuit diagram of a clock generation unit shown in FIG. 2 .
  • an internal clock generation unit 110 is referred to as a PLL circuit 110 .
  • the clock generation unit 100 includes a PLL (Phase Locked Loop) circuit 110 and a clock selection unit 120 .
  • PLL Phase Locked Loop
  • the PLL circuit 110 receives the clock clk to generate the PLL clock clk_pll.
  • the clock selection unit 120 outputs the clock clk or the PLL clock clk_pll as the first selection clock clk_sel 1 in response to the first selection signal, for example, the read selection signal read_sel, and outputs the clock clk or the PLL clock clk_pll as the second selection clock clk_sel 2 in response to the second selection signal, for example write selection signal write_sel.
  • the PLL circuit 110 may use a general PLL circuit. The PLL circuit 110 may be used to maintain a uniform frequency of an output signal. That is, the output signal is maintained to a specific phase.
  • the clock selection unit 120 includes a first multiplexer (MUX 1 ) 121 and a second multiplexer (MUX 2 ) 122 .
  • the first multiplexer (MUX 1 ) 121 outputs the clock clk or the PLL clock clk_pll as the first selection clock clk_sel 1 in response to the first selection signal, that is the read selection signal read_sel.
  • the first multiplexer (MUX 1 ) 121 provides the first selection clock clk_sel 1 to the data output unit 10 . Therefore, the first selection signal for selecting the first selection clock clk_sel 1 may be called the read selection signal that relates to a data outputting operation.
  • the second multiplexer (MUX 2 ) 122 outputs the clock clk or the PLL clock clk_pll as the second selection clock clk_sel 2 in response to the second selection signal, that is the write selection signal write_sel.
  • the second multiplexer (MUX 2 ) 122 provides the second selection clock clk_sel 2 to the data input unit 20 . Therefore, the second selection signal for selecting the second selection clock clk_sel 2 may be called the write selection signal that relates to a data inputting operation.
  • the PLL clock clk_pll can be selected as the clock clk that is input to the data output unit 10 and the data input unit 20 according to a clock frequency or a user's requirements.
  • the data output unit 10 and the data input unit 20 become sensitive to the clock clk. Accordingly, if the clock clk is distorted, the data output unit 10 and the data input unit 20 operate erroneously. In order to remove distortion of the clock clk, the clock clk is input to the PLL circuit 110 , thereby generating the PLL clock clk_pll. The PLL clock clk_pll is input to the data output unit 10 and the data input unit 20 , such that the data output unit 10 and the data input unit 20 operate stably.
  • the PLL circuit 110 is applied to generate the PLL clock clk_pll, and the generated PLL clock clk_pll is input to the data output unit 10 and the data input unit 20 .
  • the clock clk is input to the data output unit 10 and the data input unit 20 instead of the PLL clock clk_pll.
  • the semiconductor memory apparatus can selectively input the clock clk or the PLL clock clk_pll to the data output unit 10 and the data input unit 20 .
  • the semiconductor memory apparatus needs to selectively use the PLL clock clk_pll or the clock clk in order to operate according to the clock frequency or the user's requirements.
  • the read selection signal read_sel and the write selection signal write_sel are used to select the PLL clock clk_pll or the clock clk.
  • Enabling/disabling of the read selection signal read_sel and the write selection signal write_sel are set, for example, by inputting associated information to mode registers through an MRS (Mode Register Set) command.
  • the enabling/disabling of the read selection signal read_sel and the write selection signal write_sel may be set by disconnecting a fuse. If necessary, logic circuits that generate the read selection signal read_sel and the write selection signal write_sel, respectively, may be designed and used.
  • the semiconductor memory apparatus selectively uses the internal clock or the clock. As a result, stability of the semiconductor memory apparatus can be improved, and low current consumption can be achieved.
  • a buffer unit 130 that has a plurality of operational amplifiers 131 to 140 for data buffering may be provided between the clock generation unit 100 and data output unit 10 and between the clock generation unit 100 and the data input unit 20 .

Abstract

A clock generation circuit for a semiconductor memory apparatus includes an internal clock generation unit that receives a clock and generates an internal clock, and a clock selection unit that selectively outputs the clock or the internal clock in response to a selection signal.

Description

    CROSS-REFERENCE TO RELATED PATENT APPLICATION
  • This application claims the benefit of Korean Patent Application No. 10-2007-0046405, filed on May 14, 2007, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
    • BACKGROUND OF THE INVENTION
  • 1. Technical Field
  • The present invention relates to a semiconductor memory apparatus, and in particular, to a clock generation circuit and a semiconductor memory apparatus having the same.
  • 2. Related Art
  • As shown in FIG. 1, a semiconductor memory apparatus includes a data output unit 10 that outputs data Data in response to a clock clk, and a data input unit 20 that receives the data Data in response to the clock clk.
  • The clock clk is commonly input to the data output unit 10 and the data input unit 20. Further, the clock clk is used by other circuits of the semiconductor memory apparatus. Accordingly, as the number of internal circuits of the semiconductor memory apparatus that use the clock clk becomes large, the clock clk may be distorted from the original waveform.
  • Meanwhile a high-speed semiconductor memory apparatus requires an increase in clock frequency. Accordingly, a semiconductor memory apparatus using a high-frequency clock is sensitive to the clock as compared with a semiconductor memory apparatus using a low-frequency clock. Therefore, the semiconductor memory apparatus using a high-frequency clock needs to use a stable clock free from distortion. For example, when the data output unit 10 and the data input unit 20 operate in response to a low-frequency clock, the clock used in the past can be used.
  • However, when the semiconductor memory apparatus uses a high-frequency clock, since the data output unit 10 and the data input unit 20 are sensitive to the clock frequency, in order to prevent an erroneous operation, a stable clock that has no distortion compared with the previously used clock is required.
    • SUMMARY OF THE INVENTION
  • Embodiments of the present invention provide a clock generation circuit that outputs a clock or an internal clock.
  • Embodiments of the present invention provide a semiconductor memory apparatus that selectively uses one clock of a plurality of clocks according to a clock frequency or a user's intention.
  • According to an embodiment of the present invention, a clock generation circuit of a semiconductor memory apparatus includes an internal clock generation unit that receives a clock and generates an internal clock, and a clock selection unit that selectively outputs the clock or the internal clock in response to a selection signal.
  • According to another embodiment of the invention, a semiconductor memory apparatus includes a clock generation unit that receives a clock and generates an internal clock, selectively outputs the clock or the internal clock as a first selection clock in response to a first selection signal, and selectively outputs the clock or the internal clock as a second selection clock in response to a second selection signal, a data output unit that outputs data in response to the first selection clock, and a data input unit that receives data in response to the second selection clock.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a block diagram of a semiconductor memory apparatus according to the related art;
  • FIG. 2 is a block diagram of a semiconductor memory apparatus according to an embodiment of the present invention;
  • FIG. 3 is a circuit diagram showing a clock generation unit shown in FIG. 2; and
  • FIG. 4 is a block diagram of a semiconductor memory apparatus according to another embodiment of the present invention.
    •  DESCRIPTION OF EXEMPLARY EMBODIMENTS
  • Hereinafter, an embodiment of a semiconductor memory apparatus to which a clock generation circuit is applied will be described in detail with reference to the accompanying drawings. At this time, an internal clock includes a PLL (Phase Locked Loop) clock or a DLL (Delay Locked Loop) clock. Further, a clock generation circuit and a semiconductor memory apparatus using the same will be described utilizing the PLL clock, but the invention is not limited thereto. In addition, even though the internal clock as the PLL clock will be described, the internal clock may be the DLL clock.
  • Referring to FIG. 2, a semiconductor memory apparatus according to an embodiment of the present invention includes a clock generation unit 100, a data output unit 10, and a data input unit 20.
  • The clock generation unit 100 receives the clock clk to generate a PLL (Phase Locked Loop) clock. The clock generation unit 100 selectively outputs the clock clk or the PLL clock as a first selection clock clk_sel1 in response to a first selection signal. For example, the first selection signal may be a read selection signal read_sel.
  • Further and the clock generation unit 100 selectively outputs the clock clk or the PLL clock as a second selection clock clk_sel2 in response to a second selection signal. For example the second selection signal may be a write selection signal write_sel.
  • The data output unit 10 outputs data Data in response to the first selection clock clk_sel1.
  • The data input unit 20 receives the data Data in response to the second selection clock clk_sel2.
  • FIG. 3 is a circuit diagram of a clock generation unit shown in FIG. 2. Hereinafter, an internal clock generation unit 110 is referred to as a PLL circuit 110.
  • The clock generation unit 100 includes a PLL (Phase Locked Loop) circuit 110 and a clock selection unit 120.
  • The PLL circuit 110 receives the clock clk to generate the PLL clock clk_pll.
  • The clock selection unit 120 outputs the clock clk or the PLL clock clk_pll as the first selection clock clk_sel1 in response to the first selection signal, for example, the read selection signal read_sel, and outputs the clock clk or the PLL clock clk_pll as the second selection clock clk_sel2 in response to the second selection signal, for example write selection signal write_sel. The PLL circuit 110 may use a general PLL circuit. The PLL circuit 110 may be used to maintain a uniform frequency of an output signal. That is, the output signal is maintained to a specific phase.
  • The clock selection unit 120 includes a first multiplexer (MUX1) 121 and a second multiplexer (MUX2) 122.
  • The first multiplexer (MUX1) 121 outputs the clock clk or the PLL clock clk_pll as the first selection clock clk_sel1 in response to the first selection signal, that is the read selection signal read_sel. In this case, the first multiplexer (MUX1) 121 provides the first selection clock clk_sel1 to the data output unit 10. Therefore, the first selection signal for selecting the first selection clock clk_sel1 may be called the read selection signal that relates to a data outputting operation.
  • The second multiplexer (MUX2) 122 outputs the clock clk or the PLL clock clk_pll as the second selection clock clk_sel2 in response to the second selection signal, that is the write selection signal write_sel. In this case, the second multiplexer (MUX2) 122 provides the second selection clock clk_sel2 to the data input unit 20. Therefore, the second selection signal for selecting the second selection clock clk_sel2 may be called the write selection signal that relates to a data inputting operation.
  • The operation of the semiconductor memory apparatus having the above-described configuration will now be described. At this time, even though the semiconductor memory apparatus, to which the clock generation circuit according to an embodiment of the present invention is applied, is exemplified as a data input/output circuit that receives or outputs data, the invention is not limited thereto.
  • According to the semiconductor memory apparatus according to an embodiment of the present invention, the PLL clock clk_pll can be selected as the clock clk that is input to the data output unit 10 and the data input unit 20 according to a clock frequency or a user's requirements.
  • As the frequency of the clock clk that is input to the semiconductor memory apparatus becomes high, the data output unit 10 and the data input unit 20 become sensitive to the clock clk. Accordingly, if the clock clk is distorted, the data output unit 10 and the data input unit 20 operate erroneously. In order to remove distortion of the clock clk, the clock clk is input to the PLL circuit 110, thereby generating the PLL clock clk_pll. The PLL clock clk_pll is input to the data output unit 10 and the data input unit 20, such that the data output unit 10 and the data input unit 20 operate stably.
  • Further, when the user requires high operation reliability and stability of the semiconductor memory apparatus, the PLL circuit 110 is applied to generate the PLL clock clk_pll, and the generated PLL clock clk_pll is input to the data output unit 10 and the data input unit 20.
  • Meanwhile, when the user requires a semiconductor memory apparatus having low power consumption, instead of operation reliability and stability, the clock clk is input to the data output unit 10 and the data input unit 20 instead of the PLL clock clk_pll.
  • The semiconductor memory apparatus according to an embodiment of the present invention can selectively input the clock clk or the PLL clock clk_pll to the data output unit 10 and the data input unit 20.
  • As such, the semiconductor memory apparatus needs to selectively use the PLL clock clk_pll or the clock clk in order to operate according to the clock frequency or the user's requirements. The read selection signal read_sel and the write selection signal write_sel are used to select the PLL clock clk_pll or the clock clk. Enabling/disabling of the read selection signal read_sel and the write selection signal write_sel are set, for example, by inputting associated information to mode registers through an MRS (Mode Register Set) command. Alternatively, the enabling/disabling of the read selection signal read_sel and the write selection signal write_sel may be set by disconnecting a fuse. If necessary, logic circuits that generate the read selection signal read_sel and the write selection signal write_sel, respectively, may be designed and used.
  • The semiconductor memory apparatus according to an embodiment of the present invention selectively uses the internal clock or the clock. As a result, stability of the semiconductor memory apparatus can be improved, and low current consumption can be achieved.
  • In addition, as shown in FIG. 4, a buffer unit 130 that has a plurality of operational amplifiers 131 to 140 for data buffering may be provided between the clock generation unit 100 and data output unit 10 and between the clock generation unit 100 and the data input unit 20.
  • It will be apparent to those skilled in the art that various modifications and changes may be made without departing from the scope and spirit of the invention. Therefore, it should be understood that the above embodiment is not limitative, but illustrative in all aspects. The scope of the invention is defined by the appended claims rather than by the description preceding them, and therefore all changes and modifications that fall within metes and bounds of the claims, or equivalents of such metes and bounds are therefore intended to be embraced by the claims.

Claims (9)

1. A clock generation circuit for a semiconductor memory apparatus comprising:
an internal clock generation unit that receives a clock to generate an internal clock; and
a clock selection unit that selectively outputs the clock or the internal clock in response to a selection signal.
2. The clock generation circuit of claim 1,
wherein the clock selection unit includes a multiplexer.
3. A semiconductor memory apparatus comprising:
a clock generation unit that receives a clock to generate an internal clock, selectively outputs the clock or the internal clock as a first selection clock in response to a first selection signal, and selectively outputs the clock or the internal clock as a second selection clock in response to a second selection signal;
a data output unit that outputs data in response to the first selection clock; and
a data input unit that receives data in response to the second selection clock.
4. The clock generation unit of claim 3,
wherein the first selection signal is a read selection signal and the second selection signal is a write selection signal, the read selection signal and the write selection signal include low level and high level, respectively.
5. The semiconductor memory apparatus of claim 4,
wherein the clock generation unit includes:
a internal clock generation unit that receives the clock to generates the internal clock, and
a clock selector that selectively outputs the clock or the internal clock as the first selection clock in response to the read selection signal, and selectively outputs the clock or the internal clock as the second selection clock in response to the write selection signal.
6. The semiconductor memory apparatus of claim 5,
wherein the clock selector includes:
a first multiplexer that selectively outputs the clock or the internal clock as the first selection clock in response to the read selection signal, and
a second multiplexer that selectively outputs the clock or the internal clock as the second selection clock in response to the write selection signal.
7. The semiconductor memory apparatus of claim 5,
wherein the internal clock generation unit includes a PLL (Phase Locked Loop) circuit.
8. The semiconductor memory apparatus of claim 3, further comprising:
a buffer unit disposed between the clock generation unit and the data input unit, and between the clock generation unit and the data output unit.
9. The semiconductor memory apparatus of claim 8,
wherein the buffer unit includes a plurality of operational amplifiers connected in series.
US11/878,904 2007-05-14 2007-07-27 Clock generation circuit and semiconductor memory apparatus having the same Active 2030-02-14 US7953998B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2007-0046405 2007-05-14
KR1020070046405A KR20080100562A (en) 2007-05-14 2007-05-14 Clock generating circuit and semiconductor memory apparatus using the same

Publications (2)

Publication Number Publication Date
US20080288806A1 true US20080288806A1 (en) 2008-11-20
US7953998B2 US7953998B2 (en) 2011-05-31

Family

ID=40028744

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/878,904 Active 2030-02-14 US7953998B2 (en) 2007-05-14 2007-07-27 Clock generation circuit and semiconductor memory apparatus having the same

Country Status (2)

Country Link
US (1) US7953998B2 (en)
KR (1) KR20080100562A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11049536B2 (en) * 2019-07-22 2021-06-29 Shanghai Zhaoxin Semiconductor Co., Ltd. Memory device having hardware regulation training

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8611178B2 (en) * 2011-11-11 2013-12-17 Qualcomm Incorporated Device and method to perform memory operations at a clock domain crossing
KR102272259B1 (en) 2015-07-01 2021-07-06 삼성전자주식회사 Semiconductor memory device having clock generation scheme based on command interworking

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5142247A (en) * 1991-08-06 1992-08-25 Compaq Computer Corporation Multiple frequency phase-locked loop clock generator with stable transitions between frequencies
US6029250A (en) * 1998-09-09 2000-02-22 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same
US20020000853A1 (en) * 1999-10-29 2002-01-03 Shin Chung Chen Delay locked loop for timing recovery and write precompensation for a read channel of a mass data storage device, or the like
US20020104031A1 (en) * 2000-12-06 2002-08-01 Tomlinson Jock F. Programmable power management system and method
US6510095B1 (en) * 2001-09-28 2003-01-21 Fujitsu Limited Semiconductor memory device for operating in synchronization with edge of clock signal
US6654898B1 (en) * 1999-07-15 2003-11-25 Apple Computer, Inc. Stable clock generation internal to a functional integrated circuit chip
US6687322B1 (en) * 2000-10-06 2004-02-03 Adaptec, Inc. Dual mode clock alignment and distribution device
US6912680B1 (en) * 1997-02-11 2005-06-28 Micron Technology, Inc. Memory system with dynamic timing correction
US20060066759A1 (en) * 2004-09-29 2006-03-30 Matsushita Electric Industrial Co., Ltd. Automatic frequency tuning system
US20060145741A1 (en) * 2004-12-30 2006-07-06 Stmicroelectronics Pvt. Ltd. Digital delay lock loop
US20070147106A1 (en) * 2002-08-17 2007-06-28 Kye-Hyun Kyung Devices and methods for controlling active termination resistors in a memory system

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04107011A (en) 1990-08-28 1992-04-08 Fujitsu Denso Ltd Pll circuit
JPH11312400A (en) 1998-02-24 1999-11-09 Matsushita Electric Ind Co Ltd Semiconductor integrated circuit
JP4107011B2 (en) 2002-08-27 2008-06-25 松下電工株式会社 Door unit

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5142247A (en) * 1991-08-06 1992-08-25 Compaq Computer Corporation Multiple frequency phase-locked loop clock generator with stable transitions between frequencies
US6912680B1 (en) * 1997-02-11 2005-06-28 Micron Technology, Inc. Memory system with dynamic timing correction
US6029250A (en) * 1998-09-09 2000-02-22 Micron Technology, Inc. Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same
US6654898B1 (en) * 1999-07-15 2003-11-25 Apple Computer, Inc. Stable clock generation internal to a functional integrated circuit chip
US20020000853A1 (en) * 1999-10-29 2002-01-03 Shin Chung Chen Delay locked loop for timing recovery and write precompensation for a read channel of a mass data storage device, or the like
US6687322B1 (en) * 2000-10-06 2004-02-03 Adaptec, Inc. Dual mode clock alignment and distribution device
US20020104031A1 (en) * 2000-12-06 2002-08-01 Tomlinson Jock F. Programmable power management system and method
US6510095B1 (en) * 2001-09-28 2003-01-21 Fujitsu Limited Semiconductor memory device for operating in synchronization with edge of clock signal
US20070147106A1 (en) * 2002-08-17 2007-06-28 Kye-Hyun Kyung Devices and methods for controlling active termination resistors in a memory system
US20060066759A1 (en) * 2004-09-29 2006-03-30 Matsushita Electric Industrial Co., Ltd. Automatic frequency tuning system
US20060145741A1 (en) * 2004-12-30 2006-07-06 Stmicroelectronics Pvt. Ltd. Digital delay lock loop

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11049536B2 (en) * 2019-07-22 2021-06-29 Shanghai Zhaoxin Semiconductor Co., Ltd. Memory device having hardware regulation training

Also Published As

Publication number Publication date
US7953998B2 (en) 2011-05-31
KR20080100562A (en) 2008-11-19

Similar Documents

Publication Publication Date Title
JP5044849B2 (en) Delay line synchronization apparatus and method
KR101579837B1 (en) Apparatus and method for generating random number
US8013637B2 (en) Clock signal selection circuit
JP2001005554A (en) Semiconductor device and timing control circuit
JP2007166623A (en) Delay cell and delay line circuits having same
US8139429B2 (en) Output enable signal generating circuit and method of semiconductor memory apparatus
US7652939B2 (en) Semiconductor memory device and method for driving the same
US7953998B2 (en) Clock generation circuit and semiconductor memory apparatus having the same
US8294499B2 (en) Clock signal generation circuit for reducuing current consumption, and semiconductor device having the same
JP2007086960A (en) Clock switching circuit
JP3593104B2 (en) Clock switching circuit
US7178048B2 (en) System and method for signal synchronization based on plural clock signals
US10705558B2 (en) Apparatuses and methods for avoiding glitches when switching clock sources
US7653758B2 (en) Memory system with memory controller and board comprising a digital buffer wherein input/output data and clock signals are applied in parallel
US6754112B2 (en) Integrated circuit devices having delay circuits for controlling setup/delay times of data signals that are provided to memory devices
KR100925030B1 (en) Singnal Selecting Circuit and Semiconductor Memory Device including thereof
KR101086874B1 (en) Semiconductor integrated circuit
US7119593B2 (en) Delayed signal generation circuits and methods
US7185216B1 (en) System for synchronizing first and second sections of data to opposing polarity edges of a clock
KR101004686B1 (en) Semiconductor memory device and operation method thereof
CN110349606B (en) Semiconductor memory device and method of operating the same
US7508271B2 (en) Semiconductor memory apparatus having phase locked loop
KR100609135B1 (en) Setup/hold time control circuit
KR20090045584A (en) Semiconductor memory device

Legal Events

Date Code Title Description
AS Assignment

Owner name: HYNIX SEMICONDUCTOR INC., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:KANG, JONG-HO;REEL/FRAME:019680/0980

Effective date: 20070625

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12