US20080230264A1 - Interconnection structure and method thereof - Google Patents
Interconnection structure and method thereof Download PDFInfo
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- US20080230264A1 US20080230264A1 US12/045,362 US4536208A US2008230264A1 US 20080230264 A1 US20080230264 A1 US 20080230264A1 US 4536208 A US4536208 A US 4536208A US 2008230264 A1 US2008230264 A1 US 2008230264A1
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- circuit
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- interconnection structure
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
- H05K3/4658—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern characterized by laminating a prefabricated metal foil pattern, e.g. by transfer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0376—Etching temporary metallic carrier substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/063—Lamination of preperforated insulating layer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/16—Inspection; Monitoring; Aligning
- H05K2203/166—Alignment or registration; Control of registration
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4679—Aligning added circuit layers or via connections relative to previous circuit layers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49151—Assembling terminal to base by deforming or shaping
- Y10T29/49153—Assembling terminal to base by deforming or shaping with shaping or forcing terminal into base aperture
Definitions
- the present invention relates to an interconnection structure and more particularly, to an interconnection structure formed by pressing.
- FIG. 1 illustrates a schematic view of a traditional printed circuit board 10 with multiple layers.
- the printed circuit board 10 includes circuit layers 11 , 12 , and 13 and insulating layers 14 and 15 interposing there between.
- a through hole 16 penetrating the corresponding layers is formed; and then a conductive layer 17 is plated on the sidewall 18 of the through hole 16 thereby creating electrical interconnections between the different circuit layers as shown in FIG. 1 .
- the effectiveness of the electrical interconnections depends upon the plating performance, which relates to the aspect ratio of the through hole 16 .
- the aspect ratio is defined as a ratio of the depth D to the diameter R, wherein the depth D is the depth of the through hole 16 in the direction along the thickness of the printed circuit board 10 and the diameter R is referred to the cross section of the through hole 16 .
- the aspect ratio of the though hole increases, the plating performance is reduced, since flowing plating chemicals into the through hole 16 becomes more difficult. This may result in a non-uniform plated layer, for example, like the conductive layer 17 on the sidewall 18 as shown in FIG. 1 .
- the non-uniform conductive layer 17 acts adversely on electrical interconnections. That is, the conventional plating technology is not suitable for high-density printed circuit boards with high aspect ratios. Therefore, it is desired to provide inventive methods and structures to address the issues caused by the conventional methods.
- One aspect of the present invention is to provide an interconnection structure having conductive bumps.
- the interconnection structure is fabricated by forming the conductive bumps on one of the circuit layers; and then forcing the conductive bumps to penetrate an insulating layer and connect another circuit layer by pressing the circuit layers to the insulating layer.
- the present invention also provides another method comprising forming circuit layers on temporary substrates; embedding the circuit layers into an insulating layer by pressing the temporary substrates to the insulating layer; and then removing the temporary substrates to obtain a printed circuit board having a thickness as thin as the insulating layer.
- the present invention provides an interconnection structure for a printed circuit board.
- the interconnection structure includes an insulating substrate; a first circuit exposed on a first surface of the insulating substrate; a second circuit exposed on a second surface of the insulating substrate: and a first conductive bump connecting the first circuit and the second circuit, wherein the first circuit, the second circuit and the first conductive bump are embedded in the insulating substrate.
- the present invention provides a method for manufacturing an interconnection structure.
- the method includes the steps of providing a first conductive substrate, a second conductive substrate, and an insulating substrate; respectively forming a first circuit and a second circuit on the first conductive substrate and the second conductive substrate; forming a conductive bump on the second circuit; and connecting the insulating substrate with the first circuit and the second circuit by pressing the first conductive substrate, the insulating substrate and the second conductive substrate, wherein the conductive bump penetrates the insulating substrate to contact the first circuit.
- FIG. 1 illustrates a schematic view of a conventional interconnection structure for a printed circuit board
- FIG. 2A to FIG. 2C illustrate schematic views of a method for manufacturing a first circuit in accordance with a first embodiment of the present invention
- FIG. 3A to FIG. 3C illustrate schematic views of a method for manufacturing a second circuit in accordance with the first embodiment of the present invention
- FIG. 3D to FIG. 3G illustrate schematic views of a method for manufacturing a first conductive bump on the second circuit in accordance with the first embodiment of the present invention
- FIG. 4A to FIG. 4C illustrate schematic views of a method for manufacturing a printed circuit board with two circuit levels in accordance with the first embodiment of the present invention
- FIG. 5A to FIG. 5B illustrate schematic views of a method for manufacturing a second conductive bump in accordance with a second embodiment of the present invention.
- FIG. 6A to FIG. 6B illustrate schematic views of a method for manufacturing a printed circuit board with four circuit levels in accordance with the second embodiment of the present invention.
- FIG. 2A to FIG. 2C , FIG. 3A to FIG. 3G and FIGS. 4A to 4C schematically illustrate the first embodiment of the present invention, wherein FIG. 2A to FIG. 2C are directed to a first circuit 25 formed on a first conductive substrate 20 .
- a first conductive substrate 20 is provided.
- the first conductive substrate includes an alignment hole 21 to be used later.
- An un-patterned photoresist layer 23 and a first patterned photoresist layer 24 are respectively formed on the surface 20 a and the surface 20 b of the first conductive substrate 20 .
- the first conductive substrate 20 can be a copper foil, or be made of any other suitable conductive materials.
- the thickness of the first conductive substrate 20 can vary, for example, about 0.1 mm in this embodiment.
- the photoresist layers 23 and 24 can be conventional dry films for preparing ordinary printed circuit boards. The thicknesses of the photoresist layers 23 and 24 are not limited, which can be, for example, around 25 ⁇ m and 40 ⁇ m.
- plating is used for circuit formations in all embodiments of the present invention. It should be understood that the circuit formations also can be performed by any other suitable methods, for example, by printing the Ag gel or Cu gel on the related substrate, which are also included in the present invention.
- a first circuit 25 is formed on the first conductive substrate 20 by plating a conductive material in the openings of the first patterned photoresist layer 24 .
- the first circuit 25 can include an anti-etch layer 25 N and a conductive layer 25 C.
- the anti-etch layer 25 N can be a Ni layer with a thickness between 25 ⁇ m and 50 ⁇ m
- the conductive layer 25 C can be a Cu layer with a thickness between 50 ⁇ m and 100 ⁇ m.
- the line width of the first circuit 25 is preferably between 15 ⁇ m and 100 ⁇ m. In the first embodiment, the line width of the first circuit 25 is 30 ⁇ m. Note that the photoresist layers 23 and 24 are removed after forming the first circuit 25 , as shown in FIG. 2C . The structure of FIG. 2C is to be used in subsequent steps.
- FIG. 3A to FIG. 3C are directed to a second circuit 30 formed on a second conductive substrate 30 .
- a second conductive substrate 30 is provided.
- the second conductive substrate includes an alignment hole 31 corresponding to the alignment hole 21 , which is to be used later.
- a second patterned photoresist layer 33 and an un-patterned photoresist layer 34 are respectively formed on the surface 30 a and the surface 30 b of the second conductive substrate 30 .
- a second circuit 35 is formed on the second conductive substrate 30 by plating a conductive material in the openings of the second patterned photoresist layer 33 .
- the line width of the second circuit 35 is between 15 ⁇ m and 100 ⁇ m.
- the line width of the second circuit 35 is 30 ⁇ m. Materials and thicknesses of the related layers for fabricating the second circuit 35 are similar to those for the first circuit 35 as aforementioned. Note that the photoresist layers 33 and 34 are removed after forming the second circuit 35 , as shown in FIG. 3C .
- FIG. 3D to FIG. 3G illustrate a method for forming a first conductive bump 38 on the second circuit 35 .
- a third patterned photoresist layer 36 and an un-patterned photoresist layer 37 are respectively formed on the surface 30 a and the surface 30 b of the second conductive substrate 30 .
- a portion of the second circuit 35 is covered by the third patterned photoresist layer 36 while another portion of the second circuit 35 , which is reserved for forming a first conductive bump 38 thereon, is exposed.
- Materials of the photoresist layers 36 and 37 can be similar to the photoresist layers 33 and 34 .
- the thickness of the third patterned photoresist layer 36 is critical depending upon the thickness of the first conductive bump 38 to be formed later.
- the third patterned photoresist layer 36 is preferably thicker than that of the photoresist layer 33 or 34 .
- the preferred thickness of the third patterned photoresist layer 36 is between 45 ⁇ m and 70 ⁇ m.
- the first conductive bump 38 are formed on the second circuit 35 by plating conductive materials in the openings of the third patterned photoresist layer 36 .
- a diameter 38 d is defined with reference to the cross section of the conductive bump 38 along the line width 35 w of the first circuit 35 .
- the diameter 38 d is preferably less than the width 35 w of the first circuit 35 .
- the conductive bumps 38 can be made of copper or any suitable conductive materials.
- the thickness of the conductive bump 38 depends upon an insulating substrate 40 to be used. In the first embodiment, the preferred thickness of the conductive bump 38 is between 45 ⁇ m and 70 ⁇ m.
- FIG. 3F illustrates an optional step, which demonstrates planarizing the surface of the first conductive bumps 38 by polishing, which may also adjust the thickness of the conductive bump 38 to a desired value.
- FIG. 3G illustrates the step of removing the photoresist layers 36 and 37 . The resultant structure of FIG. 3G is to be used in subsequent steps.
- FIG. 4A to FIG. 4C illustrate a method for connecting the first circuit 25 , the second circuit 35 , and the insulating substrate 40 , wherein the conductive bumps 38 penetrate the insulating substrate 40 to contact the first circuit 25 .
- the insulating substrate 40 is disposed between the first conductive substrate 20 of FIG. 2C and the second conductive substrate 30 of FIG. 3G , and opposite sides of the first circuit 25 , the second circuit 35 or the conductive bumps 38 are set to face the insulating substrate 40 .
- the insulating substrate 40 is formed with an alignment hole 40 corresponding to the alignment holes 21 and 31 , as indicated by a dotted line.
- the insulating substrate 40 can be a sheet made of polymers, such as epoxy resins or polyimide resins, with a thickness between 45 ⁇ m and 70 ⁇ m.
- the insulating substrate 40 may contain reinforced materials, for example, glass fibers. Note that, as shown in FIG.
- the insulating substrate 40 is further formed with openings 42 corresponding to the first conductive bumps 38 .
- the openings 42 provide spaces for the first conductive bumps 38 to penetrate the insulating substrate 40 .
- Conventional laser drilling techniques can perform the step of forming the openings 42 .
- FIG. 4B illustrates the step of pressing the first conductive substrate 20 , the insulating substrate 40 and the second conductive substrate 30 .
- the insulating substrate 40 is heated to soften polymers contained therein before pressing.
- the temperature for softening depends upon the glass transition temperature of the polymers.
- the pressure for pressing is set at around 20 Kg/cm 2 to 40 Kg/cm 2 . Note that during the pressing operation, some fluids of the polymers may flow out of the edge of the substrates.
- the insulating substrate 40 connects the first circuit 25 and the second circuit 35 as adhesions generated from the softened polymers.
- the softened polymers are fluid and movable, the first circuit 25 and the second circuit 35 are embedded in the insulating substrate 40 .
- the conductive bumps 38 are in contact with the first circuit 25 by penetrating the insulating substrate 40 through the openings 42 . Note that the step of forming the openings 42 prior to the pressing can be omitted if the heated insulating substrate 40 , regardless of containing reinforced materials or not, is adapted to be penetrated directly by the conductive bumps.
- FIG. 4C illustrate the step of removing the first conductive substrate 20 and the second conductive substrate 30 after the pressing step of FIG. 4B .
- the removing step is preferably preformed by etching.
- the anti-etch layers 25 N and 35 N can be optionally stripped by appropriate wet chemicals.
- FIG. 4C shows the resultant printed circuit board with two circuit layers 25 and 35 according to the first embodiment, wherein the thickness of the printed circuit board is substantially as thin as the single insulating substrate 40 .
- FIG. 5A to FIG. 5B illustrate a method for manufacturing second conductive bumps 56 and 57 in accordance with the second embodiment of the present invention.
- the first conductive substrate 20 and the second conductive substrate 30 in the second embodiment are removed partially rather than completely. A portion of the first conductive substrate 20 and the second conductive substrate 30 remain for creating the second conductive bumps 56 and 57 .
- fourth patterned photoresist layers 51 and 52 are formed on the first conductive substrate 20 and the second conductive substrate 30 of the structure of FIG. 4B . Then, using the fourth patterned photoresist layers 51 and 52 as masks, anti-etch layers 53 N and 54 N are plated on the first conductive substrate 20 and the second conductive substrate 30 .
- Materials for the photoresist layers 51 and 52 are similar to the photoresist layers 23 and 24 as aforementioned.
- the anti-etch layer 53 N and 54 N can be Ni layers or any other suitable materials with a preferred thickness between 5 ⁇ m and 25 ⁇ m.
- the fourth patterned photoresist layers 51 and 52 are first removed. Then, using the anti-etch layers 53 N and 54 N as masks, the second conductive bumps 56 and 57 are created by etching the first conductive substrate 20 and the second conductive substrate 30 . Next, the anti-etch layers 53 N and 54 N and the remaining anti-etch layers are stripped using appropriated wet chemicals. The resultant structure after stripping is shown in FIG. 6A .
- FIG. 6A illustrates a third conductive substrate 70 with the third circuit 71 ; one insulating substrate 60 ; the insulating substrate 40 with the second conductive bumps 56 and 57 ; another insulating substrate 60 ; and a fourth conductive substrate 80 with the fourth circuit 81 , which are arranged in sequence for pressing. Details for manufacturing the third conductive substrate 70 and the fourth conductive substrate 80 are set forth above in connection with the descriptions of FIG. 2A to FIG. 2C . Details for pressing techniques are set forth above in connection with the descriptions of FIG. 4A and FIG. 4B .
- FIG. 6B illustrates the resultant structure after pressing the substrates as shown in FIG. 6A ; followed by removing the third conductive substrate 70 and the fourth conductive substrate 80 ; and stripping off the anti-etch layers 71 N and 81 N.
- the third circuit 71 and the fourth circuit 81 are embedded in the insulating substrates 60 . That is, FIG. 6B shows the resultant printed circuit board with four circuit layers according to the second embodiment, wherein the thickness of the printed circuit board is substantially as thin as the combination of the insulating substrates 60 , 40 and 60 .
Abstract
The present invention discloses an interconnection structure which is formed by a method comprising providing a first conductive substrate, a second conductive substrate, and an insulating substrate; respectively forming a first circuit and a second circuit on the first conductive substrate and the second conductive substrate; forming a conductive bump on the second circuit; and connecting the insulating substrate with the first circuit and the second circuit by pressing the first conductive substrate, the insulating substrate and the second conductive substrate, wherein the conductive bump penetrates the insulating substrate to contact the first circuit.
Description
- This application claims the right of priority based on Taiwan Patent Application No. 096109328 entitled “INTERCONNECTION STRUCTURE AND METHOD THEREOF,” filed on Mar. 19, 2007, which is incorporated herein by reference and assigned to the assignee herein.
- The present invention relates to an interconnection structure and more particularly, to an interconnection structure formed by pressing.
- Printed circuit boards are mechanisms with circuit patterns for connecting various electronic components.
FIG. 1 illustrates a schematic view of a traditional printedcircuit board 10 with multiple layers. The printedcircuit board 10 includescircuit layers insulating layers different circuit layers through hole 16 penetrating the corresponding layers is formed; and then aconductive layer 17 is plated on thesidewall 18 of the throughhole 16 thereby creating electrical interconnections between the different circuit layers as shown inFIG. 1 . - Generally, the effectiveness of the electrical interconnections depends upon the plating performance, which relates to the aspect ratio of the
through hole 16. As shown inFIG. 1 , the aspect ratio is defined as a ratio of the depth D to the diameter R, wherein the depth D is the depth of the throughhole 16 in the direction along the thickness of the printedcircuit board 10 and the diameter R is referred to the cross section of the throughhole 16. When the aspect ratio of the though hole increases, the plating performance is reduced, since flowing plating chemicals into the throughhole 16 becomes more difficult. This may result in a non-uniform plated layer, for example, like theconductive layer 17 on thesidewall 18 as shown inFIG. 1 . The non-uniformconductive layer 17 acts adversely on electrical interconnections. That is, the conventional plating technology is not suitable for high-density printed circuit boards with high aspect ratios. Therefore, it is desired to provide inventive methods and structures to address the issues caused by the conventional methods. - One aspect of the present invention is to provide an interconnection structure having conductive bumps. The interconnection structure is fabricated by forming the conductive bumps on one of the circuit layers; and then forcing the conductive bumps to penetrate an insulating layer and connect another circuit layer by pressing the circuit layers to the insulating layer. The present invention also provides another method comprising forming circuit layers on temporary substrates; embedding the circuit layers into an insulating layer by pressing the temporary substrates to the insulating layer; and then removing the temporary substrates to obtain a printed circuit board having a thickness as thin as the insulating layer.
- In one embodiment, the present invention provides an interconnection structure for a printed circuit board. The interconnection structure includes an insulating substrate; a first circuit exposed on a first surface of the insulating substrate; a second circuit exposed on a second surface of the insulating substrate: and a first conductive bump connecting the first circuit and the second circuit, wherein the first circuit, the second circuit and the first conductive bump are embedded in the insulating substrate.
- In another embodiment, the present invention provides a method for manufacturing an interconnection structure. The method includes the steps of providing a first conductive substrate, a second conductive substrate, and an insulating substrate; respectively forming a first circuit and a second circuit on the first conductive substrate and the second conductive substrate; forming a conductive bump on the second circuit; and connecting the insulating substrate with the first circuit and the second circuit by pressing the first conductive substrate, the insulating substrate and the second conductive substrate, wherein the conductive bump penetrates the insulating substrate to contact the first circuit.
- The present invention will now be described, by way of examples, with reference to the accompanying drawings, in which:
-
FIG. 1 illustrates a schematic view of a conventional interconnection structure for a printed circuit board; -
FIG. 2A toFIG. 2C illustrate schematic views of a method for manufacturing a first circuit in accordance with a first embodiment of the present invention; -
FIG. 3A toFIG. 3C illustrate schematic views of a method for manufacturing a second circuit in accordance with the first embodiment of the present invention; -
FIG. 3D toFIG. 3G illustrate schematic views of a method for manufacturing a first conductive bump on the second circuit in accordance with the first embodiment of the present invention; -
FIG. 4A toFIG. 4C illustrate schematic views of a method for manufacturing a printed circuit board with two circuit levels in accordance with the first embodiment of the present invention; -
FIG. 5A toFIG. 5B illustrate schematic views of a method for manufacturing a second conductive bump in accordance with a second embodiment of the present invention; and -
FIG. 6A toFIG. 6B illustrate schematic views of a method for manufacturing a printed circuit board with four circuit levels in accordance with the second embodiment of the present invention. - The preferred embodiments of the present invention will now be described in greater details by referring to the drawings that accompany the present application. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale. Descriptions of well-known components, materials, and process techniques are omitted so as not to unnecessarily obscure the embodiments of the invention.
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FIG. 2A toFIG. 2C ,FIG. 3A toFIG. 3G andFIGS. 4A to 4C schematically illustrate the first embodiment of the present invention, whereinFIG. 2A toFIG. 2C are directed to afirst circuit 25 formed on a firstconductive substrate 20. - As shown in
FIG. 2A , a firstconductive substrate 20 is provided. The first conductive substrate includes analignment hole 21 to be used later. An un-patternedphotoresist layer 23 and a first patternedphotoresist layer 24 are respectively formed on thesurface 20 a and thesurface 20 b of the firstconductive substrate 20. The firstconductive substrate 20 can be a copper foil, or be made of any other suitable conductive materials. The thickness of the firstconductive substrate 20 can vary, for example, about 0.1 mm in this embodiment. Thephotoresist layers photoresist layers - Referring to
FIG. 2B , using the photoresist layers 23 and 24 as masks, afirst circuit 25 is formed on the firstconductive substrate 20 by plating a conductive material in the openings of the firstpatterned photoresist layer 24. Preferably, thefirst circuit 25 can include ananti-etch layer 25N and aconductive layer 25C. Theanti-etch layer 25N can be a Ni layer with a thickness between 25 μm and 50 μm, and theconductive layer 25C can be a Cu layer with a thickness between 50 μm and 100 μm. The line width of thefirst circuit 25 is preferably between 15 μm and 100 μm. In the first embodiment, the line width of thefirst circuit 25 is 30 μm. Note that the photoresist layers 23 and 24 are removed after forming thefirst circuit 25, as shown inFIG. 2C . The structure ofFIG. 2C is to be used in subsequent steps. -
FIG. 3A toFIG. 3C are directed to asecond circuit 30 formed on a secondconductive substrate 30. - As shown in
FIG. 3A , a secondconductive substrate 30 is provided. The second conductive substrate includes analignment hole 31 corresponding to thealignment hole 21, which is to be used later. A secondpatterned photoresist layer 33 and anun-patterned photoresist layer 34 are respectively formed on thesurface 30 a and thesurface 30 b of the secondconductive substrate 30. Referring toFIG. 3B , using the photoresist layers 33 and 34 as masks, asecond circuit 35 is formed on the secondconductive substrate 30 by plating a conductive material in the openings of the secondpatterned photoresist layer 33. Preferably, the line width of thesecond circuit 35 is between 15 μm and 100 μm. In the first embodiment, the line width of thesecond circuit 35 is 30 μm. Materials and thicknesses of the related layers for fabricating thesecond circuit 35 are similar to those for thefirst circuit 35 as aforementioned. Note that the photoresist layers 33 and 34 are removed after forming thesecond circuit 35, as shown inFIG. 3C . -
FIG. 3D toFIG. 3G illustrate a method for forming a firstconductive bump 38 on thesecond circuit 35. - As shown in
FIG. 3D , a thirdpatterned photoresist layer 36 and anun-patterned photoresist layer 37 are respectively formed on thesurface 30 a and thesurface 30 b of the secondconductive substrate 30. A portion of thesecond circuit 35 is covered by the thirdpatterned photoresist layer 36 while another portion of thesecond circuit 35, which is reserved for forming a firstconductive bump 38 thereon, is exposed. Materials of the photoresist layers 36 and 37 can be similar to the photoresist layers 33 and 34. Note that the thickness of the thirdpatterned photoresist layer 36 is critical depending upon the thickness of the firstconductive bump 38 to be formed later. The thirdpatterned photoresist layer 36 is preferably thicker than that of thephotoresist layer patterned photoresist layer 36 is between 45 μm and 70 μm. - Referring to
FIG. 3E , using the photoresist layers 36 and 37 as masks, the firstconductive bump 38 are formed on thesecond circuit 35 by plating conductive materials in the openings of the thirdpatterned photoresist layer 36. InFIG. 3E , adiameter 38 d is defined with reference to the cross section of theconductive bump 38 along theline width 35 w of thefirst circuit 35. Note that, thediameter 38 d is preferably less than thewidth 35 w of thefirst circuit 35. Such a preferred design can increase the misalignment tolerance in the subsequent pressing steps and consequently reduce short circuits that might occur when mistakenly connecting theconductive bumps 38 with the undesired electrical joints. Theconductive bumps 38 can be made of copper or any suitable conductive materials. The thickness of theconductive bump 38 depends upon an insulatingsubstrate 40 to be used. In the first embodiment, the preferred thickness of theconductive bump 38 is between 45 μm and 70 μm. -
FIG. 3F illustrates an optional step, which demonstrates planarizing the surface of the firstconductive bumps 38 by polishing, which may also adjust the thickness of theconductive bump 38 to a desired value.FIG. 3G illustrates the step of removing the photoresist layers 36 and 37. The resultant structure ofFIG. 3G is to be used in subsequent steps. -
FIG. 4A toFIG. 4C illustrate a method for connecting thefirst circuit 25, thesecond circuit 35, and the insulatingsubstrate 40, wherein theconductive bumps 38 penetrate the insulatingsubstrate 40 to contact thefirst circuit 25. - As shown in
FIG. 4A , the insulatingsubstrate 40 is disposed between the firstconductive substrate 20 ofFIG. 2C and the secondconductive substrate 30 ofFIG. 3G , and opposite sides of thefirst circuit 25, thesecond circuit 35 or theconductive bumps 38 are set to face the insulatingsubstrate 40. The insulatingsubstrate 40 is formed with analignment hole 40 corresponding to the alignment holes 21 and 31, as indicated by a dotted line. Preferably, the insulatingsubstrate 40 can be a sheet made of polymers, such as epoxy resins or polyimide resins, with a thickness between 45 μm and 70 μm. In other embodiments, the insulatingsubstrate 40 may contain reinforced materials, for example, glass fibers. Note that, as shown inFIG. 4A , the insulatingsubstrate 40 is further formed withopenings 42 corresponding to the firstconductive bumps 38. Theopenings 42 provide spaces for the firstconductive bumps 38 to penetrate the insulatingsubstrate 40. Conventional laser drilling techniques can perform the step of forming theopenings 42. -
FIG. 4B illustrates the step of pressing the firstconductive substrate 20, the insulatingsubstrate 40 and the secondconductive substrate 30. Preferably, the insulatingsubstrate 40 is heated to soften polymers contained therein before pressing. The temperature for softening depends upon the glass transition temperature of the polymers. In the first embodiment, the pressure for pressing is set at around 20 Kg/cm2 to 40 Kg/cm2. Note that during the pressing operation, some fluids of the polymers may flow out of the edge of the substrates. After the heating and the pressing, the insulatingsubstrate 40 connects thefirst circuit 25 and thesecond circuit 35 as adhesions generated from the softened polymers. Furthermore, since the softened polymers are fluid and movable, thefirst circuit 25 and thesecond circuit 35 are embedded in the insulatingsubstrate 40. In the first embodiment, theconductive bumps 38 are in contact with thefirst circuit 25 by penetrating the insulatingsubstrate 40 through theopenings 42. Note that the step of forming theopenings 42 prior to the pressing can be omitted if the heated insulatingsubstrate 40, regardless of containing reinforced materials or not, is adapted to be penetrated directly by the conductive bumps. -
FIG. 4C illustrate the step of removing the firstconductive substrate 20 and the secondconductive substrate 30 after the pressing step ofFIG. 4B . The removing step is preferably preformed by etching. After removing the firstconductive substrate 20 and the secondconductive substrate 30, theanti-etch layers FIG. 4C shows the resultant printed circuit board with twocircuit layers substrate 40. -
FIG. 5A toFIG. 5B illustrate a method for manufacturing secondconductive bumps conductive substrate 20 and the secondconductive substrate 30 in the second embodiment are removed partially rather than completely. A portion of the firstconductive substrate 20 and the secondconductive substrate 30 remain for creating the secondconductive bumps - Specifically, as shown in
FIG. 5A , fourth patterned photoresist layers 51 and 52 are formed on the firstconductive substrate 20 and the secondconductive substrate 30 of the structure ofFIG. 4B . Then, using the fourth patterned photoresist layers 51 and 52 as masks,anti-etch layers conductive substrate 20 and the secondconductive substrate 30. Materials for the photoresist layers 51 and 52 are similar to the photoresist layers 23 and 24 as aforementioned. Theanti-etch layer - Referring to
FIG. 5B , the fourth patterned photoresist layers 51 and 52 are first removed. Then, using theanti-etch layers conductive bumps conductive substrate 20 and the secondconductive substrate 30. Next, theanti-etch layers FIG. 6A . -
FIG. 6A illustrates a thirdconductive substrate 70 with thethird circuit 71; one insulatingsubstrate 60; the insulatingsubstrate 40 with the secondconductive bumps substrate 60; and a fourthconductive substrate 80 with thefourth circuit 81, which are arranged in sequence for pressing. Details for manufacturing the thirdconductive substrate 70 and the fourthconductive substrate 80 are set forth above in connection with the descriptions ofFIG. 2A toFIG. 2C . Details for pressing techniques are set forth above in connection with the descriptions ofFIG. 4A andFIG. 4B . -
FIG. 6B illustrates the resultant structure after pressing the substrates as shown inFIG. 6A ; followed by removing the thirdconductive substrate 70 and the fourthconductive substrate 80; and stripping off theanti-etch layers third circuit 71 and thefourth circuit 81 are embedded in the insulatingsubstrates 60. That is,FIG. 6B shows the resultant printed circuit board with four circuit layers according to the second embodiment, wherein the thickness of the printed circuit board is substantially as thin as the combination of the insulatingsubstrates - The detailed description of the above preferable embodiments is to describe the technical features and spirit of the present invention, and the disclosed preferable embodiments are not intended to limit the scope of the present invention. On the contrary, the preferable embodiments and their variations or equivalents all fall within the scope of the present invention. Therefore, the scope of the present invention should be most broadly interpreted according to the foregoing description and includes all possible variations and equivalents.
Claims (15)
1. A method for manufacturing an interconnection structure, the method comprising the steps of:
providing a first conductive substrate, a second conductive substrate, and an insulating substrate;
respectively forming a first circuit and a second circuit on the first conductive substrate and the second conductive substrate;
forming a conductive bump on the second circuit; and
connecting the insulating substrate with the first circuit and the second circuit by pressing the first conductive substrate, the insulating substrate and the second conductive substrate, wherein the conductive bump penetrates the insulating substrate to contact the first circuit.
2. The method according to claim 1 , wherein the step of forming the conductive bump comprises:
forming a patterned photoresist layer on the second circuit; and
plating a conductive material on the second circuit.
3. The method according to claim 1 , further comprising planarizing the conductive bump prior to the step of pressing.
4. The method according to claim 1 , further comprising forming an opening in the insulating substrate prior to the step of pressing, wherein the conductive bump penetrates the insulating substrate through the opening.
5. The method according to claim 4 , wherein the step of forming the opening is conducted by lasers drilling.
6. The method according to claim 1 , further comprising heating the insulating substrate for softening polymers contained in the insulating substrate.
7. The method according to claim 1 , wherein the first circuit and the second circuit are embedded in the insulating substrate via the step of pressing.
8. The method according to claim 1 , further comprising removing the first conductive substrate and the second conductive substrate to expose the first circuit and the second circuit after the step of pressing.
9. The method according to claim 1 , further comprising removing a portion of the first conductive substrate and remaining another portion of the first conductive substrate after the step of pressing.
10. An interconnection structure for a printed circuit board, wherein the interconnection structure is made by the method according to claim 1 .
11. An interconnection structure for a printed circuit board, comprising:
an insulating substrate;
a first circuit exposed on a first surface of the insulating substrate;
a second circuit exposed on a second surface of the insulating substrate: and
a first conductive bump connecting the first circuit and the second circuit,
wherein the first circuit, the second circuit and the first conductive bump are embedded in the insulating substrate.
12. The interconnection structure according to claim 11 , wherein one of the first circuit and the second circuit is formed with a line width between 15 μm and 100 μm.
13. The interconnection structure according to claim 12 , wherein the first conductive bump comprises a cross section having a diameter less than the line width.
14. The interconnection structure according to claim 11 , wherein the first conductive bump is formed by plating.
15. The interconnection structure according to claim 11 , further comprising a second conductive bump on the first surface, wherein the second conductive bump connects the first circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US13/069,874 US20110168438A1 (en) | 2007-03-19 | 2011-03-23 | Interconnection structure and method thereof |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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TW96109328 | 2007-03-19 | ||
TW096109328A TW200839941A (en) | 2007-03-19 | 2007-03-19 | Interconnection structure and method thereof |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US13/069,874 Division US20110168438A1 (en) | 2007-03-19 | 2011-03-23 | Interconnection structure and method thereof |
Publications (1)
Publication Number | Publication Date |
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US20080230264A1 true US20080230264A1 (en) | 2008-09-25 |
Family
ID=39773567
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US12/045,362 Abandoned US20080230264A1 (en) | 2007-03-19 | 2008-03-10 | Interconnection structure and method thereof |
US13/069,874 Abandoned US20110168438A1 (en) | 2007-03-19 | 2011-03-23 | Interconnection structure and method thereof |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
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US13/069,874 Abandoned US20110168438A1 (en) | 2007-03-19 | 2011-03-23 | Interconnection structure and method thereof |
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US (2) | US20080230264A1 (en) |
TW (1) | TW200839941A (en) |
Cited By (7)
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US20140027925A1 (en) * | 2012-07-26 | 2014-01-30 | Unimicron Technology Corporation | Through-holed interposer, packaging substrate, and methods of fabricating the same |
US20140242777A1 (en) * | 2013-02-26 | 2014-08-28 | Varughese Mathew | Method for Bonding Semiconductor Devices |
CN105611729A (en) * | 2016-03-10 | 2016-05-25 | 安捷利电子科技(苏州)有限公司 | Printed circuit board |
CN107205312A (en) * | 2016-03-16 | 2017-09-26 | 景硕科技股份有限公司 | Double-layer circuit board and preparation method thereof |
CN107205311A (en) * | 2016-03-16 | 2017-09-26 | 景硕科技股份有限公司 | Without weld pad multilayer circuit board and preparation method thereof |
CN113141727A (en) * | 2020-01-17 | 2021-07-20 | 庆鼎精密电子(淮安)有限公司 | Circuit board with embedded electronic element and manufacturing method thereof |
CN113194620A (en) * | 2021-04-25 | 2021-07-30 | 珠海方正科技多层电路板有限公司 | Method for drilling non-metallized hole and printed circuit board |
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US7238603B2 (en) * | 2002-02-18 | 2007-07-03 | Tessera Interconnect Materials, Inc. | Connecting member between wiring films, manufacturing method thereof, and manufacturing method of multilayer wiring substrate |
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US20140027925A1 (en) * | 2012-07-26 | 2014-01-30 | Unimicron Technology Corporation | Through-holed interposer, packaging substrate, and methods of fabricating the same |
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US8981570B2 (en) * | 2012-07-26 | 2015-03-17 | Unimicron Technology Corporation | Through-holed interposer, packaging substrate, and methods of fabricating the same |
US9224683B2 (en) | 2012-07-26 | 2015-12-29 | Unimicron Technology Corporation | Method of fabricating packaging substrate having a through-holed interposer |
US9337136B2 (en) | 2012-07-26 | 2016-05-10 | Unimicron Technology Corporation | Method of fabricating a through-holed interposer |
US9460992B2 (en) | 2012-07-26 | 2016-10-04 | Unimicron Technology Corp. | Packaging substrate having a through-holed interposer |
US20140242777A1 (en) * | 2013-02-26 | 2014-08-28 | Varughese Mathew | Method for Bonding Semiconductor Devices |
CN105611729A (en) * | 2016-03-10 | 2016-05-25 | 安捷利电子科技(苏州)有限公司 | Printed circuit board |
CN107205312A (en) * | 2016-03-16 | 2017-09-26 | 景硕科技股份有限公司 | Double-layer circuit board and preparation method thereof |
CN107205311A (en) * | 2016-03-16 | 2017-09-26 | 景硕科技股份有限公司 | Without weld pad multilayer circuit board and preparation method thereof |
CN113141727A (en) * | 2020-01-17 | 2021-07-20 | 庆鼎精密电子(淮安)有限公司 | Circuit board with embedded electronic element and manufacturing method thereof |
CN113194620A (en) * | 2021-04-25 | 2021-07-30 | 珠海方正科技多层电路板有限公司 | Method for drilling non-metallized hole and printed circuit board |
Also Published As
Publication number | Publication date |
---|---|
TW200839941A (en) | 2008-10-01 |
US20110168438A1 (en) | 2011-07-14 |
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