US20070296469A1 - Data Receiving Circuit With Current Mirror and Data Slicer - Google Patents
Data Receiving Circuit With Current Mirror and Data Slicer Download PDFInfo
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- US20070296469A1 US20070296469A1 US11/666,482 US66648205A US2007296469A1 US 20070296469 A1 US20070296469 A1 US 20070296469A1 US 66648205 A US66648205 A US 66648205A US 2007296469 A1 US2007296469 A1 US 2007296469A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H40/00—Arrangements specially adapted for receiving broadcast information
- H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
- H04H40/27—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
- H04H40/90—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for satellite broadcast receiving
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/19—Monitoring patterns of pulse trains
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0292—Arrangements specific to the receiver end
- H04L25/0294—Provision for current-mode coupling
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/20—Adaptations for transmission via a GHz frequency band, e.g. via satellite
Definitions
- the present invention generally relates to data communication for purposes such as Digital Satellite Equipment Control (DiSEqC), and more particularly, to a data receiving circuit that is capable of properly receiving current modulated signals having a wide range of frequencies.
- DISEqC Digital Satellite Equipment Control
- DiSEqC Data communication for DiSEqC has historically been performed through the modulation of a 22 kHz voltage tone. This modulated tone may be superimposed onto a direct current (DC) voltage that powers one or more low noise blocks (LNBs) of a satellite receiving system.
- DC direct current
- LNBs low noise blocks
- an integrated receiver/decoder (IRD) apparatus e.g., set-top box, etc.
- IRD integrated receiver/decoder
- DiSEqC communication may also include a return channel (e.g., on the same transmission medium) in which current modulated signals are transmitted from the LNB and/or switching unit back to the IRD apparatus.
- FIG. 1 shows a data receiving circuit according to conventional art that may be used to receive current modulated signals via a DiSEqC return channel.
- the conventional data receiving circuit of FIG. 1 includes RLC circuitry for converting a pulsed 45 mA current modulated signal provided from an LNB or switching unit to a semi-sinusoidal voltage signal.
- FIGS. 2 and 3 A depiction of the pulsed current modulated signal and the resultant semi-sinusoidal voltage signal for two different frequencies is shown in FIGS. 2 and 3 .
- the resultant semi-sinusoidal voltage signal is sliced by a subsequent data slicer circuit to generate a sliced digital output signal which may then be envelope and edge detected by a processor (not shown in FIG. 1 ).
- waveforms are shown for the current modulated signal provided from the LNB or switching unit at a frequency of 22 kHz (i.e., lower waveform), and the resultant semi-sinusoidal voltage signal provided by the RLC circuitry (i.e., upper waveform).
- the waveforms of FIG. 2 may be contrasted with the waveforms of FIG. 3 .
- waveforms are shown for the current modulated signal provided from the LNB or switching unit at a frequency of 88 kHz (i.e., lower waveform), and the resultant semi-sinusoidal voltage signal provided by the RLC circuitry (i.e., upper waveform). Comparing the voltage waveforms of FIGS. 2 and 3 , it is evident that the amplitude of the semi-sinusoidal voltage signal provided by the RLC circuitry decreases as the frequency of the current modulated signal provided from the LNB or switching unit increases. In this manner, the amplitude of the semi-sinusoidal voltage signal provided by the RLC circuitry of FIG.
- a data receiving circuit comprises a current mirror operative to receive a current modulated signal from an external device and to convert the current modulated signal to a voltage signal.
- a data slicer is operative to generate digital data responsive to the voltage signal.
- a method for receiving a current modulated signal comprises receiving the current modulated signal from an external device, using a current mirror to convert the current modulated signal to a voltage signal, and generating digital data responsive to the voltage signal.
- an apparatus comprising current mirroring means for receiving a current modulated signal from an external device and converting the current modulated signal to a voltage signal.
- Data slicing means generates digital data responsive to the voltage signal.
- FIG. 1 shows circuitry including a data receiving circuit according to conventional art
- FIG. 2 shows exemplary waveforms related to the data receiving circuit of FIG. 1 in which the frequency of a current modulated signal is 22 kHz;
- FIG. 3 shows exemplary waveforms related to the data receiving circuit of FIG. 1 in which the frequency of a current modulated signal is 88 kHz;
- FIG. 4 shows circuitry including a data receiving circuit according to an exemplary embodiment of the present invention
- FIG. 5 shows exemplary waveforms related to the data receiving circuit of FIG. 4 in which the frequency of a current modulated signal is 22 kHz;
- FIG. 6 shows exemplary waveforms related to the data receiving circuit of FIG. 4 in which the frequency of a current modulated signal is 88 kHz.
- Circuitry 100 including a data receiving circuit comprises an external device 10 , and a data receiving circuit including current mirroring means such as current mirror 20 and data slicing means such as data slicer 30 .
- a data receiving circuit including current mirroring means such as current mirror 20 and data slicing means such as data slicer 30 .
- Preferred values for many of the circuit elements are shown in FIG. 4 , although different values may also be used.
- circuitry 100 of FIG. 4 represents a portion of a satellite receiving system in which external device 10 represents a portion of an LNB and/or radio frequency (RF) switch, and the data receiving circuit represents a portion of an IRD apparatus (e.g., set-top box, etc.) used to receive and process signals including satellite signals.
- circuitry 100 of FIG. 4 may be used for DiSEqC, and/or for other types of data communication.
- the data receiving circuit of FIG. 4 may also be implemented in other types of systems and/or devices such as television signal receivers and/or other devices.
- External device 10 comprises current means such as a 22 kHz, 30 mA pulsed current sink 15 and a fixed current sink 16 of 100 mA. These two currents sum together and draw current from voltage source V 80 .
- the resulting current may be modulated using any suitable modulation technique by a modulation controller (not shown in FIG. 4 ) and provided to current mirror 20 as a current modulated signal via a transmission medium such as coaxial cable and/or other medium.
- this current modulated signal may represent a return channel signal provided for purposes of DiSEqC.
- Current mirror 20 comprises voltage means such as voltage source V 80 , resistance means such as resistors R 181 and R 184 to R 186 , and switching means such as transistors Q 54 to Q 57 .
- transistors Q 54 and Q 55 are pnp-type bipolar junction transistors (BJTs), and transistors Q 56 and Q 57 are npn-type BJTs.
- BJTs pnp-type bipolar junction transistors
- FETs field effect transistors
- Transistors Q 54 to Q 57 are operatively coupled in the manner shown in FIG. 4 .
- the base terminal of transistor Q 54 is operatively coupled to the base terminal of transistor Q 55
- the base terminal of transistor Q 57 is operatively coupled to the base terminal of transistor Q 56
- the collector terminal of transistor Q 54 is operatively coupled to the collector terminal of transistor Q 57
- the collector terminal of transistor Q 55 is operatively coupled to the collector terminal of transistor Q 56
- the base terminals of transistors Q 54 and Q 55 are operatively coupled to the collector terminals of transistors Q 55 and Q 56
- the base terminals of transistors Q 56 and Q 57 are operatively coupled to the collector terminals of transistors Q 54 and Q 57 .
- the current modulated signal provided from external device 10 flows through resistor R 181 of current mirror 20 where a voltage proportional to the current is dropped across it.
- Current mirror 20 conducts and maintains substantially the same current in each of its two signal paths, namely the signal path defined by transistors Q 54 and Q 57 (i.e., the left leg of current mirror 20 ) and the signal path defined by transistors Q 55 and Q 56 (i.e., the right leg of current mirror 20 ). In this manner, the current in the left leg of current mirror 20 is “mirrored” in its right leg due to the configuration of transistors Q 54 to Q 57 and the fact that resistors R 185 and R 186 have the same resistance.
- the voltage across resistor R 184 is approximately the same as the voltage across resistor R 181 .
- the voltage across resistor R 184 divided by its resistance determines the current in the right and left legs of current mirror 20 .
- the voltage across resistors R 185 and R 186 is proportional to the current flowing through resistor R 181 , and is referenced to ground.
- the operation of current mirror 20 produces a current to voltage conversion, which according to an exemplary embodiment is approximately 10 millivolts per milliamp (mV/mA).
- the converted voltage signal produced by current mirror 20 is AC coupled to data slicer 30 via capacitance means such as capacitor C 53 .
- Data slicer 30 comprises voltage means such as voltage source V 85 , resistance means such as resistors R 194 to R 196 , R 201 and R 202 , and signal comparing means such as comparator U 18 A.
- Resistors R 194 and R 202 of data slicer 30 produce a 50 % voltage divider.
- Resistors R 195 and R 201 of data slicer 30 produce a voltage divider that is slightly greater than 50%. It is this difference in reference points that must be overcome in order for data slicer 30 to reach the threshold of detection. This detection threshold gives the data receiving circuit of FIG. 4 its noise immunity margin.
- the current modulation needs to reach 30 mA of current excursion to breach the detection threshold and enable comparator U 18 A to provide a valid digital output signal.
- the sliced digital output signal of comparator U 18 A is provided to a peak detector circuit and in turn to a processor (neither of which are shown in FIG. 4 ) where edge detection and timing to demodulate intelligent signals takes place.
- the data receiving circuit of FIG. 4 overcomes the problems associated with conventional data receiving circuits such as the RLC circuitry of FIG. 1 in that it is capable of properly receiving current modulated signals having a wide range of frequencies.
- the ability of the data receiving circuit of FIG. 4 to properly receive current modulated signals having a wide range of frequencies is evident from the waveforms shown in FIGS. 5 and 6 .
- FIG. 5 and 6 In FIG.
- waveforms are shown for: (i) a current modulated signal provided from external device 10 at a frequency of 22 kHz (i.e., middle waveform), (ii) the resultant converted voltage signal provided to the non-inverting (+) input terminal of comparator U 18 A along with the constant voltage signal provided to the inverting ( ⁇ ) input terminal of comparator U 18 A (i.e., lower waveform), and (iii) the resultant (i.e., sliced) digital output signal provided from comparator U 18 A (i.e., upper waveform).
- the waveforms of FIG. 5 may be compared to the waveforms of FIG. 6 .
- waveforms are shown for: (i) a current modulated signal provided from external device 10 at a frequency of 88 kHz (i.e., middle waveform), (ii) the resultant converted voltage signal provided to the non-inverting (+) input terminal of comparator U 18 A along with the constant voltage signal provided to the inverting ( ⁇ ) input terminal of comparator U 18 A (i.e., lower waveform), and (iii) the resultant (i.e., sliced) digital output signal provided from comparator U 18 A (i.e., upper waveform).
- a current modulated signal provided from external device 10 at a frequency of 88 kHz (i.e., middle waveform)
- the resultant converted voltage signal provided to the non-inverting (+) input terminal of comparator U 18 A along with the constant voltage signal provided to the inverting ( ⁇ ) input terminal of comparator U 18 A (i.e., lower
- signal amplitudes of the converted voltage signals provided to the non-inverting (+) input terminal of comparator U 18 A and the resultant (i.e., sliced) digital output signal provided from comparator U 18 A remain essentially constant despite the relatively significant frequency difference (i.e., 22 kHz versus 88 kHz).
- the data receiving circuit of FIG. 4 advantageously avoids the frequency dependent nature of conventional data receiving circuits such as the one shown in FIG. 1 .
- the present invention provides a data communication circuit that is capable of properly receiving current modulated signals having a wide range of frequencies.
- the present invention may be applicable to various apparatuses, either with or without an integrated display device.
- the phrase “television signal receiver” or “IRD apparatus” as used herein may refer to systems or apparatuses including, but not limited to, television sets, computers or monitors that include an integrated display device, and systems or apparatuses such as set-top boxes, video cassette recorders (VCRs), digital versatile disk (DVD) players, video game boxes, personal video recorders (PVRs), computers or other apparatuses that may not include an integrated display device.
- VCRs video cassette recorders
- DVD digital versatile disk
- PVRs personal video recorders
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- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Nonlinear Science (AREA)
- Astronomy & Astrophysics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
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- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
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Abstract
Description
- This application claims priority to and all benefits accruing from a provisional application filed in the United States Patent and Trademark Office on Nov, 3, 2004, and there assigned Ser. No. 60/624,661.
- 1. Field of the Invention
- The present invention generally relates to data communication for purposes such as Digital Satellite Equipment Control (DiSEqC), and more particularly, to a data receiving circuit that is capable of properly receiving current modulated signals having a wide range of frequencies.
- 2. Background Information
- Data communication for DiSEqC has historically been performed through the modulation of a 22 kHz voltage tone. This modulated tone may be superimposed onto a direct current (DC) voltage that powers one or more low noise blocks (LNBs) of a satellite receiving system. Using DiSEqC, an integrated receiver/decoder (IRD) apparatus (e.g., set-top box, etc.) may for example transmit signals via a transmission medium such as coaxial cable that enable selection and control of a particular LNB via a switching unit. DiSEqC communication may also include a return channel (e.g., on the same transmission medium) in which current modulated signals are transmitted from the LNB and/or switching unit back to the IRD apparatus.
- IRD apparatuses may include dedicated circuitry for receiving the current modulated signals provided via the return channel.
FIG. 1 shows a data receiving circuit according to conventional art that may be used to receive current modulated signals via a DiSEqC return channel. In particular, the conventional data receiving circuit ofFIG. 1 includes RLC circuitry for converting a pulsed 45 mA current modulated signal provided from an LNB or switching unit to a semi-sinusoidal voltage signal. A depiction of the pulsed current modulated signal and the resultant semi-sinusoidal voltage signal for two different frequencies is shown inFIGS. 2 and 3 . InFIG. 1 , the resultant semi-sinusoidal voltage signal is sliced by a subsequent data slicer circuit to generate a sliced digital output signal which may then be envelope and edge detected by a processor (not shown inFIG. 1 ). - With the conventional data receiving circuit of
FIG. 1 , problems may arise when the current modulated signal provided from the LNB or switching unit exhibits different frequencies. In particular, when the current modulated signal exhibits different frequencies, the semi-sinusoidal voltage signal provided by the RLC circuitry exhibits inconsistent amplitudes which can create processing errors in the aforementioned data slicing, envelope detection and edge detection functions. These amplitude inconsistencies are evident from the waveforms shown inFIGS. 2 and 3 . InFIG. 2 , for example, waveforms are shown for the current modulated signal provided from the LNB or switching unit at a frequency of 22 kHz (i.e., lower waveform), and the resultant semi-sinusoidal voltage signal provided by the RLC circuitry (i.e., upper waveform). - The waveforms of
FIG. 2 may be contrasted with the waveforms ofFIG. 3 . InFIG. 3 , waveforms are shown for the current modulated signal provided from the LNB or switching unit at a frequency of 88 kHz (i.e., lower waveform), and the resultant semi-sinusoidal voltage signal provided by the RLC circuitry (i.e., upper waveform). Comparing the voltage waveforms ofFIGS. 2 and 3 , it is evident that the amplitude of the semi-sinusoidal voltage signal provided by the RLC circuitry decreases as the frequency of the current modulated signal provided from the LNB or switching unit increases. In this manner, the amplitude of the semi-sinusoidal voltage signal provided by the RLC circuitry ofFIG. 1 is dependent upon the frequency of current modulated signal provided from the LNB or switching unit. When the amplitude of the semi-sinusoidal voltage signal provided by the RLC circuitry is below a given threshold, processing errors may occur in the aforementioned data slicing, envelope detection and edge detection functions. - Accordingly, there is a need for a data receiving circuit capable of avoiding the foregoing problems by properly receiving current modulated signals having a wide range of frequencies. The present invention addresses these and/or other issues.
- In accordance with an aspect of the present invention, a data receiving circuit is disclosed. According to an exemplary embodiment, the data receiving circuit comprises a current mirror operative to receive a current modulated signal from an external device and to convert the current modulated signal to a voltage signal. A data slicer is operative to generate digital data responsive to the voltage signal.
- In accordance with another aspect of the present invention, a method for receiving a current modulated signal is disclosed. According to an exemplary embodiment, the method comprises receiving the current modulated signal from an external device, using a current mirror to convert the current modulated signal to a voltage signal, and generating digital data responsive to the voltage signal.
- In accordance with another aspect of the present invention, an apparatus is disclosed. According to an exemplary embodiment, the apparatus comprises current mirroring means for receiving a current modulated signal from an external device and converting the current modulated signal to a voltage signal. Data slicing means generates digital data responsive to the voltage signal.
- The above-mentioned and other features and advantages of this invention, and the manner of attaining them, will become more apparent and the invention will be better understood by reference to the following description of embodiments of the invention taken in conjunction with the accompanying drawings, wherein:
-
FIG. 1 shows circuitry including a data receiving circuit according to conventional art; -
FIG. 2 shows exemplary waveforms related to the data receiving circuit ofFIG. 1 in which the frequency of a current modulated signal is 22 kHz; -
FIG. 3 shows exemplary waveforms related to the data receiving circuit ofFIG. 1 in which the frequency of a current modulated signal is 88 kHz; -
FIG. 4 shows circuitry including a data receiving circuit according to an exemplary embodiment of the present invention; -
FIG. 5 shows exemplary waveforms related to the data receiving circuit ofFIG. 4 in which the frequency of a current modulated signal is 22 kHz; and -
FIG. 6 shows exemplary waveforms related to the data receiving circuit ofFIG. 4 in which the frequency of a current modulated signal is 88 kHz. - The exemplifications set out herein illustrate preferred embodiments of the invention, and such exemplifications are not to be construed as limiting the scope of the invention in any manner.
- Referring now to the drawings, and more particularly to
FIG. 4 ,circuitry 100 including a data receiving circuit according to an exemplary embodiment of the present invention is shown.Circuitry 100 ofFIG. 4 comprises anexternal device 10, and a data receiving circuit including current mirroring means such ascurrent mirror 20 and data slicing means such asdata slicer 30. Preferred values for many of the circuit elements are shown inFIG. 4 , although different values may also be used. - According to an exemplary embodiment,
circuitry 100 ofFIG. 4 represents a portion of a satellite receiving system in whichexternal device 10 represents a portion of an LNB and/or radio frequency (RF) switch, and the data receiving circuit represents a portion of an IRD apparatus (e.g., set-top box, etc.) used to receive and process signals including satellite signals. Accordingly,circuitry 100 ofFIG. 4 may be used for DiSEqC, and/or for other types of data communication. The data receiving circuit ofFIG. 4 may also be implemented in other types of systems and/or devices such as television signal receivers and/or other devices. -
External device 10 comprises current means such as a 22 kHz, 30 mA pulsedcurrent sink 15 and a fixedcurrent sink 16 of 100 mA. These two currents sum together and draw current from voltage source V80. The resulting current may be modulated using any suitable modulation technique by a modulation controller (not shown inFIG. 4 ) and provided tocurrent mirror 20 as a current modulated signal via a transmission medium such as coaxial cable and/or other medium. According to an exemplary embodiment, this current modulated signal may represent a return channel signal provided for purposes of DiSEqC. -
Current mirror 20 comprises voltage means such as voltage source V80, resistance means such as resistors R181 and R184 to R186, and switching means such as transistors Q54 to Q57. As indicated inFIG. 4 , transistors Q54 and Q55 are pnp-type bipolar junction transistors (BJTs), and transistors Q56 and Q57 are npn-type BJTs. Although BJTs are used in the exemplary embodiment ofFIG. 4 , field effect transistors (FETs) could also be used. Transistors Q54 to Q57 are operatively coupled in the manner shown inFIG. 4 . In particular, the base terminal of transistor Q54 is operatively coupled to the base terminal of transistor Q55, and the base terminal of transistor Q57 is operatively coupled to the base terminal of transistor Q56. The collector terminal of transistor Q54 is operatively coupled to the collector terminal of transistor Q57, and the collector terminal of transistor Q55 is operatively coupled to the collector terminal of transistor Q56. Moreover, the base terminals of transistors Q54 and Q55 are operatively coupled to the collector terminals of transistors Q55 and Q56, and the base terminals of transistors Q56 and Q57 are operatively coupled to the collector terminals of transistors Q54 and Q57. - In operation, the current modulated signal provided from
external device 10 flows through resistor R181 ofcurrent mirror 20 where a voltage proportional to the current is dropped across it.Current mirror 20 conducts and maintains substantially the same current in each of its two signal paths, namely the signal path defined by transistors Q54 and Q57 (i.e., the left leg of current mirror 20) and the signal path defined by transistors Q55 and Q56 (i.e., the right leg of current mirror 20). In this manner, the current in the left leg ofcurrent mirror 20 is “mirrored” in its right leg due to the configuration of transistors Q54 to Q57 and the fact that resistors R185 and R186 have the same resistance. The voltage across resistor R184 is approximately the same as the voltage across resistor R181. The voltage across resistor R184 divided by its resistance determines the current in the right and left legs ofcurrent mirror 20. The voltage across resistors R185 and R186 is proportional to the current flowing through resistor R181, and is referenced to ground. The operation ofcurrent mirror 20 produces a current to voltage conversion, which according to an exemplary embodiment is approximately 10 millivolts per milliamp (mV/mA). The converted voltage signal produced bycurrent mirror 20 is AC coupled todata slicer 30 via capacitance means such as capacitor C53. -
Data slicer 30 comprises voltage means such as voltage source V85, resistance means such as resistors R194 to R196, R201 and R202, and signal comparing means such as comparator U18A. Resistors R194 and R202 ofdata slicer 30 produce a 50% voltage divider. Resistors R195 and R201 ofdata slicer 30 produce a voltage divider that is slightly greater than 50%. It is this difference in reference points that must be overcome in order for data slicer 30 to reach the threshold of detection. This detection threshold gives the data receiving circuit ofFIG. 4 its noise immunity margin. With the data receiving circuit ofFIG. 4 , the current modulation needs to reach 30 mA of current excursion to breach the detection threshold and enable comparator U18A to provide a valid digital output signal. The sliced digital output signal of comparator U18A is provided to a peak detector circuit and in turn to a processor (neither of which are shown inFIG. 4 ) where edge detection and timing to demodulate intelligent signals takes place. - The data receiving circuit of
FIG. 4 overcomes the problems associated with conventional data receiving circuits such as the RLC circuitry ofFIG. 1 in that it is capable of properly receiving current modulated signals having a wide range of frequencies. The ability of the data receiving circuit ofFIG. 4 to properly receive current modulated signals having a wide range of frequencies is evident from the waveforms shown inFIGS. 5 and 6 . InFIG. 5 , for example, waveforms are shown for: (i) a current modulated signal provided fromexternal device 10 at a frequency of 22 kHz (i.e., middle waveform), (ii) the resultant converted voltage signal provided to the non-inverting (+) input terminal of comparator U18A along with the constant voltage signal provided to the inverting (−) input terminal of comparator U18A (i.e., lower waveform), and (iii) the resultant (i.e., sliced) digital output signal provided from comparator U18A (i.e., upper waveform). - The waveforms of
FIG. 5 may be compared to the waveforms ofFIG. 6 . InFIG. 6 , waveforms are shown for: (i) a current modulated signal provided fromexternal device 10 at a frequency of 88 kHz (i.e., middle waveform), (ii) the resultant converted voltage signal provided to the non-inverting (+) input terminal of comparator U18A along with the constant voltage signal provided to the inverting (−) input terminal of comparator U18A (i.e., lower waveform), and (iii) the resultant (i.e., sliced) digital output signal provided from comparator U18A (i.e., upper waveform). As indicated inFIGS. 5 and 6 , signal amplitudes of the converted voltage signals provided to the non-inverting (+) input terminal of comparator U18A and the resultant (i.e., sliced) digital output signal provided from comparator U18A remain essentially constant despite the relatively significant frequency difference (i.e., 22 kHz versus 88 kHz). In this manner, the data receiving circuit ofFIG. 4 advantageously avoids the frequency dependent nature of conventional data receiving circuits such as the one shown inFIG. 1 . - As described herein, the present invention provides a data communication circuit that is capable of properly receiving current modulated signals having a wide range of frequencies. The present invention may be applicable to various apparatuses, either with or without an integrated display device. Accordingly, the phrase “television signal receiver” or “IRD apparatus” as used herein may refer to systems or apparatuses including, but not limited to, television sets, computers or monitors that include an integrated display device, and systems or apparatuses such as set-top boxes, video cassette recorders (VCRs), digital versatile disk (DVD) players, video game boxes, personal video recorders (PVRs), computers or other apparatuses that may not include an integrated display device.
- While this invention has been described as having a preferred design, the present invention can be further modified within the spirit and scope of this disclosure. This application is therefore intended to cover any variations, uses, or adaptations of the invention using its general principles. Further, this application is intended to cover such departures from the present disclosure as come within known or customary practice in the art to which this invention pertains and which fall within the limits of the appended claims.
Claims (28)
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US11/666,482 US8433239B2 (en) | 2004-11-03 | 2005-10-26 | Data receiving circuit with current mirror and data slicer |
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US62466104P | 2004-11-03 | 2004-11-03 | |
US11/666,482 US8433239B2 (en) | 2004-11-03 | 2005-10-26 | Data receiving circuit with current mirror and data slicer |
PCT/US2005/038506 WO2006052450A1 (en) | 2004-11-03 | 2005-10-26 | Data receiving circuit with current mirror and data slicer |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070082610A1 (en) * | 2005-10-12 | 2007-04-12 | Kesse Ho | Dynamic current sharing in Ka/Ku LNB design |
US20110151769A1 (en) * | 2008-09-26 | 2011-06-23 | John James Fitzpatrick | Method for controlling signal transmission for multiple devices |
US20130051481A1 (en) * | 2011-08-30 | 2013-02-28 | Sony Corporation | Electric power-supply apparatus and receiving apparatus |
US20150022183A1 (en) * | 2010-10-28 | 2015-01-22 | Infineon Technologies Austria Ag | Accessory Presence Detection |
Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4412186A (en) * | 1980-04-14 | 1983-10-25 | Tokyo Shibaura Denki Kabushiki Kaisha | Current mirror circuit |
US4942593A (en) * | 1989-03-16 | 1990-07-17 | Dallas Semiconductor Corporation | Telecommunications interface with improved jitter reporting |
US4961009A (en) * | 1988-06-29 | 1990-10-02 | Goldstar Semiconductor, Ltd. | Current-voltage converting circuit utilizing CMOS-type transistor |
US5289278A (en) * | 1991-02-21 | 1994-02-22 | Plessey Semiconductors Limited | Duo-binary and/or binary data slicer |
US5319514A (en) * | 1992-03-03 | 1994-06-07 | Voltage Control, Inc., A Montana Corporation | Digital voltage and phase monitor for AC power line |
US5412692A (en) * | 1992-07-27 | 1995-05-02 | Mitsumi Electric Co., Ltd. | Data slicer |
US5539772A (en) * | 1994-10-13 | 1996-07-23 | Westinghouse Electric Corporation | Apparatus and method for verifying performance of RF receiver |
US5649318A (en) * | 1995-03-24 | 1997-07-15 | Terrastar, Inc. | Apparatus for converting an analog c-band broadcast receiver into a system for simultaneously receiving analog and digital c-band broadcast television signals |
US5886546A (en) * | 1996-06-27 | 1999-03-23 | Lg Semicon Co., Ltd. | Current/voltage converter, sense amplifier and sensing method using same |
US5937004A (en) * | 1994-10-13 | 1999-08-10 | Fasulo, Ii; Albert Joseph | Apparatus and method for verifying performance of digital processing board of an RF receiver |
US5945878A (en) * | 1998-02-17 | 1999-08-31 | Motorola, Inc. | Single-ended to differential converter |
US6252633B1 (en) * | 1997-07-03 | 2001-06-26 | U.S. Philips Corporation | Television signal receiver |
US20040028149A1 (en) * | 2002-08-08 | 2004-02-12 | Krafft Stephen Edward | Programmable integrated DiSEqC transceiver |
US6693587B1 (en) * | 2003-01-10 | 2004-02-17 | Hughes Electronics Corporation | Antenna/feed alignment system for reception of multibeam DBS signals |
US20040042368A1 (en) * | 2002-08-30 | 2004-03-04 | Samsung Electronics Co., Ltd. | Data slicer and data slicing method for optical disc system |
US6714608B1 (en) * | 1998-01-27 | 2004-03-30 | Broadcom Corporation | Multi-mode variable rate digital satellite receiver |
US6791624B1 (en) * | 1999-10-19 | 2004-09-14 | Canon Kabushiki Kaisha | Television receiver image processing using display of different image quality adjusted images |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3109147C2 (en) | 1981-03-11 | 1984-12-13 | Philips Patentverwaltung Gmbh, 2000 Hamburg | Circuit arrangement for monitoring the state of a binary signal |
JPS63296418A (en) | 1987-05-28 | 1988-12-02 | Yagi Antenna Co Ltd | Satellite broadcast receiver |
JPH0693658B2 (en) * | 1987-09-09 | 1994-11-16 | 株式会社日立製作所 | Receiver for spatially propagating optical signal |
JPH07297872A (en) | 1994-04-28 | 1995-11-10 | Matsushita Electric Ind Co Ltd | Demodulator |
JPH0974555A (en) | 1995-09-06 | 1997-03-18 | Sharp Corp | Digital satellite broadcast receiver |
GB9606114D0 (en) | 1996-03-22 | 1996-05-22 | Digi Media Vision Ltd | Improvements in or relating to digital satellite receivers |
JPH104367A (en) | 1996-06-18 | 1998-01-06 | Dx Antenna Co Ltd | Satellite receiver of received polarized wave front voltage changeover system |
JPH1013276A (en) | 1996-06-27 | 1998-01-16 | Toshiba Corp | Satellite broadcast 2nd converter and satellite broadcast receiver |
JPH10190505A (en) | 1996-12-27 | 1998-07-21 | Maspro Denkoh Corp | Satellite broadcasting receiving device |
KR19990049717A (en) | 1997-12-15 | 1999-07-05 | 김영환 | LNB control apparatus and method using diesec |
JPH11261500A (en) * | 1998-03-10 | 1999-09-24 | Motorola Kk | Rssi circuit operatable at low voltage |
JP2000036847A (en) | 1998-07-17 | 2000-02-02 | Hitachi Ltd | Method for transmitting extended receiver start control information, and satellite digital broadcast receiver |
GB2347055A (en) | 1999-02-17 | 2000-08-23 | 3Com Corp | Network connections |
CN1169062C (en) | 1999-07-16 | 2004-09-29 | 汤姆森许可公司 | Method and apparatus for generating a control signal bitstream |
JP3653215B2 (en) | 1999-10-01 | 2005-05-25 | シャープ株式会社 | Satellite broadcast receiving system, and low noise block down converter and satellite broadcast receiver used in satellite broadcast receiving system |
JP3492964B2 (en) | 1999-12-14 | 2004-02-03 | シャープ株式会社 | Phase shifter and demodulator using the same |
US6414615B1 (en) | 2000-03-22 | 2002-07-02 | Raytheon Company | Excess delay compensation in a delta sigma modulator analog-to-digital converter |
JP2002076795A (en) | 2000-08-25 | 2002-03-15 | Sharp Corp | Amplifying circuit and satellite broadcast receiving set using it |
JP2006133869A (en) | 2004-11-02 | 2006-05-25 | Nec Electronics Corp | Cmos current mirror circuit and reference current/voltage circuit |
-
2005
- 2005-10-26 CN CN2005800370883A patent/CN101049023B/en not_active Expired - Fee Related
- 2005-10-26 JP JP2007540343A patent/JP4981677B2/en not_active Expired - Fee Related
- 2005-10-26 BR BRPI0516945-3A patent/BRPI0516945A/en not_active Application Discontinuation
- 2005-10-26 US US11/666,482 patent/US8433239B2/en active Active
- 2005-10-26 WO PCT/US2005/038506 patent/WO2006052450A1/en active Application Filing
- 2005-10-26 EP EP05823315A patent/EP1808021A1/en not_active Ceased
Patent Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4412186A (en) * | 1980-04-14 | 1983-10-25 | Tokyo Shibaura Denki Kabushiki Kaisha | Current mirror circuit |
US4961009A (en) * | 1988-06-29 | 1990-10-02 | Goldstar Semiconductor, Ltd. | Current-voltage converting circuit utilizing CMOS-type transistor |
US4942593A (en) * | 1989-03-16 | 1990-07-17 | Dallas Semiconductor Corporation | Telecommunications interface with improved jitter reporting |
US5289278A (en) * | 1991-02-21 | 1994-02-22 | Plessey Semiconductors Limited | Duo-binary and/or binary data slicer |
US5319514A (en) * | 1992-03-03 | 1994-06-07 | Voltage Control, Inc., A Montana Corporation | Digital voltage and phase monitor for AC power line |
US5412692A (en) * | 1992-07-27 | 1995-05-02 | Mitsumi Electric Co., Ltd. | Data slicer |
US5937004A (en) * | 1994-10-13 | 1999-08-10 | Fasulo, Ii; Albert Joseph | Apparatus and method for verifying performance of digital processing board of an RF receiver |
US5539772A (en) * | 1994-10-13 | 1996-07-23 | Westinghouse Electric Corporation | Apparatus and method for verifying performance of RF receiver |
US5649318A (en) * | 1995-03-24 | 1997-07-15 | Terrastar, Inc. | Apparatus for converting an analog c-band broadcast receiver into a system for simultaneously receiving analog and digital c-band broadcast television signals |
US5886546A (en) * | 1996-06-27 | 1999-03-23 | Lg Semicon Co., Ltd. | Current/voltage converter, sense amplifier and sensing method using same |
US6252633B1 (en) * | 1997-07-03 | 2001-06-26 | U.S. Philips Corporation | Television signal receiver |
US6714608B1 (en) * | 1998-01-27 | 2004-03-30 | Broadcom Corporation | Multi-mode variable rate digital satellite receiver |
US5945878A (en) * | 1998-02-17 | 1999-08-31 | Motorola, Inc. | Single-ended to differential converter |
US6791624B1 (en) * | 1999-10-19 | 2004-09-14 | Canon Kabushiki Kaisha | Television receiver image processing using display of different image quality adjusted images |
US20040028149A1 (en) * | 2002-08-08 | 2004-02-12 | Krafft Stephen Edward | Programmable integrated DiSEqC transceiver |
US20040042368A1 (en) * | 2002-08-30 | 2004-03-04 | Samsung Electronics Co., Ltd. | Data slicer and data slicing method for optical disc system |
US6693587B1 (en) * | 2003-01-10 | 2004-02-17 | Hughes Electronics Corporation | Antenna/feed alignment system for reception of multibeam DBS signals |
Non-Patent Citations (1)
Title |
---|
DJEMOUAI, A. et al: "Integrated ASK Demodulator Dedicated to Implantable Electronic Devices", IEEE, US. Vol. 1; 27 Dec. 2003, pages 80-83...submitted in PDF format. * |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070082610A1 (en) * | 2005-10-12 | 2007-04-12 | Kesse Ho | Dynamic current sharing in Ka/Ku LNB design |
US8515342B2 (en) * | 2005-10-12 | 2013-08-20 | The Directv Group, Inc. | Dynamic current sharing in KA/KU LNB design |
US20110151769A1 (en) * | 2008-09-26 | 2011-06-23 | John James Fitzpatrick | Method for controlling signal transmission for multiple devices |
US8903306B2 (en) * | 2008-09-26 | 2014-12-02 | Thomson Licensing | Method for controlling signal transmission for multiple devices |
US20150022183A1 (en) * | 2010-10-28 | 2015-01-22 | Infineon Technologies Austria Ag | Accessory Presence Detection |
US9835657B2 (en) * | 2010-10-28 | 2017-12-05 | Infineon Technologies Austria Ag | Accessory presence detection |
US20130051481A1 (en) * | 2011-08-30 | 2013-02-28 | Sony Corporation | Electric power-supply apparatus and receiving apparatus |
Also Published As
Publication number | Publication date |
---|---|
CN101049023A (en) | 2007-10-03 |
WO2006052450A1 (en) | 2006-05-18 |
JP2008519563A (en) | 2008-06-05 |
BRPI0516945A (en) | 2008-09-23 |
EP1808021A1 (en) | 2007-07-18 |
CN101049023B (en) | 2012-08-29 |
JP4981677B2 (en) | 2012-07-25 |
US8433239B2 (en) | 2013-04-30 |
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