JPH0974555A - Digital satellite broadcast receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of bits of a digital part for an AGC control, to relax the restriction on the nonlinearity of an AGC characteristic in a tuner part and to realize a front end part at low cost. SOLUTION: At the poststage of an AGC amplifier 57 or at the poststages of low-pass filters 62 and 63 for I signal or Q signal, the level detection part 81 of an analog system is provided. The output of the level detection part is inputted into a DC amplifier 82 to impart the voltage that the detection value of a digital level detection part 68 of a QPSK demodulation part 22 is converted into analog values by a D/A converter 70 as the reference voltage of the DC amplifier. The DC amplifier controls the gain of an AGC amplifier 57 so as to keep the signal amplifier of the QPSK demodulation part 22 constant.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital modulation (eg, QP) of digitally compressed video information and audio information.
SK modulation: Quadrature Phase Shift Keying) related to a satellite broadcasting receiver, which is particularly composed of a tuner section for receiving and selecting a 1 GHz band signal from an antenna (LNB) and a QPSK demodulation section. AGC
(Automatic Gain Control) system. Note that the QPSK modulation is also called four-phase modulation, and digital data "0" and "1" are collectively carried as a 2-bit symbol and transmitted corresponding to his four phases. Phase (0,0), π / 2 phase (0,1), π phase (1,1), and 3π / 2 phase (1,0) are transmitted. Is.

[0002]

2. Description of the Related Art As a television broadcasting system using satellites,
There are an analog FM system in which an analog video signal and an audio signal are FM-modulated, and a digital modulation system in which data after the analog video signal and the audio signal are digitized and compressed is digitally modulated by QPSK modulation and transmitted. Due to advances in semiconductor technology and digital image compression technology, more TV programs can be sent in the same frequency band in the digital modulation method than in the analog FM method, so satellite broadcasting of the digital modulation method is planned and implemented. There is. Also, CATV
Similarly, terrestrial broadcasting is also being considered for digitization.

First, the general structure of a digital satellite broadcast receiver will be described below with reference to the block diagram of FIG.

The internal circuit connected to the antenna 10 includes a front end portion 20, a core portion 30 and a back end portion 4.
It consists of three blocks of 0.

The front end section 20 is a tuner section 21,
The QPSK demodulation unit 22 and the error correction unit 23 are included. The tuner unit 21 is the LN of the antenna 10.
A signal of one channel is selected and amplified from a signal of 1 GHz band consisting of a plurality of channels from B (Low Noise Block Downconverter).

Next, the QPSK demodulator 22 extracts the digital data. At this time, the data transmission speed is about 40 Mbps to 60 Mbps, and includes video and audio of a plurality of programs of about 4 to 10, related data, and redundant data for error correction.

As a characteristic of satellite broadcasting, the signal from the satellite that reaches the antenna 10 is very small and is set to the minimum level required for reception. Therefore, the error correction unit 23
For this, an error correction technique called FEC (Forward Error Correction) is used.

The digital data taken out by the QPSK demodulation unit 22 has an error removed by the error correction unit 23, and there is almost no error (Quasi Error Free).
BER (Bit Error Rate) of 10 ^-10 to 10 ^-11 . Redundant data for error correction is removed from this signal, and it becomes a bit stream composed of a fixed-length frame called a transport stream, and becomes an output signal of the front end unit 20.

The core unit 30 includes a transport demultiplexer 31 and an on-screen display control 3
It is composed of 2 etc. The transport demultiplexer 31 decomposes the fixed-length transport stream input from the front end unit 20 and divides it into a video stream (data string), an audio stream, and other data. Also, one program included in the signal of one channel is selected. The on-screen display control 32 displays a menu for selecting a program or the like. The core unit 30 also includes a function of descrambling so that only the contractor can view it. The video stream and the audio stream are sent to the next back end unit 40.

The back end section 40 is also called a source decoding section, and is composed of an MPEG2 video decoder 41, an MPEG audio decoder 42, an NTSC encoder 43, an RF modulator 44 and the like. The back end unit 40 expands the digitally compressed video and audio data from the core unit 30 in the preceding stage, and converts the data into an analog television signal. In addition, MPEG (Moving Picture E)
xperts Group) is an international standard for decoding digitally compressed video and audio.

Next, the tuner section 21 and the QPSK demodulation section 2
2 will be described. The present invention includes a tuner section and a QPS
The present invention relates to an AGC system including a K demodulation unit.

FIG. 4 shows a block diagram of the tuner section and the QPSK demodulation section.

In FIG. 4, 51 is a preamplifier, 52 is a filter, 53 is a first mixer, 54 is a first local oscillator,
55 is a PPL circuit, 56 is a 480 MHz SAW filter, 57 is an AGC amplifier, 58 and 59 are IQ mixers, 6
0 is a 90-degree phase shifter, 61 is a second local oscillator, 62, 63
Is a low-pass filter. Also, 64 and 65 are A / D
A converter, 66 is a clock reproducing unit for reproducing a symbol clock, 67 is a carrier reproducing unit, 68 is a level detecting unit, 6
Reference numerals 9 and 70 are D / A converters.

The tuner section 21 selects only one channel of the signal from the LNB of the antenna 10 and converts it into an IF frequency. That is, the high-frequency signal is amplified by the preamplifier 51, noise is removed by the filter 52, and the first mixer 5
3, the first local oscillator 54 and the PLL circuit 55 convert to an IF frequency and select only one channel. The intermediate frequency signal passes through the SAW filter 56 and the level is adjusted by the AGC amplifier 57. The level-adjusted QPSK signal (baseband signal) is IQ
It is led to the mixers 58 and 59. The signal from the second local oscillator 61 is input to the 90-degree phase shifter 60, and the two signals having a phase difference of 90 degrees are input to the IQ mixers 58 and 59, respectively. The second local oscillator 61 is kept in the same phase as the carrier of the input IF signal by the function of the carrier reproducing unit 67 of the QPSK demodulating unit 22. The baseband signal is multiplied by the signal from the 90-degree phase shifter 60 in the IQ mixers 58 and 59, and the I signal and the Q signal (each of which is a color difference signal whose carrier signals are orthogonal to each other) are baseband signals. There is). The I signal and Q signal are the same as those on the transmitting side. However, since the absolute phase cannot be reproduced at this point in time, the waveform on the transmitting side is not strict, but this is corrected by a later circuit. The I signal and the Q signal pass through the low pass filters 62 and 63,
It is input to the A / D converters 64 and 65 of the QPSK demodulation unit 22 and A / D converted into a digital signal of about 6 bits. In FIG. 4, thick lines represent digital signals of a plurality of bits.
The digital signals of the I signal and the Q signal are guided to the clock reproducing unit 66, the carrier reproducing unit 67, and the level detecting unit 68, and their respective processes are performed. The level of the I signal or the Q signal detected by the level detection unit 68 is the D / A converter 7
The gain of the AGC amplifier 57 is controlled so that the I signal and the Q signal after being converted into an analog signal by A / D conversion by 0 maintain an optimum amplitude. Although not shown in FIG. 4, an RF attenuator may be used up to the first mixer 53 if necessary.

[0015]

The input level of the tuner section 21 is usually from -65 dBm to 1 channel per channel.
The range is 25 dBm and the dynamic range is 40 d.
B is necessary. Further, considering variations in gain of the tuner section and temperature changes, a dynamic range of at least 50 dB is required. If this is aimed to be controlled in 0.5 dB steps, 100 steps are required. Furthermore, considering the non-linearity of the AGC characteristic, a resolution of 8 bits or more is required. Incorporating a D / A converter of 8 bits or more into a digital IC on a single chip causes a cost increase, and attempts to suppress the non-linearity of the AGC characteristics (AGC control voltage vs. gain) of the tuner unit within a certain range. Then, this also causes a cost increase. Especially when combined with an RF attenuator, the AGC control circuit becomes complicated.

A further supplement will be given. The A / D converters 64 and 65 for the I signal and the Q signal are sampled in a state where the conversion rate is twice the normal symbol rate. Therefore, the sampling rate is 40 to 60MHz, which means that it becomes a flash type A / D converter.
The number of bits to be converted greatly affects the chip area and thus the cost. If the number of bits is increased by 1 bit, the chip area will be doubled. Therefore, it is necessary to keep the number of bits as small as possible, and normally 4 to 6 bits are used. Here, there is a need to precisely control the AGC.

[0017]

The present invention provides a satellite broadcast receiver for receiving digital satellite broadcasts,
A DC that amplifies the output signal of the analog level detection section by providing an analog level detection section in the tuner section
An amplifier is provided, and QPS is used as a reference voltage for the DC amplifier.
In order to keep the signal amplitude of the QPSK demodulator constant by using the output value of the digital level detector in the K demodulator,
The feature is that the gain of the AGC amplifier is controlled by the output of the C amplifier. That is, an analog type level detection unit is also provided in the tuner unit, and feedback is performed inside the tuner unit. Further, the output of the digital level detector is applied to the reference voltage of the feedback loop.

A feedback loop composed of an analog level detector covers a dynamic range of 50 dB required as a receiver. Then, variations due to the analog method, temperature fluctuations, and fluctuations due to the factors of the circuits after the level detection unit are corrected by the output of the digital side level detection unit.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a digital satellite broadcast receiver according to the present invention will be described below in detail with reference to the drawings.

[First Embodiment] FIG. 1 is a block diagram showing an electrical configuration of a digital satellite broadcast receiver according to a first embodiment. In FIG. 1, the same reference numerals as those shown in FIG. 4 according to the related art represent the elements having the same functions, and thus detailed description thereof will be omitted here. In the first embodiment, the analog level detection unit 81 that detects the level of the IF signal output from the AGC amplifier 57 is provided as an AG.
A DC amplifier 8 which is connected to the output side of the C amplifier 57 and which amplifies the detection signal of the level detecting section 81 by direct current.
2 are provided. The output of the DC amplifier 82 is connected to the gain control terminal of the AGC amplifier 57 to control the gain of the AGC amplifier 57, and the AGC amplifier 57, the level detection unit 81, and the DC amplifier 82 form a feedback loop.
As a result, the dynamic range of 50 dB required for a digital satellite broadcast receiver is secured.

The DC amplifier 82 includes a QPSK demodulation unit 22.
The detection value of the digital level detector 68 in
The reference voltage converted to analog by the A / A converter 70 is input, and by setting the gain of the DC amplifier 82 sufficiently high, the output voltage of the analog level detection unit 81 becomes the reference. The gain of the AGC amplifier 57 is controlled so as to be equal to the voltage. As a result, fluctuations due to the factors of the circuits after the analog level detector 81 are corrected.

In this case, the digital level detecting section 68 in the QPSK demodulating section 22 corrects only variations and temperature variations from the analog level detecting section 81 to the A / D converters 64 and 65 on the tuner section 21 side. Therefore, the resolution may be coarser than that of the prior art, and the non-linearity of the AGC characteristic (AGC control voltage vs. gain) of the tuner section 21 does not matter. Therefore, it is possible to reduce the number of bits of the digital section for AGC control, that is, the A / D converters 64 and 65 and the D / A converter 70, and the tuner section 21 uses the AGC.
The restrictions on the nonlinearity of the characteristic can be relaxed.
As described above, the chip area can be reduced, the configuration of the AGC control circuit can be simplified, and the front end section 20 with low cost can be realized.

[Second Embodiment] FIG. 2 is a block diagram showing an electrical configuration of a digital satellite broadcast receiver according to a second embodiment. In FIG. 2, the same reference numerals as those shown in FIG. 4 according to the related art represent the elements having the same functions, and therefore detailed description thereof will be omitted here. In the second embodiment, the low-pass filter 63 in the tuner unit 21.
An analog type level detection unit 91 for detecting the level of the Q signal output from is provided. Further, a DC amplifier 92 for DC-amplifying the detection signal of the level detecting section 91.
Is provided. The output of the DC amplifier 92 is connected to the gain control terminal of the AGC amplifier 57 to control the gain of the AGC amplifier 57, and the AGC amplifier 57 and the IQ mixer 59 are connected.
The low pass filter 63, the level detector 91 and the DC amplifier 92 form a feedback loop. As a result, the dynamic range of 50 dB required for a digital satellite broadcast receiver is secured. Similar to the first embodiment,
In the DC amplifier 92, the detected value of the digital level detecting section 68 in the QPSK demodulating section 22 is transferred to the D / A converter 7.
The reference voltage converted to analog by 0 is input, and by setting the gain of the DC amplifier 92 sufficiently high, the output voltage of the analog level detection unit 91 becomes equal to the reference voltage. Like AGC
The gain of the amplifier 57 is controlled. As a result, fluctuations due to the factors of the circuits after the analog level detection unit 91 are corrected. Note that, basically, since the Q signal and the I signal have the same amplitude, the I signal may be used instead of the Q signal for level detection. In that case, the level detection unit 91 of the low pass filter 62 is used. Connect to the output side.

With this configuration, QPSK
Digital level detector 68 in demodulator 22
Since it only corrects the variations and temperature fluctuations of the analog level detector 91 and the A / D converters 64 and 65 on the tuner section 21 side, the comparison with the first embodiment is, of course, compared with the first embodiment. However, the resolution may be coarser, and the non-linearity of the AGC characteristic (AGC control voltage vs. gain) of the tuner 21 does not matter. Therefore, it is possible to reduce the number of bits of the digital part for AGC control, that is, the A / D converters 64 and 65 and the D / A converter 70.
The restrictions on the non-linearity of the C characteristic can be relaxed. As described above, the chip area can be reduced, the configuration of the AGC control circuit can be simplified, and the front end section 20 with low cost can be realized.

The level detecting section 91 may be provided anywhere as long as it is a base band section. For example, the IQ mixer 58,
You may provide in the latter part of 59. Further, in any of the first and second embodiments, an RF attenuator may be inserted between the input of the tuner section 21 and the first mixer 53, and the same effect is obtained in this case as well.

[0026]

According to the present invention, it is possible to reduce the number of bits in the digital section for AGC control, and relax the restriction on the nonlinearity of the AGC characteristic (AGC control voltage vs. gain) in the tuner section. Therefore, it is possible to realize a low-cost front end part.

[Brief description of drawings]

FIG. 1 is a block diagram showing an electrical configuration of a tuner unit and a QPSK demodulation unit of a digital satellite broadcast receiver according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing an electrical configuration of a tuner section and a QPSK demodulation section of a digital satellite broadcast receiver according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a general configuration of a digital satellite broadcast receiver.

FIG. 4 is a block diagram showing an electrical configuration of a tuner unit and a QPSK demodulation unit of a conventional digital satellite broadcast receiver.

[Explanation of symbols]

 53 ... 1st mixer 54 ... 1st local oscillator 55 ... PLL circuit 56 ... SAW filter 57 ... AGC amplifier 58 ... IQ mixer 59 ... IQ mixer 60 ... 90 degree phase shifter 61 ... 2 local oscillator 62 ... Low-pass filter (for I signal) 63 ... Low-pass filter (for Q signal) 64 ... A / D converter (for I signal) 65 ... A / D converter (for Q signal) 66 ...... Clock reproducing unit 67 …… Carrier reproducing unit 68 …… Digital type level detecting unit 69 …… D / A converter 70 …… D / A converter 81 …… Analog type level detecting unit 82 …… DC amplifier 91 ... Analog level detector 92 ... DC amplifier

Claims (3)

[Claims] 1. A satellite broadcast receiver for receiving digital satellite broadcasts, wherein a tuner is provided with an analog level detector, and a DC amplifier for amplifying an output signal of the analog level detector is provided. The output of the DC amplifier is used to maintain the signal amplitude of the QPSK demodulator constant by using the output value of the digital level detector in the QPSK demodulator as the reference voltage of the DC amplifier.
A digital satellite broadcast receiver characterized by being configured to control the gain of a C amplifier. 2. The digital satellite broadcast receiver according to claim 1, wherein an analog level detector is provided after the AGC amplifier. 3. The digital satellite broadcasting receiver according to claim 1, wherein an analog level detecting section is provided in a baseband section for outputting an I signal or a Q signal.