US20070257828A1 - Digital-to-analog converter and method thereof - Google Patents
Digital-to-analog converter and method thereof Download PDFInfo
- Publication number
- US20070257828A1 US20070257828A1 US11/309,100 US30910006A US2007257828A1 US 20070257828 A1 US20070257828 A1 US 20070257828A1 US 30910006 A US30910006 A US 30910006A US 2007257828 A1 US2007257828 A1 US 2007257828A1
- Authority
- US
- United States
- Prior art keywords
- signal
- terminal
- output
- switch
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/76—Simultaneous conversion using switching tree
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/76—Simultaneous conversion using switching tree
- H03M1/765—Simultaneous conversion using switching tree using a single level of switches which are controlled by unary decoded digital signals
Definitions
- the present invention relates to a digital-to-analog converter (DAC), and more particularly to a DAC which phase by phase outputs the digital signal according to N timing signals.
- DAC digital-to-analog converter
- a source driver is used to provide the analog signal required for driving pixels.
- every output terminal of the source driver is electrically connected to a conventional DAC as shown in FIG. 1 .
- a conventional DAC (a DAC with 3-bits resolution is taken as exemplary herein) includes three switch units 101 ⁇ 103 .
- the switch units 101 ⁇ 103 are respectively controlled by bits b[ 3 ] ⁇ b[ 1 ], wherein the switches in each switch unit are allocated in couples (for example, SW 17 and SW 18 ; SW 13 and SW 14 ) and the coupled switches are electrically connected to a same switch.
- the coupled switches are controlled by a bit and the phase-inverted bit of the bit, respectively (for example, the switches SW 18 and SW 17 are respectively controlled by the bit b[ 1 ] and the phase-inverted bit thereof /b[ 1 ]). Therefore, the reference voltages V 1 ⁇ V 8 to be input to the conventional DAC are sequentially delivered through the switching operations of the switch units from 101 to 103 under the controls of the digital signals b[ 3 ] ⁇ b[ 1 ]. In this way, the switch unit 101 selects half of the reference voltages from the reference voltages V 1 ⁇ V 8 for outputting and delivering to the switch unit 102 .
- the received four reference voltages (for example, V 1 , V 3 , V 5 and V 7 ) are selected into two reference voltages for outputting to the switch unit 101 .
- the switch unit 101 would, through switching, select a reference voltage as the output analog signal V out1 of the conventional DAC.
- a conventional DAC employs multiple switches to implement the switching on the reference voltages.
- Such a scheme requires a huge number of switches for numerous DACs to be disposed in a source driving circuit, which indicates an excessive cost a TFT LCD needs.
- the conventional DAC 210 is formed by a conventional DAC 110 and switches SW 21 and SW 22 .
- the switches SW 21 and SW 22 are respectively coupled with the output terminal of the conventional DAC 110 to further create two signal output terminals P out21 and P out22 controlled by timing switching signals SW CLK21 and SW CLK22 .
- every two output terminals of a source driver share a same DAC, which is advantageous to downsize the chip area.
- the analog signals are output phase by phase as shown in FIG. 3 , which can be achieved by using two non-overlapped timing switching signals SW CLK21 and SW CLK22 .
- the above-mentioned conventional DAC 210 functions to downsize a chip area, however, it only allows a half of the output terminals of a source driver being able to drive pixels at any time under the ‘phase by phase outputting’ mode. Under the situation, the available charging time each output terminal can provide to the pixels needs to be shortened, and the available charging time is reduced proportionally with the number of the DACs the output terminals share.
- an extra switch is required to be disposed (as shown by the arrows 104 and 201 in FIG. 1 and FIG. 2 ).
- the conventional DAC 210 is forced to adopt the switches (SW 21 and SW 22 ) with a larger layout area in order to maintain the original performance of the source driver.
- An object of the present invention is to provide a DAC using a control unit controlled by multiple timing signals to reduce the number of the switches inside the circuit and the number of the reference voltage lines, which further lowers the cost of the source driving circuit.
- the present invention no longer requires increasing the switching paths of the switches; furthermore, the present invention also enables the source driver to drive every output terminal at any time.
- Another object of the present invention is to provide a digital-to-analog converting method, where the timings of multiple timing signals are used to make the analog signals output phase by phase and to achieve the advantage of downsizing chip area.
- the present invention provides a DAC, which includes a reference voltage unit, a control unit and a decoding unit.
- the reference voltage unit includes 2 M output terminals VR k .
- the control unit coupled with the 2 M output terminals of the reference voltage unit delivers at least a reference voltage among the reference voltages output from the above-mentioned output terminals VR k to the 2 M output terminals of the control unit according to the N timing signals and the N bits of the digital signal, respectively.
- the decoding unit selects a signal among the signals come from the 2 M output terminals of the control unit as an analog signal for output according to M bits of the digital signal.
- the converter is able to select a reference voltage from the received 2 M+N reference voltages V q (at most) as an analog signal for output according to the digital signal having (M+N) bits, where N, M are integers larger than zero and 1 ⁇ q ⁇ 2 M+N , 1 ⁇ k ⁇ 2 M .
- each output terminal respectively outputs reference voltages V ((k ⁇ 1) ⁇ 2 ⁇ N)+1 ⁇ V k ⁇ 2 ⁇ N in 2 N time phases of an output period, where V 1 ⁇ V 2 ⁇ . . . ⁇ V 2 ⁇ (M+N) .
- each output terminal respectively outputs reference voltages V ((k ⁇ 1) ⁇ 2 ⁇ N)+1 ⁇ V k ⁇ 2 ⁇ N in 2 N time phases of an output period, where V 1 ⁇ V 2 ⁇ . . . ⁇ V 2 ⁇ (M+N) .
- the control unit receives b[ 1 ] ⁇ b[N] of the digital signal, while the decoding unit receives b[N+1] ⁇ b[M+N] of the digital signal.
- the control unit includes a control circuit and a switching circuit.
- the control circuit is used for outputting N control signals according to the N timing signals and the bits b[ 1 ] ⁇ b[N].
- the switching circuit electrically connected to the control circuit phase by phase outputs the reference voltages V ((k ⁇ 1) ⁇ 2 ⁇ N)+1 ⁇ V k ⁇ 2 ⁇ N provided by the output terminals VR k according to the control result of the N control signals on the circuit itself.
- the present invention provides a digital-to-analog converting method.
- the method is to provide 2 M voltages VR k in an output period by receiving a digital signal with (M+N)-bits and setting the levels of 2 M+N reference voltages V q .
- the levels of the voltage VR k in 2 N phases are V ((k ⁇ 1) ⁇ 2 ⁇ N)+1 ⁇ V k ⁇ 2 ⁇ N , respectively.
- one of the above-described 2 M voltages VR k is selected, and further at lease a level among the levels V ((k ⁇ 1) ⁇ 2 ⁇ N)+1 ⁇ V k ⁇ 2 ⁇ N of the selected voltage VR k is selected as the analog signal, so as to achieve the objective of digital-to-analog conversion.
- N, M are integers larger than zero
- V q represents the q th reference voltage and 1 ⁇ q ⁇ 2 M+N , a ⁇ k ⁇ 2 M .
- the present invention uses N timing signals to respectively control the control unit and the reference voltage unit, so that multiple reference voltages are able to share an output, which contributes to downsize the chip area required by the reference voltage lines and the decoding unit.
- the present invention not only achieves the objective of lowering the chip area, but also enables the source driver to drive every output terminal at any time.
- FIG. 1 is a detailed circuit drawing of a conventional digital-to-analog converter (DAC).
- DAC digital-to-analog converter
- FIG. 2 is a detailed circuit drawing of another conventional DAC.
- FIG. 3 illustrates the analog signal timing diagrams for the DAC in FIG. 2 .
- FIG. 4 is a detailed framework drawing of a DAC according to an embodiment of the present invention.
- FIG. 5 is a detailed circuit drawing of a 3-bits DAC according to an embodiment of the present invention.
- FIGS. 6A and 6B are analog signal timing diagrams for the DAC in FIG. 5 .
- FIG. 7 is another analog signal timing diagram for the DAC in FIG. 5 .
- FIG. 8 is a detailed circuit drawing of another 3-bits DAC according to an embodiment of the present invention.
- FIG. 9 is an analog signal timing diagram for the DAC in FIG. 8 .
- FIG. 10 is a detailed circuit drawing of another 3-bits DAC according to an embodiment of the present invention.
- FIGS. 11A and 11B are analog signal timing diagrams for the DAC in FIG. 10 .
- FIGS. 12A and 12B are another set of the analog signal timing diagrams for the DAC in FIG. 10 .
- FIG. 13 is a detailed drawing of a control circuit according to an embodiment of the present invention.
- FIG. 14 is a detailed framework drawing of another DAC according to an embodiment of the present invention.
- FIG. 15 is a detailed circuit drawing of a 3-bits DAC according to the embodiment shown in FIG. 14 .
- FIG. 16 is an analog signal timing diagram of the DAC of FIG. 15 .
- FIG. 4 is a detailed framework drawing of a DAC according to an embodiment of the present invention.
- the DAC receiving a digital signal with (M+N) bits of b[M+N] ⁇ b[ 1 ] includes a reference voltage unit 401 , a control unit 402 and a decoding unit 403 , where N and M are integers larger than zero.
- the reference voltage unit 401 includes 2 M output terminals VR 1 ⁇ VR 2 ⁇ M .
- the control unit 402 is electrically connected to the 2 M output terminals of the reference voltage unit 401 .
- the decoding unit 403 is electrically connected to the 2 M output terminals of the control unit 402 .
- the reference voltage unit 401 outputs the reference voltages V 1 ⁇ V 2 ⁇ (M+N) through the output terminals VR 1 ⁇ VR 2 ⁇ M according to the timing of the N timing signals, wherein VR k represents the k th output terminal and provides the reference voltages V ((k ⁇ 1) ⁇ 2 ⁇ N)+1 ⁇ V k ⁇ 2 ⁇ N , where 1 ⁇ k ⁇ 2 M .
- the control unit 402 delivers one of the reference voltages V ((k ⁇ 1) ⁇ 2 ⁇ N)+1 ⁇ V k ⁇ 2 ⁇ N output from each of the above-mentioned output terminals VR k to the 2 M output terminals of the control unit 402 according to the above-mentioned N timing signals and the N bits b[N] ⁇ b[ 1 ] of the digital signal.
- the decoding unit 403 selects one of the output signals come from the 2 M output terminals of the control unit 402 as an analog signal for output according to the M bits b[M+N] ⁇ b[N+1] and the bits /b[M+N] ⁇ /b[N+1].
- the bits /b[M+N] ⁇ /b[N+1] are logic-levels inverted to the bits b[M+N] ⁇ b[N+1], respectively.
- the reference voltage V 1 has the lowest level
- the reference voltage V 2 has a level next to the lowest
- the rest can be analogized.
- the reference voltage V 2 ⁇ (M+N) has the highest level, i.e., V 1 ⁇ V 2 ⁇ . . . ⁇ V 2 ⁇ (M+N) .
- the bit b[ 1 ] is the least significant bit (LSB) of the digital signal
- bit b[M+N] is the most significant bit (MSB) of the digital signal.
- anyone skilled in the art is able to re-design the levels of the reference voltages V 1 ⁇ V 2 ⁇ (M+N) into V 1 ⁇ V 2 ⁇ . . . ⁇ V 2 ⁇ (M+N) to fit the different application requirements.
- the control unit 402 of the embodiment in FIG. 4 includes a control circuit 410 and a switching circuit 420 .
- the switching circuit 420 includes N switching units UA 1 ⁇ UA N and each of the switching units UA 1 ⁇ UA N includes 2 M switches.
- the second terminal of the switch SWA(1;1) is coupled with the first terminal of the switch SWA(2;1); the second terminal of the switch SWA(1;2) is coupled with the first terminal of the switch SWA(2;2); and the second terminal of the switch SWA(N;1) is coupled with the output terminal VR 0 of the reference voltage unit 401 .
- the second terminal of the switch SWA(s;k) is coupled with the first terminal of the switch SWA(s+1;k), while the second terminal of the switch SWA(N;k) is coupled with the output terminal VR k of the reference voltage unit 401 , where SWA(s;k) indicates the k th switch of the s th switching unit UA S , 1 ⁇ s ⁇ N.
- the control circuit 410 outputs N control signals C 1 ⁇ C N to the switching circuit 420 according to the N timing signals and the N bits b[ 1 ] ⁇ b[N].
- each switch in the switching circuit 420 decides on/off status thereof according to the control signals C 1 ⁇ C N , respectively, so that one of the reference voltages V 1 ⁇ V 2 ⁇ (M+N) is allowed to be output to the decoding unit 403 .
- control terminals of the switches SWA(1;1) ⁇ SWA(1;2 M ) receive the control signal C 1
- the control terminals of the switches SWA(2;1) ⁇ SWA(2;2 M ) receive the control signal C 2
- the control terminal of the switch SWA(t;r) receives the control signal C t , 1 ⁇ t ⁇ N.
- the decoding unit 403 of the embodiment in FIG. 4 includes M switch units UB 1 ⁇ UB M .
- the switch unit UB 1 includes two switches SWB(1;1) and SWB(1;2).
- the switch unit UB 2 includes four (2 2 ) switches SWB(2;1) ⁇ SWB(2;4).
- the i th switch unit UB i includes 2 i switches SWB(i;k), wherein SWB(i;k) represents the k th switch of the i th switch unit Ub i , and 1 ⁇ i ⁇ M.
- the second terminal of the switch SWB(1;1) is electrically connected to the first terminals of the switches SWB(2;1) and SWB(2;2); the second terminal of the switch SWB(1;2) is electrically connected to the first terminals of the switches SWB(2;3) and SWB(2;4); the control terminal of the switch SWB(1;1) receives the bit b[M+N], while the control terminal of the switch SWB(1;2) receives the bit /b[M+N].
- the second terminal of the switch SWB(j;k) is electrically connected to the first terminals of the switches SWB(j+1;2k ⁇ 1) and SWB(j+1;2k) and the second terminal of the switch SWB(M;k) is coupled with the switching unit 420 .
- the control terminal of the switch SWB(i;2g ⁇ 1) receives the bit b[M+N+1 ⁇ i], while the control terminal of the switch SWB(i;2g) receives the bit /b[M+N+1 ⁇ i].
- the logic-level of the bit /b[i] is inverted to bit b[i], 1 ⁇ j ⁇ (M ⁇ 1) and the g value range is: 1 ⁇ g ⁇ 2 i ⁇ 1 .
- the decoding unit 403 has the similar working principle and the architecture to the conventional DAC.
- the switches in every switch unit of UB 1 ⁇ UB M are allocated in couples (for example, SWB(2;1) and SWB(2;2) form a couple)
- the switches of a couple are electrically connected to a same switch (for example, SWB(1;1)) and the switches in a couple are respectively controlled by a bit and the phase-inverted bit of the bit (for example, SWB(2;1) and SWB(2;2) are respectively controlled by the bit b[M+N ⁇ 1] and the phase-inverted bit /b[M+N ⁇ 1])
- one of the signals provided by the output terminals 2 M of the control unit 402 would be selected by the decoding unit 403 after the sequentially switching operations of the switch units UB 1 ⁇ UB M as an analog signal for output.
- an embodiment of 3-bits DAC is taken as exemplary.
- the control unit 402 receives one bit b[ 1 ] of the digital signal
- the decoding unit 403 receives two bits b[ 2 ] and b[ 3 ] of the digital signal.
- the control circuit 410 of the control unit 402 is formed by an NAND-gate 501 .
- the switching circuit 420 includes a switching unit UA 1 formed by 2 2 switches SWA(1;1) ⁇ SWA(1;4).
- the decoding unit 403 includes switch units UB 1 and UB 2 .
- the switch unit UB 1 includes switches SWB(1;1) and SWB(1;2), while the switch unit UB 2 includes switches SWB(2;1) ⁇ SWB(2;4),
- the first terminal of the NAND-gate 501 is used for receiving the inverted signal /b[ 1 ] of the bit b[ 1 ], while the second terminal thereof receives a timing signal CLK 51 and outputs a control signal C 1 according to the received signal.
- the wiring relationships of the switches SWA(1;1) ⁇ SWA(1;4), the switches SWB(1;1) and SWB(1;2), and the switches SWB(2;1) ⁇ SWB(2;4) can be obtained by a relationship derived from the embodiment in FIG. 4 , and the detail is omitted to describe herein.
- the mode ‘output phase by phase’ is to be defined first.
- the so-called ‘output phase by phase’ mode means that the DAC outputs the analog signal by 2 N phases according to the number N of the bits received by the control unit 402 .
- the analog signal is one of V 1 , V 3 , V 5 and V 7 (for example, V 1 )
- the analog signal would be charged/discharged to a predetermined level (for example, V 1 ) in the first phase and hold the level (for example, V 1 ) in the second phase.
- the analog signal is one of V 2 , V 4 , V 6 and V 8 (for example, V 2 )
- the analog signal would be charged/discharged to one of V 1 , V 3 , V 5 and V 7 (for example, V 1 ) in the first phase and be re-charged to a predetermined level (for example, V 2 ) in the second phase.
- the reference voltage unit 401 represented by a block in FIG. 5 is omitted for simplicity. Instead, the reference voltage unit 401 respectively outputs the reference voltages V 1 ⁇ V 8 through the output terminals VR 1 ⁇ VR 4 according to a timing signal CLK 51 . As shown in FIG. 5 , the reference voltage unit 401 sends out the reference voltages V 1 , V 3 , V 5 and V 7 in the first phase T 1 and sends out the reference voltages V 2 , V 4 , V 6 and V 8 in the second phase T 2 according to the timing signal CLK 51 .
- the reference voltages V 1 ⁇ V 8 are allocated in couples and the two voltages of a couple are provided by an output terminal of VR 1 ⁇ VR 4 (for example, V 1 and V 2 are provided by the output terminal VR 1 ).
- the control circuit 410 in the first phase T 1 outputs a control signal C 1 with a high-level (logic-1) in response to the low-level (logic-0) of the timing signal CLK 51 which makes the NAND-gate 501 ignore the phase-inverted signal /b[ 1 ] of the bit b[ 1 ].
- the switches SWA(1;1) ⁇ SWA(1;4) in the switching unit 420 hold the on-state in the first phase T 1 according to the control signal C 1 , so as to output the reference voltages V 1 , V 3 , V 5 and V 7 to the four output terminals of the control unit 402 , respectively.
- FIGS. 1-10 The switches SWA(1;1) ⁇ SWA(1;4) in the switching unit 420 hold the on-state in the first phase T 1 according to the control signal C 1 , so as to output the reference voltages V 1 , V 3 , V 5 and V 7 to the four output terminals of the control unit 402 , respectively.
- the decoding unit 403 would select one of signals provided by the four output terminals of the control unit 402 according to the bits b[ 2 ], b[ 3 ], /b[ 2 ] and /b[ 3 ], so that the analog signal is charged/discharged to one of the reference voltages V 1 , V 3 , V 5 and V 7 (for example, V 1 ) in the first phase T 1 .
- the control circuit 410 makes the control signal C 1 output from the NAND-gate 501 the same as the bit b[ 1 ] in response to the high-level (logic-1) of the timing signal CLK 51 .
- the bit b[ 1 ] is the high-level (logic-1), i.e. the predetermined output level of the analog signal is one of V 2 , V 4 , V 6 and V 8 (for example, V 2 )
- the control signal C 1 would turn on the switches SWA(1;1) ⁇ SWA(1;4) in the switching unit 420 , so that the reference voltages V 2 , V 4 , V 6 and V 8 are respectively output to the four output terminals of the control unit 402 .
- the decoding unit 403 is able to make the analog signal charge to a predetermined output level (for example, V 2 ) in the second phase T 2 according to the bits b[ 2 ], b[ 3 ], /b[ 2 ] and /b[ 3 ].
- a predetermined output level for example, V 2
- the bit b[ 1 ] is the low-level (logic-0), i.e.
- the predetermined output level of the analog signal is one of V 1 , V 3 , V 5 and V 7 (for example, V 1 )
- the switches SWA(1;1) ⁇ SWA(1;4) in the switching unit 420 would be off under the control of the control signal C 1 , which further makes the output terminal of the decoding unit 403 in floating-state and the analog signal in the second phase T 2 , and accordingly hold the level obtained in the first phase T 1 (for example, V 1 ).
- the analog signal can be charged/discharged phase by phase for more effectively utilizing time.
- the scheme is shown by FIG. 7 where the charge time of the analog signal in the second phase T 2 is far less than the charge time in the first phase T 1 due to a minor difference between two consecutive reference voltages (for example, difference between V 1 and V 2 ). If the DAC receives a 3-bits digital signal, sequentially 000-111-000, the output analog signal during the phase-by-phase charging period has a timing distribution as shown in FIG. 7 where a reduced time ratio corresponding to the second phase T 2 suggests a more effectively utilization of the timing signal CLK 51 .
- control circuit 410 in the embodiment of FIG. 5 can adopt another design as well.
- the control circuit 410 in FIG. 5 is formed by an OR-gate 801 .
- the first terminal and the second terminal of the OR-gate 801 respectively receive the bit b[ 1 ] and the timing signal CLK 51 , and the OR-gate 801 outputs a control signal C 1 to the control terminals of the switches SWA(1;1) ⁇ SWA(1;4).
- the coupling relationships of the switching circuit 420 , the decoding unit 403 and the output timing and the routed output terminals of the reference voltages V 1 ⁇ V 8 are the same as FIG. 5 , so the details are omitted to describe herein.
- control circuit 410 in spite of the modification of the control circuit 410 , as long as the control circuit 410 , as FIG. 5 , is able to output a control signal C 1 with a high-level (logic-1) to the switching unit 420 in the first phase T 1 and the control signal C 1 output from the control circuit 410 is equal to the bit b[ 1 ] in the second phase T 2 , the working principle described by the embodiment in FIG. 4 is still valid.
- the present embodiment utilizes a timing signal CLK 81 holding a high-level (logic-1) in the first phase T 1 to enable the control circuit 410 to output a control signal C 1 with a high-level (logic-1) to the switching unit 420 and makes the timing signal CLK 81 hold a low-level (logic-0), so that the control signal output from the OR-gate 801 can be equal to the bit b[ 1 ].
- the analog signal is able to be output phase by phase as shown in FIGS. 6A and 6B .
- the analog signal can be charged/discharged phase by phase for more effectively utilizing time, as the embodiment in FIG. 5 .
- the DAC receives a 3-bits digital signal, sequentially 000-111-000, the time ratio corresponding to the second phase T 2 is reduced as in FIG. 7 , a more effectively utilization of the duty cycle of the timing signal CLK 51 is expected.
- the switching circuit 420 includes two switching units UA 1 and UA 2 , while the switching units UA 1 and UA 2 respectively include switches SWA(1;1) and SWA(1;2) and switches SWA(2;1) and SWA(2;2).
- the decoding unit 403 is formed by a switch unit UB 1 , while the switch unit UB 1 includes switches SWB(1;1) and SWB(1;2).
- the coupling relationships of the switches SWA(1;1), SWA(1;2), SWA(2;1) and SWA(2;2) in the control circuit 410 and the switching circuit 420 and the switches SWB(1;1) and SWB(1;2) in the decoding unit 403 follow the relationship derived in FIG. 4 , so the detail is omitted to describe herein.
- the analog signal has various output distributions with multi-phases.
- One of the timings in ‘output phase by phase’ mode is shown by FIGS. 11A and 11B , wherein if the predetermined output level of the analog signal is the reference voltage V 3 during the output course formed by four phases T 1 ⁇ T 4 , the analog signal can be charged to the reference voltage V 1 in the first phase T 1 .
- the analog signal holds the reference voltage V 1 .
- the analog signal is recharged to the reference voltage V 3 , and in the fourth phase T 4 the analog signal holds the predetermined level, the reference voltage V 3 .
- the output course of the analog signal with a final level of the reference voltage V 3 can be in this way.
- the analog signal is charged to the reference voltage V 1 in the first phase T 1 .
- the analog signal is recharged to the reference voltage V 2 .
- the analog signal is recharged to the reference voltage V 3
- the fourth phase T 4 holds the predetermined level, the reference voltage V 3 .
- FIGS. 12A and 12B Another variation of the phase-by-phase output timing is shown by FIGS. 12A and 12B , where after the analog signal is charged to the predetermined level, the analog signal in thereafter phase holds the level of the previous phase.
- the predetermined level of an analog signal is the reference voltage V 3
- the analog signal is charged repeatedly phase by phase, from the first phase to the third phase, to the final level of the reference voltage V 3 , followed by holding the analog signal in the reference voltage V 3 in the fourth phase. Therefore, in comparison with FIGS. 11A and 11B , the ‘output phase by phase’ mode shown by FIGS. 12A and 12B can be covered by the scheme of FIGS. 11A and 11B .
- FIG. 13 a control circuit 410 compliant with the embodiment of FIG. 10 is given by FIG. 13 .
- the control circuit 410 includes NAND-gates 1305 ⁇ 1307 and XOR-gates 1308 and 1309 .
- the first terminal of the NAND-gate 1305 receives the phase-inverted signal /CLK 101 of the timing signal CLK 101 , while the second terminal thereof receives the phase-inverted signal /CLK 102 of the timing signal CLK 102 .
- the first terminal of the XOR-gate 1308 receives the phase-inverted signal /CLK 102 of the timing signal CLK 102 , while the second terminal thereof receives the phase-inverted signal /b[ 1 ] of the bit b[ 1 ].
- the first terminal and the second terminal of the NAND-gate 1306 are electrically connected to the output terminals of the NAND-gate 1305 and the XOR-gate 1308 , respectively.
- the first terminal and the second terminal of the NAND-gate 1307 are electrically connected to the output terminals of the NAND-gate 1305 and the XOR-gate 1309 , respectively.
- the reference voltages V 1 ⁇ V 8 output from the reference voltage unit 401 are divided into two sets of four reference voltages according to the architecture of the system and each set of the four reference voltages is provided by an output terminal (for example, V 1 ⁇ V 4 are provided by the output terminal VR 0 ).
- the reference voltages V 1 and V 5 among the reference voltages V 1 ⁇ V 8 are sent out in the first phase T 1 ; the reference voltages V 2 and V 6 are sent out in the first phase T 2 , and the rest can be analogized as shown in FIG. 10 .
- the NAND-gate 1305 outputs a low-level (logic-0) in the first phase where the timing signals CLK 101 and CLK 102 take a low-level (logic-0).
- the NAND-gates 1306 and 1307 output the control signals C 1 and C 2 with high-level (logic-1) to turn on the switches SWA(1;1), SWA(1;2), SWA(2;1) and SWA(2;2) in the control unit 420 , so as to respectively deliver the reference voltages V 1 and V 5 to the two output terminals of the control unit 402 .
- the decoding unit 403 charges the analog signal to one of the levels of the reference voltages V 1 and V 5 according to the bits b[ 3 ] and /b[ 3 ].
- the timing signals CLK 101 and CLK 102 respectively take a high-level (logic-1) and a low-level (logic-0) and the NAND-gate 1305 outputs a high-level (logic-1), which makes the control signals C 2 and C 1 output from the NAND-gates 1306 and 1307 inverted to the outputs of the XOR-gates 1308 and 1309 , respectively. Since the XOR-gates 1308 and 1309 respectively output the bits b[ 2 ] and /b[i] at the point, the control signals C 2 and C 1 are /b[ 2 ] and b[i] opposite to the b[ 2 ] and /b[i].
- the control signals C 2 and C 1 in the third phase T 3 should be b[ 2 ] and /b[ 1 ], respectively, while the control signals C 2 and C 1 in the fourth phase T 4 should be b[ 2 ] and b[ 1 ], respectively.
- the switching circuit 420 is able to achieve the ‘output phase by phase’ mode as shown in FIGS. 11A and 11B in the phases T 2 ⁇ T 4 by using the bits b[ 2 ] and b[ 1 ] to control the switching circuit 420 .
- the switching circuit 420 in the second phase T 2 produces the control signals C 2 and C 1 both with a low-level (logic-0), which turns off the switches SWA(1;1), SWA(1;2), SWA(2;1) and SWA(2;2) and makes the analog signal hold the voltage level output in the first phase T 1 (the reference voltage V 1 ).
- the control signals C 2 and C 1 take a high-level (logic-1), which turns on the switches SWA(1;1), SWA(1;2), SWA(2;1) and SWA(2;2) and the analog signal is charged to the reference voltage V 3 .
- the control signal C 2 turns on the switches SWA(2;1) and SWA(2;2)
- the control signal C 1 turns off the switches SWA(1;1) and SWA(1;2) and the analog signal holds the level output in the third phase T 3 (the reference voltage V 3 ).
- the output terminal of the embodiment in FIG. 4 can be modified by adding an output switching unit 1401 as shown in FIG. 14 , which combines the spirit of the present invention with the prior art for more effectively utilizing the circuit.
- the output switching unit 1401 is formed by aa switches SW 1 ⁇ SW aa , the first terminal of the switch SW 1 is coupled with the signal output terminal S out1 , the second terminal thereof is coupled with the output terminal of the decoding unit 403 , the first terminal of the switch SW 2 is coupled with the signal output terminal S out2 and the second terminal thereof is coupled with the output terminal of the decoding unit 403 .
- the first terminal of the b th switch among the switches SW 1 ⁇ SW aa is coupled with the b th signal output terminal S outb and the second terminal of the b th switch is coupled with the output terminal of the decoding unit 403 , where a and b are integers, and 1 ⁇ b ⁇ aa.
- a and b are integers, and 1 ⁇ b ⁇ aa.
- FIG. 15 is a 3-bits DAC according to the embodiment shown by FIG. 14 .
- the control unit 402 in the embodiment receives a bit b[ 1 ] of the digital signal and the decoding unit 403 receives two bits b[ 2 ] and b[ 3 ] and two bits /b[ 2 ] and /b[ 3 ] of the digital signal, which is similar to the embodiment of FIG. 5 .
- the output switching unit 1401 in FIG. 15 is formed by switches SW 1 and SW 2 .
- the first terminals of the switches SW 1 and SW 2 are electrically connected to the signal output terminals S out1 and S out2 , respectively, while the second terminals of the switches SW 1 and SW 2 are electrically connected to the output terminal of the decoding unit 403 .
- FIG. 16 The working principle of the embodiment in FIG. 15 can be better explained by referring to FIG. 16 .
- the control unit 402 and the decoding unit 403 in FIG. 15 are similar to the control unit 402 and the decoding unit 403 in FIG. 5 . Therefore, the decoding unit 403 in FIG. 15 is able to output an analog signal similar to the one in FIG. 6A . Since the output switching unit 1401 uses the timing switching signals CLK SW1 and CLK Sw2 to control the switches SW 1 and SW 2 , the decoding unit 403 would output an analog signal similar to the one in FIG.
- FIG. 16 illustrates a timing diagram of the above-described analog signal from the first phase T 1 to the fourth phase T 4 .
- the present invention further provides a digital-to-analog conversion method.
- the method is to set the levels of the 2 M+N reference voltages V q in response to receiving a digital signal with (M+N)-bits.
- N and M are integers larger than zero
- V q represents a q th reference voltage and 1 ⁇ q ⁇ 2 M+N .
- 2 M voltages VR k are provided in an output period, and the levels of the voltages VR k in 2 N phases of the output period are the levels of the reference voltages V ((k ⁇ 1) ⁇ 2 ⁇ N)+1 ⁇ V k ⁇ 2 ⁇ N , respectively.
- one of the above-described 2 M voltages VR k is selected and further a level among the levels V ((k ⁇ 1) ⁇ 2 ⁇ N)+1 ⁇ V k ⁇ 2 ⁇ N of the selected voltage VR k is selected as the analog signal.
- the received digital signal with (M+N)-bits is converted into an analog signal.
- the present invention employs a control unit and uses the control of the N bits of the digital signal and the N timing signals to make multiple reference voltages share a same output terminal, which effectively downsizes the chip area required mainly by the reference voltage lines and the decoding unit.
- it not only reduces the chip area, but also has the advantage of outputting the analog signal phase by phase without disposing an extra switch, which enables the driving driver to drive every output terminal with sufficient charge time at any time.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
A digital-to-analog converter (DAC) and the method thereof are disclosed. The DAC receives a digital signal with (M+N) bits, and a reference voltage unit sequentially outputs 2M+N reference voltages through the 2N output terminals thereof according to at least N timing signals. Afterwards, a control unit outputs at least a reference voltage to a decoding unit according to the above-mentioned N timing signals and the N bits of the digital signal. In the end, the decoding unit selects one of the signals produced by the control unit as the analog signal for output according to the M bits of the digital signal.
Description
- This application claims the priority benefit of Taiwan application Ser. No. 95115702, filed on May 3, 2006. All disclosure of the Taiwan application is incorporated herein by reference.
- 1. Field of Invention
- The present invention relates to a digital-to-analog converter (DAC), and more particularly to a DAC which phase by phase outputs the digital signal according to N timing signals.
- 2. Description of the Related Art
- In terms of the mechanism for driving a display panel of a conventional thin film transistor liquid crystal display (TFT LCD), a source driver is used to provide the analog signal required for driving pixels. Wherein, every output terminal of the source driver is electrically connected to a conventional DAC as shown in
FIG. 1 . Referring toFIG. 1 , a conventional DAC (a DAC with 3-bits resolution is taken as exemplary herein) includes threeswitch units 101˜103. Theswitch units 101˜103 are respectively controlled by bits b[3]˜b[1], wherein the switches in each switch unit are allocated in couples (for example, SW17 and SW18; SW13 and SW14) and the coupled switches are electrically connected to a same switch. In addition, the coupled switches are controlled by a bit and the phase-inverted bit of the bit, respectively (for example, the switches SW18 and SW17 are respectively controlled by the bit b[1] and the phase-inverted bit thereof /b[1]). Therefore, the reference voltages V1˜V8 to be input to the conventional DAC are sequentially delivered through the switching operations of the switch units from 101 to 103 under the controls of the digital signals b[3]˜b[1]. In this way, theswitch unit 101 selects half of the reference voltages from the reference voltages V1˜V8 for outputting and delivering to theswitch unit 102. Afterwards, through the switching operation of theswitch unit 102, the received four reference voltages (for example, V1, V3, V5 and V7) are selected into two reference voltages for outputting to theswitch unit 101. Theswitch unit 101 would, through switching, select a reference voltage as the output analog signal Vout1 of the conventional DAC. - According to the above mentioned, a conventional DAC employs multiple switches to implement the switching on the reference voltages. Such a scheme, however, requires a huge number of switches for numerous DACs to be disposed in a source driving circuit, which indicates an excessive cost a TFT LCD needs.
- To solve the above-described problem, another
conventional DAC 210 was provided. Referring toFIG. 2 , theconventional DAC 210 is formed by aconventional DAC 110 and switches SW21 and SW22. The switches SW21 and SW22 are respectively coupled with the output terminal of theconventional DAC 110 to further create two signal output terminals Pout21 and Pout22 controlled by timing switching signals SWCLK21 and SWCLK22. Thus, every two output terminals of a source driver share a same DAC, which is advantageous to downsize the chip area. Wherein, the analog signals are output phase by phase as shown inFIG. 3 , which can be achieved by using two non-overlapped timing switching signals SWCLK21 and SWCLK22. When the timing switching signal SWCLK21 turns on the switch SW21, an analog signal Vout21 is produced and delivered to the signal output terminal Pout21; when the timing switching signal SWCLK22 turns on the switch SW22, an analog signal Vout22 is produced and delivered to the signal output terminal Pout22. - Although the above-mentioned
conventional DAC 210 functions to downsize a chip area, however, it only allows a half of the output terminals of a source driver being able to drive pixels at any time under the ‘phase by phase outputting’ mode. Under the situation, the available charging time each output terminal can provide to the pixels needs to be shortened, and the available charging time is reduced proportionally with the number of the DACs the output terminals share. In comparison with theconventional DAC 110, on each switching path of theconventional DAC 210, an extra switch is required to be disposed (as shown by thearrows FIG. 1 andFIG. 2 ). Thus, to avoid the increase of the equivalent resistor, theconventional DAC 210 is forced to adopt the switches (SW21 and SW22) with a larger layout area in order to maintain the original performance of the source driver. - An object of the present invention is to provide a DAC using a control unit controlled by multiple timing signals to reduce the number of the switches inside the circuit and the number of the reference voltage lines, which further lowers the cost of the source driving circuit. Compared with the prior art, the present invention no longer requires increasing the switching paths of the switches; furthermore, the present invention also enables the source driver to drive every output terminal at any time.
- Another object of the present invention is to provide a digital-to-analog converting method, where the timings of multiple timing signals are used to make the analog signals output phase by phase and to achieve the advantage of downsizing chip area.
- To achieve the above-described and other objectives, the present invention provides a DAC, which includes a reference voltage unit, a control unit and a decoding unit. The reference voltage unit includes 2M output terminals VRk. The control unit coupled with the 2M output terminals of the reference voltage unit delivers at least a reference voltage among the reference voltages output from the above-mentioned output terminals VRk to the 2M output terminals of the control unit according to the N timing signals and the N bits of the digital signal, respectively. In the end, the decoding unit selects a signal among the signals come from the 2M output terminals of the control unit as an analog signal for output according to M bits of the digital signal. In this way, the converter is able to select a reference voltage from the received 2M+N reference voltages Vq (at most) as an analog signal for output according to the digital signal having (M+N) bits, where N, M are integers larger than zero and 1≦q≦2M+N, 1≦k≦2M.
- According to the DAC of an embodiment of the present invention, each output terminal respectively outputs reference voltages V((k−1)·2̂N)+1˜Vk·2̂N in 2N time phases of an output period, where V1≦V2≦ . . . ≦V2̂(M+N). According to the DAC of another embodiment of the present invention, each output terminal respectively outputs reference voltages V((k−1)·2̂N)+1˜Vk·2̂N in 2N time phases of an output period, where V1≧V2≧ . . . ≧V2̂(M+N).
- According to the DAC of an embodiment of the present invention, if the xth bit of the digital signal is represented by b[x], 1≦x≦(M+N), b[1] is the least significant bit (LSB) of the digital signal and b[M+N] is the most significant bit (MSB) of the digital signal, the control unit receives b[1]˜b[N] of the digital signal, while the decoding unit receives b[N+1]˜b[M+N] of the digital signal.
- According to the DAC of an embodiment of the present invention, the control unit includes a control circuit and a switching circuit. The control circuit is used for outputting N control signals according to the N timing signals and the bits b[1]˜b[N]. The switching circuit electrically connected to the control circuit phase by phase outputs the reference voltages V((k−1)·2̂N)+1∞Vk·2̂N provided by the output terminals VRk according to the control result of the N control signals on the circuit itself.
- On the other hand, the present invention provides a digital-to-analog converting method. The method is to provide 2M voltages VRk in an output period by receiving a digital signal with (M+N)-bits and setting the levels of 2M+N reference voltages Vq. Wherein, the levels of the voltage VRk in 2N phases are V((k−1)·2̂N)+1˜Vk·2̂N, respectively. After that, one of the above-described 2M voltages VRk is selected, and further at lease a level among the levels V((k−1)·2̂N)+1˜Vk·2̂N of the selected voltage VRk is selected as the analog signal, so as to achieve the objective of digital-to-analog conversion. Wherein, N, M are integers larger than zero, Vq represents the qth reference voltage and 1≦q≦2M+N, a≦k≦2M.
- The present invention uses N timing signals to respectively control the control unit and the reference voltage unit, so that multiple reference voltages are able to share an output, which contributes to downsize the chip area required by the reference voltage lines and the decoding unit. In comparison with the conventional architecture, the present invention not only achieves the objective of lowering the chip area, but also enables the source driver to drive every output terminal at any time.
- The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve for explaining the principles of the invention.
-
FIG. 1 is a detailed circuit drawing of a conventional digital-to-analog converter (DAC). -
FIG. 2 is a detailed circuit drawing of another conventional DAC. -
FIG. 3 illustrates the analog signal timing diagrams for the DAC inFIG. 2 . -
FIG. 4 is a detailed framework drawing of a DAC according to an embodiment of the present invention. -
FIG. 5 is a detailed circuit drawing of a 3-bits DAC according to an embodiment of the present invention. -
FIGS. 6A and 6B are analog signal timing diagrams for the DAC inFIG. 5 . -
FIG. 7 is another analog signal timing diagram for the DAC inFIG. 5 . -
FIG. 8 is a detailed circuit drawing of another 3-bits DAC according to an embodiment of the present invention. -
FIG. 9 is an analog signal timing diagram for the DAC inFIG. 8 . -
FIG. 10 is a detailed circuit drawing of another 3-bits DAC according to an embodiment of the present invention. -
FIGS. 11A and 11B are analog signal timing diagrams for the DAC inFIG. 10 . -
FIGS. 12A and 12B are another set of the analog signal timing diagrams for the DAC inFIG. 10 . -
FIG. 13 is a detailed drawing of a control circuit according to an embodiment of the present invention. -
FIG. 14 is a detailed framework drawing of another DAC according to an embodiment of the present invention. -
FIG. 15 is a detailed circuit drawing of a 3-bits DAC according to the embodiment shown inFIG. 14 . -
FIG. 16 is an analog signal timing diagram of the DAC ofFIG. 15 . -
FIG. 4 is a detailed framework drawing of a DAC according to an embodiment of the present invention. Referring toFIG. 4 , the DAC receiving a digital signal with (M+N) bits of b[M+N]˜b[1] includes areference voltage unit 401, acontrol unit 402 and adecoding unit 403, where N and M are integers larger than zero. Thereference voltage unit 401 includes 2M output terminals VR1˜VR2̂M. Thecontrol unit 402 is electrically connected to the 2M output terminals of thereference voltage unit 401. Thedecoding unit 403 is electrically connected to the 2M output terminals of thecontrol unit 402. Thereference voltage unit 401 outputs the reference voltages V1˜V2̂(M+N) through the output terminals VR1˜VR2̂M according to the timing of the N timing signals, wherein VRk represents the kth output terminal and provides the reference voltages V((k−1)·2̂N)+1˜Vk·2̂N, where 1≦k≦2M. Afterwards, thecontrol unit 402 delivers one of the reference voltages V((k−1)·2̂N)+1˜Vk·2̂N output from each of the above-mentioned output terminals VRk to the 2M output terminals of thecontrol unit 402 according to the above-mentioned N timing signals and the N bits b[N]˜b[1] of the digital signal. In the end, thedecoding unit 403 selects one of the output signals come from the 2M output terminals of thecontrol unit 402 as an analog signal for output according to the M bits b[M+N]˜b[N+1] and the bits /b[M+N]˜/b[N+1]. Wherein, the bits /b[M+N]˜/b[N+1] are logic-levels inverted to the bits b[M+N]˜b[N+1], respectively. - Among the above-mentioned reference voltages, the reference voltage V1 has the lowest level, the reference voltage V2 has a level next to the lowest, and the rest can be analogized. The reference voltage V2̂(M+N) has the highest level, i.e., V1≦V2≦ . . . ≦V2̂(M+N). The bit b[1] is the least significant bit (LSB) of the digital signal, while bit b[M+N] is the most significant bit (MSB) of the digital signal. In addition, anyone skilled in the art is able to re-design the levels of the reference voltages V1˜V2̂(M+N) into V1≧V2≧ . . . ≧V2̂(M+N) to fit the different application requirements.
- The
control unit 402 of the embodiment inFIG. 4 includes acontrol circuit 410 and aswitching circuit 420. Theswitching circuit 420 includes N switching units UA1˜UAN and each of the switching units UA1˜UAN includes 2M switches. The second terminal of the switch SWA(1;1) is coupled with the first terminal of the switch SWA(2;1); the second terminal of the switch SWA(1;2) is coupled with the first terminal of the switch SWA(2;2); and the second terminal of the switch SWA(N;1) is coupled with the output terminal VR0 of thereference voltage unit 401. Analogically, the second terminal of the switch SWA(s;k) is coupled with the first terminal of the switch SWA(s+1;k), while the second terminal of the switch SWA(N;k) is coupled with the output terminal VRk of thereference voltage unit 401, where SWA(s;k) indicates the kth switch of the sth switching unit UAS, 1≦s≦N. - Continuing to
FIG. 4 , in terms of the overall operation of thecontrol unit 402, first, thecontrol circuit 410 outputs N control signals C1˜CN to theswitching circuit 420 according to the N timing signals and the N bits b[1]˜b[N]. Next, each switch in theswitching circuit 420 decides on/off status thereof according to the control signals C1˜CN, respectively, so that one of the reference voltages V1˜V2̂(M+N) is allowed to be output to thedecoding unit 403. Wherein, the control terminals of the switches SWA(1;1)˜SWA(1;2M) receive the control signal C1, while the control terminals of the switches SWA(2;1)˜SWA(2;2M) receive the control signal C2. Analogically, the control terminal of the switch SWA(t;r) receives the control signal Ct, 1≦t≦N. - The
decoding unit 403 of the embodiment inFIG. 4 includes M switch units UB1˜UBM. The switch unit UB1 includes two switches SWB(1;1) and SWB(1;2). The switch unit UB2 includes four (22) switches SWB(2;1)˜SWB(2;4). Analogically, the ith switch unit UBi includes 2i switches SWB(i;k), wherein SWB(i;k) represents the kth switch of the ith switch unit Ubi, and 1<i<M. - The second terminal of the switch SWB(1;1) is electrically connected to the first terminals of the switches SWB(2;1) and SWB(2;2); the second terminal of the switch SWB(1;2) is electrically connected to the first terminals of the switches SWB(2;3) and SWB(2;4); the control terminal of the switch SWB(1;1) receives the bit b[M+N], while the control terminal of the switch SWB(1;2) receives the bit /b[M+N]. Analogically, the second terminal of the switch SWB(j;k) is electrically connected to the first terminals of the switches SWB(j+1;2k−1) and SWB(j+1;2k) and the second terminal of the switch SWB(M;k) is coupled with the
switching unit 420. The control terminal of the switch SWB(i;2g−1) receives the bit b[M+N+1−i], while the control terminal of the switch SWB(i;2g) receives the bit /b[M+N+1−i]. Wherein, the logic-level of the bit /b[i] is inverted to bit b[i], 1≦j≦(M−1) and the g value range is: 1≦g≦2i−1. - The
decoding unit 403 has the similar working principle and the architecture to the conventional DAC. By using the scheme that the switches in every switch unit of UB1˜UBM are allocated in couples (for example, SWB(2;1) and SWB(2;2) form a couple), the switches of a couple are electrically connected to a same switch (for example, SWB(1;1)) and the switches in a couple are respectively controlled by a bit and the phase-inverted bit of the bit (for example, SWB(2;1) and SWB(2;2) are respectively controlled by the bit b[M+N−1] and the phase-inverted bit /b[M+N−1]), one of the signals provided by theoutput terminals 2M of thecontrol unit 402 would be selected by thedecoding unit 403 after the sequentially switching operations of the switch units UB1˜UBM as an analog signal for output. - To better explain the present invention, an embodiment of 3-bits DAC is taken as exemplary. As shown in
FIG. 5 , it is an embodiment corresponding to N=1 and M=2 inFIG. 4 , that is, thecontrol unit 402 receives one bit b[1] of the digital signal, while thedecoding unit 403 receives two bits b[2] and b[3] of the digital signal. Thecontrol circuit 410 of thecontrol unit 402 is formed by anNAND-gate 501. Theswitching circuit 420 includes a switching unit UA1 formed by 22 switches SWA(1;1)˜SWA(1;4). Thedecoding unit 403 includes switch units UB1 and UB2. The switch unit UB1 includes switches SWB(1;1) and SWB(1;2), while the switch unit UB2 includes switches SWB(2;1)˜SWB(2;4), The first terminal of theNAND-gate 501 is used for receiving the inverted signal /b[1] of the bit b[1], while the second terminal thereof receives a timing signal CLK51 and outputs a control signal C1 according to the received signal. The wiring relationships of the switches SWA(1;1)˜SWA(1;4), the switches SWB(1;1) and SWB(1;2), and the switches SWB(2;1)˜SWB(2;4) can be obtained by a relationship derived from the embodiment inFIG. 4 , and the detail is omitted to describe herein. - Prior to describing the working principle of the embodiment of
FIG. 5 , the mode ‘output phase by phase’ is to be defined first. The so-called ‘output phase by phase’ mode means that the DAC outputs the analog signal by 2N phases according to the number N of the bits received by thecontrol unit 402. Thus, the output timing of the analog signal corresponding to the case N=1 of theFIG. 5 embodiment is as shown inFIGS. 6A and 6B , where the analog signal is output by two phases (T1 and T2). If the analog signal is one of V1, V3, V5 and V7 (for example, V1), the analog signal would be charged/discharged to a predetermined level (for example, V1) in the first phase and hold the level (for example, V1) in the second phase. On the other hand, if the analog signal is one of V2, V4, V6 and V8 (for example, V2), the analog signal would be charged/discharged to one of V1, V3, V5 and V7 (for example, V1) in the first phase and be re-charged to a predetermined level (for example, V2) in the second phase. - Continuing to
FIG. 5 ,FIG. 6A andFIG. 6B , the working principle of the present embodiment is explained as follows. Thereference voltage unit 401 represented by a block inFIG. 5 is omitted for simplicity. Instead, thereference voltage unit 401 respectively outputs the reference voltages V1˜V8 through the output terminals VR1˜VR4 according to a timing signal CLK51. As shown inFIG. 5 , thereference voltage unit 401 sends out the reference voltages V1, V3, V5 and V7 in the first phase T1 and sends out the reference voltages V2, V4, V6 and V8 in the second phase T2 according to the timing signal CLK51. The reference voltages V1˜V8 are allocated in couples and the two voltages of a couple are provided by an output terminal of VR1˜VR4 (for example, V1 and V2 are provided by the output terminal VR1). Next, thecontrol circuit 410 in the first phase T1 outputs a control signal C1 with a high-level (logic-1) in response to the low-level (logic-0) of the timing signal CLK51 which makes the NAND-gate 501 ignore the phase-inverted signal /b[1] of the bit b[1]. The switches SWA(1;1)˜SWA(1;4) in theswitching unit 420 hold the on-state in the first phase T1 according to the control signal C1, so as to output the reference voltages V1, V3, V5 and V7 to the four output terminals of thecontrol unit 402, respectively. At the point, as shown inFIGS. 6A and 6B , thedecoding unit 403 would select one of signals provided by the four output terminals of thecontrol unit 402 according to the bits b[2], b[3], /b[2] and /b[3], so that the analog signal is charged/discharged to one of the reference voltages V1, V3, V5 and V7 (for example, V1) in the first phase T1. - Afterwards, in the second phase T2, the
control circuit 410 makes the control signal C1 output from the NAND-gate 501 the same as the bit b[1] in response to the high-level (logic-1) of the timing signal CLK51. Thus, if the bit b[1] is the high-level (logic-1), i.e. the predetermined output level of the analog signal is one of V2, V4, V6 and V8 (for example, V2), the control signal C1 would turn on the switches SWA(1;1)˜SWA(1;4) in theswitching unit 420, so that the reference voltages V2, V4, V6 and V8 are respectively output to the four output terminals of thecontrol unit 402. In this way, as shown inFIGS. 6A and 6B , thedecoding unit 403 is able to make the analog signal charge to a predetermined output level (for example, V2) in the second phase T2 according to the bits b[2], b[3], /b[2] and /b[3]. On the other hand, if the bit b[1] is the low-level (logic-0), i.e. the predetermined output level of the analog signal is one of V1, V3, V5 and V7 (for example, V1), the switches SWA(1;1)˜SWA(1;4) in theswitching unit 420 would be off under the control of the control signal C1, which further makes the output terminal of thedecoding unit 403 in floating-state and the analog signal in the second phase T2, and accordingly hold the level obtained in the first phase T1 (for example, V1). - According to the above-described embodiment, by rearranging the duty cycle of the timing signal CLK51, the analog signal can be charged/discharged phase by phase for more effectively utilizing time. The scheme is shown by
FIG. 7 where the charge time of the analog signal in the second phase T2 is far less than the charge time in the first phase T1 due to a minor difference between two consecutive reference voltages (for example, difference between V1 and V2). If the DAC receives a 3-bits digital signal, sequentially 000-111-000, the output analog signal during the phase-by-phase charging period has a timing distribution as shown inFIG. 7 where a reduced time ratio corresponding to the second phase T2 suggests a more effectively utilization of the timing signal CLK51. - In addition, the
control circuit 410 in the embodiment ofFIG. 5 can adopt another design as well. Referring toFIG. 8 , thecontrol circuit 410 inFIG. 5 is formed by anOR-gate 801. For convenience of explanation, a detailed architecture of a DAC similar toFIG. 5 is illustrated byFIG. 8 . Wherein, the first terminal and the second terminal of the OR-gate 801 respectively receive the bit b[1] and the timing signal CLK51, and the OR-gate 801 outputs a control signal C1 to the control terminals of the switches SWA(1;1)˜SWA(1;4). The coupling relationships of theswitching circuit 420, thedecoding unit 403 and the output timing and the routed output terminals of the reference voltages V1˜V8 are the same asFIG. 5 , so the details are omitted to describe herein. - Continuing to
FIG. 8 , in spite of the modification of thecontrol circuit 410, as long as thecontrol circuit 410, asFIG. 5 , is able to output a control signal C1 with a high-level (logic-1) to theswitching unit 420 in the first phase T1 and the control signal C1 output from thecontrol circuit 410 is equal to the bit b[1] in the second phase T2, the working principle described by the embodiment inFIG. 4 is still valid. Thus, the present embodiment utilizes a timing signal CLK81 holding a high-level (logic-1) in the first phase T1 to enable thecontrol circuit 410 to output a control signal C1 with a high-level (logic-1) to theswitching unit 420 and makes the timing signal CLK81 hold a low-level (logic-0), so that the control signal output from the OR-gate 801 can be equal to the bit b[1]. As a result, that the analog signal is able to be output phase by phase as shown inFIGS. 6A and 6B . - According to the embodiment of
FIG. 8 , the analog signal can be charged/discharged phase by phase for more effectively utilizing time, as the embodiment inFIG. 5 . Referring toFIG. 9 , if the DAC receives a 3-bits digital signal, sequentially 000-111-000, the time ratio corresponding to the second phase T2 is reduced as inFIG. 7 , a more effectively utilization of the duty cycle of the timing signal CLK51 is expected. - Another embodiment of a 3-bits DAC is given hereinafter. Referring to
FIG. 10 , the present embodiment corresponds to the case of N=2 and M=1 inFIG. 4 , which means thecontrol unit 402 receives the two bits of b[2] and b[1] in the digital signal and thedecoding unit 403 receives a bit b[3] and a bit /b[3] in the digital signal. Theswitching circuit 420 includes two switching units UA1 and UA2, while the switching units UA1 and UA2 respectively include switches SWA(1;1) and SWA(1;2) and switches SWA(2;1) and SWA(2;2). Thedecoding unit 403 is formed by a switch unit UB1, while the switch unit UB1 includes switches SWB(1;1) and SWB(1;2). The coupling relationships of the switches SWA(1;1), SWA(1;2), SWA(2;1) and SWA(2;2) in thecontrol circuit 410 and theswitching circuit 420 and the switches SWB(1;1) and SWB(1;2) in thedecoding unit 403 follow the relationship derived inFIG. 4 , so the detail is omitted to describe herein. - The embodiment of
FIG. 10 makes an analog signal output by 22 phases according to N=2, the number of the bits received by thecontrol unit 402. In an output timing formed by four phases T1˜T4, associated with a modified design of thecontrol circuit 410, the analog signal has various output distributions with multi-phases. One of the timings in ‘output phase by phase’ mode is shown byFIGS. 11A and 11B , wherein if the predetermined output level of the analog signal is the reference voltage V3 during the output course formed by four phases T1˜T4, the analog signal can be charged to the reference voltage V1 in the first phase T1. In the second phase T2, the analog signal holds the reference voltage V1. Afterwards, in the third phase T3, the analog signal is recharged to the reference voltage V3, and in the fourth phase T4 the analog signal holds the predetermined level, the reference voltage V3. In addition, according toFIGS. 11A and 11B , the output course of the analog signal with a final level of the reference voltage V3 can be in this way. The analog signal is charged to the reference voltage V1 in the first phase T1. In the second phase T2, the analog signal is recharged to the reference voltage V2. Afterwards, in the third phase T3, the analog signal is recharged to the reference voltage V3, and in the fourth phase T4the analog signal holds the predetermined level, the reference voltage V3. Another variation of the phase-by-phase output timing is shown byFIGS. 12A and 12B , where after the analog signal is charged to the predetermined level, the analog signal in thereafter phase holds the level of the previous phase. For example, the predetermined level of an analog signal is the reference voltage V3, the analog signal is charged repeatedly phase by phase, from the first phase to the third phase, to the final level of the reference voltage V3, followed by holding the analog signal in the reference voltage V3 in the fourth phase. Therefore, in comparison withFIGS. 11A and 11B , the ‘output phase by phase’ mode shown byFIGS. 12A and 12B can be covered by the scheme ofFIGS. 11A and 11B . - According to the ‘output phase by phase’ mode shown by
FIGS. 11A and 11B , acontrol circuit 410 compliant with the embodiment ofFIG. 10 is given byFIG. 13 . Thecontrol circuit 410 includes NAND-gates 1305˜1307 and XOR-gates NAND-gate 1305 receives the phase-inverted signal /CLK101 of the timing signal CLK101, while the second terminal thereof receives the phase-inverted signal /CLK102 of the timing signal CLK102. The first terminal of theXOR-gate 1308 receives the phase-inverted signal /CLK102 of the timing signal CLK102, while the second terminal thereof receives the phase-inverted signal /b[1] of the bit b[1]. The first terminal and the second terminal of the NAND-gate 1306 are electrically connected to the output terminals of the NAND-gate 1305 and theXOR-gate 1308, respectively. In addition, the first terminal and the second terminal of the NAND-gate 1307 are electrically connected to the output terminals of the NAND-gate 1305 and theXOR-gate 1309, respectively. - The reference voltages V1˜V8 output from the
reference voltage unit 401 are divided into two sets of four reference voltages according to the architecture of the system and each set of the four reference voltages is provided by an output terminal (for example, V1˜V4 are provided by the output terminal VR0). According to the timing signals CLK101 and CLK102, the reference voltages V1 and V5 among the reference voltages V1˜V8 are sent out in the first phase T1; the reference voltages V2 and V6 are sent out in the first phase T2, and the rest can be analogized as shown inFIG. 10 . Afterwards, in thecontrol unit 402 for receiving the reference voltages V1˜V8, the NAND-gate 1305 outputs a low-level (logic-0) in the first phase where the timing signals CLK101 and CLK102 take a low-level (logic-0). Thus, the NAND-gates control unit 420, so as to respectively deliver the reference voltages V1 and V5 to the two output terminals of thecontrol unit 402. Thedecoding unit 403 charges the analog signal to one of the levels of the reference voltages V1 and V5 according to the bits b[3] and /b[3]. - In the following second phase T2, the timing signals CLK101 and CLK102 respectively take a high-level (logic-1) and a low-level (logic-0) and the NAND-gate 1305 outputs a high-level (logic-1), which makes the control signals C2 and C1 output from the NAND-
gates gates gates switching circuit 420 is able to achieve the ‘output phase by phase’ mode as shown inFIGS. 11A and 11B in the phases T2˜T4 by using the bits b[2] and b[1] to control theswitching circuit 420. For example, if the predetermined level of the analog signal is the reference voltage V3, that is, the bits b[2] and b[1] are a high-level (logic-1) and a low-level (logic-0) respectively, theswitching circuit 420 in the second phase T2 produces the control signals C2 and C1 both with a low-level (logic-0), which turns off the switches SWA(1;1), SWA(1;2), SWA(2;1) and SWA(2;2) and makes the analog signal hold the voltage level output in the first phase T1 (the reference voltage V1). In the third phase T3, however, the control signals C2 and C1 take a high-level (logic-1), which turns on the switches SWA(1;1), SWA(1;2), SWA(2;1) and SWA(2;2) and the analog signal is charged to the reference voltage V3. In the final fourth phase T4, the control signal C2 turns on the switches SWA(2;1) and SWA(2;2), the control signal C1 turns off the switches SWA(1;1) and SWA(1;2) and the analog signal holds the level output in the third phase T3 (the reference voltage V3). - The output terminal of the embodiment in
FIG. 4 can be modified by adding anoutput switching unit 1401 as shown inFIG. 14 , which combines the spirit of the present invention with the prior art for more effectively utilizing the circuit. Wherein, theoutput switching unit 1401 is formed by aa switches SW1˜SWaa, the first terminal of the switch SW1 is coupled with the signal output terminal Sout1, the second terminal thereof is coupled with the output terminal of thedecoding unit 403, the first terminal of the switch SW2 is coupled with the signal output terminal Sout2 and the second terminal thereof is coupled with the output terminal of thedecoding unit 403. Analogically, the first terminal of the bth switch among the switches SW1˜SWaa is coupled with the bth signal output terminal Soutb and the second terminal of the bth switch is coupled with the output terminal of thedecoding unit 403, where a and b are integers, and 1≦b≦aa. In this way, by using theswitching unit 1401, aa signal output terminals Sout1˜Soutaa are formed in the DAC. Furthermore, by using aa timing switching signals CLKSW1˜CLKSWaa to control the switches SW1˜SWaa, the analog signal is sent to one of the signal output terminals Sout1˜Soutaa. -
FIG. 15 is a 3-bits DAC according to the embodiment shown byFIG. 14 . Thecontrol unit 402 in the embodiment receives a bit b[1] of the digital signal and thedecoding unit 403 receives two bits b[2] and b[3] and two bits /b[2] and /b[3] of the digital signal, which is similar to the embodiment ofFIG. 5 . Thus, the wiring and the working principles of thecontrol unit 402 and thedecoding unit 403 are omitted to describe herein. Theoutput switching unit 1401 inFIG. 15 is formed by switches SW1 and SW2. The first terminals of the switches SW1 and SW2 are electrically connected to the signal output terminals Sout1 and Sout2, respectively, while the second terminals of the switches SW1 and SW2 are electrically connected to the output terminal of thedecoding unit 403. - The working principle of the embodiment in
FIG. 15 can be better explained by referring toFIG. 16 . In fact, thecontrol unit 402 and thedecoding unit 403 inFIG. 15 are similar to thecontrol unit 402 and thedecoding unit 403 inFIG. 5 . Therefore, thedecoding unit 403 inFIG. 15 is able to output an analog signal similar to the one inFIG. 6A . Since theoutput switching unit 1401 uses the timing switching signals CLKSW1 and CLKSw2 to control the switches SW1 and SW2, thedecoding unit 403 would output an analog signal similar to the one inFIG. 6A to the signal output terminals Sout1 in response to the switch SW1 in on state in the first phase T1 and the second phase T2 (the switch SW2 is off at the point); thedecoding unit 403 would output an analog signal similar to the one inFIG. 6A to the signal output terminals Sout2 in response to the switch SW2 in on state in the third phase T3 and the fourth phase T4 (the switch SW1 is off at the point).FIG. 16 illustrates a timing diagram of the above-described analog signal from the first phase T1 to the fourth phase T4. - On the other hand, the present invention further provides a digital-to-analog conversion method. First, the method is to set the levels of the 2M+N reference voltages Vq in response to receiving a digital signal with (M+N)-bits. Wherein, N and M are integers larger than zero, Vq represents a qth reference voltage and 1≦q≦2M+N. Next, in response to the levels of the above-mentioned reference voltages Vq, 2M voltages VRk are provided in an output period, and the levels of the voltages VRk in 2N phases of the output period are the levels of the reference voltages V((k−1)·2̂N)+1˜Vk·2̂N, respectively. Afterwards, one of the above-described 2M voltages VRk is selected and further a level among the levels V((k−1)·2̂N)+1˜Vk·2̂N of the selected voltage VRk is selected as the analog signal. In this way, the received digital signal with (M+N)-bits is converted into an analog signal. The detail of the method is covered by the above-described embodiments and omitted to describe herein.
- In summary, the present invention employs a control unit and uses the control of the N bits of the digital signal and the N timing signals to make multiple reference voltages share a same output terminal, which effectively downsizes the chip area required mainly by the reference voltage lines and the decoding unit. In comparison with the prior art, for the application of the present invention in a source driver, it not only reduces the chip area, but also has the advantage of outputting the analog signal phase by phase without disposing an extra switch, which enables the driving driver to drive every output terminal with sufficient charge time at any time.
- It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the specification and examples to be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims and their equivalents.
Claims (14)
1. A digital-to-analog converter (DAC), used for selecting one of at most 2M+N reference voltages Vq as the analog signal for output according to a (M+N)-bit digital signal, wherein Vq represents a qth reference voltage, 1≦q≦2M+N, and N and M are integers larger than zero; the DAC comprising:
a reference voltage unit, comprising 2M output terminals VRk, wherein VRk represents the kth output terminal, 1≦k≦2M;
a control unit, coupled with the 2M output terminals VRk of the reference voltage unit, used for respectively delivering at least a reference voltage among the reference voltages outputed from every said output terminal VRk to the 2M output terminals of the control unit according to the N bits among the bits of the digital signal; and
a decoding unit, coupled with the 2M output terminals of the control unit, used for selecting one of the signals from the 2M output terminals of the control unit as the analog signal according to the M bits among the bits of the digital signal.
wherein each of the output terminals VRk respectively outputs reference voltages (k−1)·2̂N)+1˜Vk·2̂N in 2N phases of an output period.
2. The DAC as recited in claim 1 , wherein the reference voltages V1≦V2≦ . . . ≦V2̂(M+N).
3. The DAC as recited in claim 1 , wherein the reference voltages V1≧V2≧ . . . ≧V2̂(M+N).
4. The DAC as recited in claim 1 , wherein if b[x] represents the xth bit of the digital signal, 1≦x≦(M+N), b[1] is the LSB of the digital signal and b[M+N] is the MSB of the digital signal, the control unit receives b[1]˜b[N] of the digital signal, while the decoding unit receives b[N+1]˜b[M+N] of the digital signal.
5. The DAC as recited in claim 4 , wherein the control unit comprises:
a control circuit, used for outputting N control signals Ct according to N timing signals and the bits b[1]˜b[N], where 1≦t≦N; and
a switching circuit, comprising N switching units, wherein each of the switching units comprises 2M switches SWA(s;k), wherein SWA(s;k) represents the kth switch in the sth switching unit, the second terminal of the switch SWA(s;k) is coupled with the first terminal of the SWA(s+1;k), the second terminal of the switch SWA(N;k) is coupled with the output terminal VRk of the reference voltage unit and the control terminal of the switch SWA(t;k) receives the control signal Ct, where 1≦s≦N.
6. The DAC as recited in claim 5 , wherein the bit /b[1] and the bit b[i] have logic-values inverted to each other, the decoding unit comprises M switch units, the ith switch unit comprises 2i switches SWB(i;r) where SWB(i;r) represents the rth switch in the ith switch unit; the second terminal of the switch SWB(j;r) is coupled with the first terminals of the switches SWB(j+1;2r−1) and SWB(j+1;2r), the second terminal of the switch SWB(M;r) is coupled with the switching circuit, the control terminal of the switch SWB(i;2g−1) receives the bit b[M+N+1−i], the control terminal of the switch SWB(i;2g) receives the bit /b[M+N+1−i], where 1≦i≦M, 1≦j≦(M−1), the range of the r value in the ith switch unit is 1≦r≦2i and the range of the g value in the ith switch unit is 1≦g≦2i−1.
7. The DAC as recited in claim 5 , wherein when N=1, the control circuit outputs the control signal according to the timing signal and the bit b[1] and the control circuit comprises:
an NAND-gate, wherein the first terminal thereof receives the phase-inverted signal of the bit b[1], the second terminal thereof receives the timing signal and the NAND-gate outputs the control signal.
8. The DAC as recited in claim 5 , wherein when N=1, the control circuit outputs the control signal according to the timing signal and the bit b[1] and the control circuit comprises:
an OR-gate, wherein the first terminal and the second terminal thereof respectively receive the bit b[1] and the timing signal and the OR-gate outputs the control signal.
9. The DAC as recited in claim 5 , wherein when N=2, the control circuit outputs the first control signal and the second control signal according to the first timing signal, the second timing signal and the bits b[1]˜b[2] and the control circuit comprises:
a first NAND-gate, wherein the first terminal thereof receives the phase-inverted signal of the first timing signal, while the second terminal thereof receives the phase-inverted signal of the second timing signal;
a first XOR-gate, wherein the first terminal thereof receives the phase-inverted signal of the second timing signal, while the second terminal thereof receives the phase-inverted signal of the bit b[2];
a second XOR-gate, wherein the first terminal thereof receives the phase-inverted signal of the first timing signal, while the second terminal thereof receives the phase-inverted signal of the bit b[1];
a second NAND-gate, wherein the first terminal thereof is electrically connected to the output terminal of the first NAND-gate, the second terminal thereof is electrically connected to the output terminal of the first XOR-gate and the second NAND-gate is used for outputting the second control signal; and
a third NAND-gate, wherein the first terminal thereof is electrically connected to the output terminal of the first NAND-gate, the second terminal thereof is electrically connected to the output terminal of the second XOR-gate and the third NAND-gate is used for outputting the first control signal.
10. The DAC as recited in claim 1 , for delivering the analog signal to one of aa signal output terminals according to aa timing switching signals where aa is an integer larger than zero; the DAC further comprising:
an output switching unit, comprising aa switches, wherein the first terminal of the bth switch is coupled with the output terminal of the bth signal, the second terminal of the bth switch is coupled with the output terminal of the decoding unit and the on/off states between the first terminal and the second terminal of the bth switch are determined by the bth timing switching signal, where b is an integer and 1≦b≦aa.
11. A digital-to-analog converting method, used for converting a digital signal into an analog signal; the converting method comprising:
receiving a digital signal with (M+N) bits, wherein N and M are integers larger than zero;
setting the levels of 2M+N reference voltages Vq, wherein Vq represents the qth reference voltage and 1≦q≦2M+N;
providing 2M voltages VRk in an output period, wherein the levels of the voltage VRk in 2N phases of the output period are V((k−1)·2̂N)+1˜Vk·2̂N, respectively;
selecting one of the 2M voltages VRk; and
selecting at least a level among the levels V((k−1)·2̂N)+1˜Vk·2̂N of the selected voltage VRk as the analog signal.
12. The digital-to-analog converting method as recited in claim 11 , wherein the reference voltages V1≦V2≦ . . . ≦V2̂(M+N).
13. The digital-to-analog converting method as recited in claim 11 , wherein the reference voltages V1≧V2≧ . . . ≧V2̂(M+N).
14. The digital-to-analog converting method as recited in claim 11 , wherein the xth bit of the digital signal is b[x], b[1]˜b[N] are a set of less significant bits, b[N+1]˜b[M+N] are a set of larger bits, b[1] is the least significant bit (LSB) and b[M+N] is the most significant bit (MSB), wherein x is an integer and 1≦x≦(M+N).
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW095115702A TWI342005B (en) | 2006-05-03 | 2006-05-03 | Digital-to-analog converter and method thereof |
TW95115702 | 2006-05-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
US7292173B1 US7292173B1 (en) | 2007-11-06 |
US20070257828A1 true US20070257828A1 (en) | 2007-11-08 |
Family
ID=38653416
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/309,100 Expired - Fee Related US7292173B1 (en) | 2006-05-03 | 2006-06-22 | Digital-to-analog converter and method thereof |
Country Status (2)
Country | Link |
---|---|
US (1) | US7292173B1 (en) |
TW (1) | TWI342005B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI467538B (en) | 2012-07-05 | 2015-01-01 | Novatek Microelectronics Corp | Driving voltage generator and digital to analog converter |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6326913B1 (en) * | 2000-04-27 | 2001-12-04 | Century Semiconductor, Inc. | Interpolating digital to analog converter and TFT-LCD source driver using the same |
US20020008650A1 (en) * | 2000-07-20 | 2002-01-24 | Hyundai Electronics Industries Co., Ltd. | Digital-analogue transformer |
-
2006
- 2006-05-03 TW TW095115702A patent/TWI342005B/en not_active IP Right Cessation
- 2006-06-22 US US11/309,100 patent/US7292173B1/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6326913B1 (en) * | 2000-04-27 | 2001-12-04 | Century Semiconductor, Inc. | Interpolating digital to analog converter and TFT-LCD source driver using the same |
US20020008650A1 (en) * | 2000-07-20 | 2002-01-24 | Hyundai Electronics Industries Co., Ltd. | Digital-analogue transformer |
Also Published As
Publication number | Publication date |
---|---|
TW200743083A (en) | 2007-11-16 |
US7292173B1 (en) | 2007-11-06 |
TWI342005B (en) | 2011-05-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5877717A (en) | D/A converter with a Gamma correction circuit | |
US7425941B2 (en) | Source driver of liquid crystal display | |
US9171518B2 (en) | Two-stage DAC achitecture for LCD source driver utilizing one-bit pipe DAC | |
KR100660886B1 (en) | Digital analog converter using capacitor and operational amplifier | |
CN1335682A (en) | Digital to analog converter | |
US6535192B1 (en) | Data driving circuit for liquid crystal display | |
JP4420345B2 (en) | Digital / analog converters, display drivers and displays | |
US10727856B2 (en) | Successive approximation register analog-to-digital converter and control circuit thereof | |
US6225931B1 (en) | D/A converter with a gamma correction circuit | |
US8228317B2 (en) | Active matrix array device | |
WO2006075769A1 (en) | A digital to analogue converter | |
US20090243989A1 (en) | Display apparatus | |
US7292173B1 (en) | Digital-to-analog converter and method thereof | |
CN113678188B (en) | Output driver of display device | |
KR100723509B1 (en) | Digital-analog converting driver joining R-string DAC and capacitor DAC and method thereof | |
KR101239613B1 (en) | Digital to analog converter of data driver and converting method of the same | |
US7595747B2 (en) | Digital-to-analog converter, and method thereof | |
US5673045A (en) | Digital-to-analog conversion circuit and analog-to-digital conversion device using the circuit | |
JP2006014125A (en) | D/a converter, and driving circuit employing d/a converter | |
KR100295676B1 (en) | Liquid crystal display source driver | |
KR100375203B1 (en) | Method of and circuit for converting digital data to analog signals | |
US20080309538A1 (en) | Digital/analog converting driver and method | |
US7283077B2 (en) | Divide-add circuit and high-resolution digital-to-analog converter using the same | |
JP2001160757A (en) | Digital/analog converter | |
KR100207508B1 (en) | digital to analog converter |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: NOVATEK MICROELECTRONICS CORP., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LIU, SHANG-I;REEL/FRAME:017830/0456 Effective date: 20060524 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20151106 |