KR100295676B1 - Liquid crystal display source driver - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LCD source driver. In the related art, a resistive string structure in a source driver for converting an LCD pixel data has a large increase in the chip area of the source driver according to the increase in the number of bits. The increase in the number of bits has a problem that the area of the chip increases. Therefore, when the digital data is input, the digital controller stores the digital data in an internal register and outputs the digital data, and decodes only the upper bits to be converted by the resistor string after receiving the digital data of the digital controller. A plurality of channels for converting and outputting an analog signal, a shift register for connecting six channels of the plurality of channels and storing digital data of the digital control unit by a latch control signal in each channel; Since the voltage divider divides the voltage by only the number of resistances for the upper bits for conversion, the voltage-divided signal lines of the resistor string that occupy most of the source driver chip area by the hybrid digital / analog converter structure are drastically reduced. There is an effect to reduce the area.

Description

LCD source driver {LIQUID CRYSTAL DISPLAY SOURCE DRIVER}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LCD source driver, and more particularly, to an LCD source driver in which a chip structure is combined with a resistor string and a capacitor string so that the chip area hardly increases even when the number of bits is increased.

In general, an LCD source driver is a device that receives digital data, internally converts it to an analog value, and drives the value into pixels through a buffer of an output terminal. Such a conventional device will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a conventional LCD source driver. As shown in FIG. 1, when digital data is input, a digital controller 1 stores an internal register and outputs the digital data. A plurality of channels for receiving digital data, converting them into analog signals, and outputting the analog data are connected to each of six channels of the plurality of channels, and the digital control unit is connected to each channel. Shift registers 2 and 3 for storing digital data of 1) by a latch control signal, and a voltage divider 100 for dividing a voltage for conversion of the plurality of channels.

The channel is a two-line latch (4) for receiving and storing digital data, a decoder (5) for receiving data from the two-line latch (4) and decoding it, and the output of the decoder (5) The level shifter 6 receives a signal and is connected to a level shifter 6 for raising the level so that the signal can operate at a high voltage, and 256 signal lines divided by voltage in the resistance column of the voltage divider 100 so that the level shifter 6 P-decoder 7 and N-decoder 8, the switch operation of which is selected by the output signal, and a multiplexer which receives the output signals of the P-decoder 7 and N-decoder 8 and multiplies them. 9) and a buffer 10 for buffering an output signal of the multiplexer 9 to output an LCD pixel.

The voltage dividing unit 100 is configured by connecting a plurality of resistors R1 to R255 in series between the high voltage VH255 and the low voltage VH0, and the operation of the conventional device configured as described above will be described.

First, the digital input data applied to the source driver is first stored in the data register of the digital controller 1, and the input data is stored in the two-line latch 4 of each channel.

At this time, the input data is stored in each of the two line latches 4 of each channel by the control signals of the plurality of sheath registers 2 and 3 respectively connected to the six channels. .

Then, the decoder 5 composed of NAND gates receives the input data stored in the two-line latch 4 and decodes it and outputs the decoded signal. The decoded signal is applied to the P-decoder 7 and the N-decoder 8. As a result, an analog value corresponding to the digital input data is obtained. Since the switch selection signal must be a high voltage in the P-decoder 7 and the N-decoder 8, the output signal of the decoder 5 is P-. The voltage level is raised by the level shifter 6 before being applied to the decoder 7 and the N-decoder 8.

At this time, the voltage signal raised by the level shifter 6 selects the switches of the P-decoder 7 and the N-decoder 8.

If the power supply voltage is 10V, the pixel stores the data at the 5V reference voltage, so that when the signal obtained through the source driver is in the 10V range, it becomes ± 5V at the pixel.

On the other hand, the resistor string is composed of two resistor strings to obtain the signal level of two levels, the low level and the high level. Each node value of the resistor string constitutes the signal string so that the P-decoder 7 of all channels is used. And the switch of the N-decoder 8.

Then, the analog value (positive signal or negative signal) of one of the P-decoder 7 and the N-decoder 8 is selected through the multiplexer 9 and this value is transmitted to the pixel through the output buffer 10. do.

However, in the conventional device operating as described above, the resistance area structure in the source driver for converting the pixel pixel data of the source driver increases with the number of bits, so that the chip area of the source driver is greatly increased. There is a problem that the area of the chip is increased by increasing.

Accordingly, an object of the present invention, which was devised in view of the above problems, is to provide an LCD source driver that does not increase the chip area even when the number of bits is increased.

1 is a block diagram showing a configuration of a conventional LCD source driver.

Figure 2 is a block diagram showing the configuration of the present invention the LCD source driver.

FIG. 3 is a circuit diagram showing the configuration of a C-digital / analog converter in FIG. 2. FIG.

***** Description of the symbols for the main parts of the drawings *****

1: Digital control unit 2, 3: Sheath register

4: 2 line latch 5: decoder

6: Level shifter 7: P-decoder

8: N-decoder 9: multiplexer

10: buffer 200: voltage division unit

300: C to Digital / Analog Converter

In order to achieve the above object, the present invention stores a digital data in an internal register when the digital data is input, and outputs the digital data, and receives the digital data of the digital control unit to a higher bit to be converted by a resistor string. A plurality of channels that decode only the analog signal and then convert the analog signal into an analog signal, and each of six channels of the plurality of channels is connected and stores the digital data of the digital control unit in each channel by a latch control signal. A shift register and a voltage divider for dividing the voltage by only the number of resistances to the upper bits for the conversion of the plurality of channels are characterized in that the configuration.

Hereinafter, operations and effects on the LCD source driver according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram showing a configuration of an LCD source driver according to the present invention. As shown in FIG. 2, when digital data is input, the digital controller 1 stores the digital data in an internal register and outputs the digital data. A plurality of channels for receiving digital data of 1) and decoding only the upper bits to be converted by the resistance string, and then converting them into analog signals and outputting the same, and six channels of the plurality of channels. Shift registers 2 and 3 for storing digital data of the digital control unit 1 by a latch control signal, connected to each channel, and conversion of the plurality of channels. To this end, the voltage divider 200 divides the voltage by only the number of resistances for the upper bits.

Each of the plurality of channels includes two line latches 4 for receiving and storing digital data, a decoder for receiving data from the two line latches 4, decoding the data, and an output signal of the decoder. A level shifter 6 which raises the level so that the signal is operable at a high voltage, and an output signal of the level shifter 6, and selects and decodes the voltage across the resistor in the resistor string corresponding to the upper predetermined bit. The P-decoder 7 and the N-decoder 8 and the output signals of the P-decoder 7 and the N-decoder 8 are received and multiplexed according to the polarity to transmit the positive and negative signals accordingly. C-digit which receives the output multiplexer 9, the positive signal and the negative signal of the multiplexer 9, converts it by a switch on / off operation by a lower bit, and divides and charges the capacitors C1 to C3. A full-analog converter 300 and a buffer 10 for buffering and outputting the output signal of the C-digital-analog converter 300 are provided.

The voltage dividing unit 200 is configured by connecting a predetermined number of resistors R1 to R64 corresponding to the predetermined number of upper bits between the high voltage VH64 and the low voltage VH0.

FIG. 3 is a circuit diagram showing the configuration of the C-digital / analog converter 300. As shown in FIG. 3, the positive signal is applied to the node A through the first switch S1, and the negative signal is applied to the second switch. S5) is applied to Node B, a positive signal is applied to Node C through third switch S2, and a third switch S3 is connected between Node A and Node B, and Node B and Node C are connected. A fourth switch S4 is connected therebetween, and the nodes A, B, and C are connected to the node D through the first, second, and third capacitors C1, C2, and C3, respectively. The fifth switch S6 is connected between the node B and the node D, and the output signal Vout is output from the node D. The operation of the present invention configured as described above will be described.

First, the source driver stores the digital input data in the data register of the digital controller 1, and then the digital input data is stored in the corresponding channel of the plurality of channels by the shifting signals of the shift registers 2 and 3. The data stored in the two-line latch 4 is transmitted to the decoder 5 consisting of NAND gates after being stored in the two-line latch 4.

At this time, the data applied to the decoder 5 is not the data of all bits, but only the data of any upper bit that is desired to be converted only by resistance string transformation.

If the number of bits to be converted by the source driver is K bits, the number of bits to be converted in the resistance string conversion is the upper M bit, and the number of bits to be converted in the capacitor string conversion is the lower N bit (M> N due to the operation characteristics). Only the upper M bits of the total K bits output from the two-line latch 4 enter the input of the decoder 5.

2 shows a case in which the number of bits K to be converted is 8 bits, and 6 bits correspond to upper M bits and 2 bits correspond to lower N bits.

Thereafter, the signal decoded by the decoder 5 is applied to the switches of the P-decoder 7 and the N-decoder 8 through the level shifter 6 in the same way as in the prior art in the resistance string corresponding to the upper M bits. The voltage across the resistor is selected.

Then, two signals (positive signal and negative signal) selected in the P-decoder 7 and the N-decoder 8, respectively, a total of four signal lines enter the input of the next multiplexer 9, and the multiplexer ( 9) determines and outputs two signals for each channel according to the polarity of the P-decoder 7 and the N-decoder 8.

Then, the C-digital / analog converter 300 configured as shown in FIG. 3 receives the signal of the multiplexer 9 and operates the plurality of switches S1 to S6 by a lower bit to operate the switch. The bit conversion value is divided into the capacitors C1 to C3 to charge.

Thereafter, the value charged in the capacitors C1 to C3 is output to the outside through the buffer 10.

As described in detail above, the present invention has an effect that the voltage-divided signal lines of the resistor string that occupy most of the source driver chip area are abruptly reduced by the hybrid digital / analog converter structure, thereby reducing the area.

Claims (4)

When digital data is input, it is stored in an internal register and outputs the digital data, and the digital data of the digital control unit is input and decoded only for the higher bits to be converted by a resistor string and then converted into an analog signal. And a plurality of shift registers connected to each of six channels of the plurality of channels and storing the digital data of the digital controller by a latch control signal in each channel, and converting the plurality of channels. An LCD source driver comprising a voltage divider for dividing a voltage by only the number of resistors for the upper number of bits. The channel of claim 1, wherein the channel comprises two line latches for receiving and storing digital data, a decoder for receiving data from the two line latches, and decoding the data; A level shifter which raises the level to be operable, a P-decoder and an N-decoder for receiving the output signal of the level shifter and selecting and decoding a voltage across the resistor in a resistor string corresponding to the upper predetermined bit; A multiplexer that receives the output signals of the decoder and the N-decoder and multiplexes them according to polarity, and outputs the positive and negative signals according to the polarity, and receives the positive and negative signals of the multiplexer and switches them on and off by lower bits. A C-digital / analog converter for converting and charging the capacitor by dividing and charging the capacitor; An LCD source driver, comprising: a buffer configured to buffer and output an output signal of an analog converter. The LCD source driver of claim 1, wherein the voltage divider is formed by connecting a predetermined number of resistors corresponding to an upper predetermined number of bits between the high voltage and the low voltage in series. The method of claim 2, wherein the C-digital / analog converter applies a positive signal to the node A through the first switch, applies a negative signal to the node B, and applies the positive signal to the third switch. Apply to node C, connect a third switch between node A and node B, connect a fourth switch between node B and node C, and connect nodes A, B, and C to the first and second nodes, respectively. And a third switch connected to the node D through a third capacitor, a fifth switch connected between the node B and the node D, and configured to output an output signal from the node D.