US20070216632A1 - Liquid crystal display device and method of driving the same - Google Patents
Liquid crystal display device and method of driving the same Download PDFInfo
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- US20070216632A1 US20070216632A1 US11/646,247 US64624706A US2007216632A1 US 20070216632 A1 US20070216632 A1 US 20070216632A1 US 64624706 A US64624706 A US 64624706A US 2007216632 A1 US2007216632 A1 US 2007216632A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B63—SHIPS OR OTHER WATERBORNE VESSELS; RELATED EQUIPMENT
- B63J—AUXILIARIES ON VESSELS
- B63J2/00—Arrangements of ventilation, heating, cooling, or air-conditioning
- B63J2/12—Heating; Cooling
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B63—SHIPS OR OTHER WATERBORNE VESSELS; RELATED EQUIPMENT
- B63J—AUXILIARIES ON VESSELS
- B63J3/00—Driving of auxiliaries
- B63J2003/001—Driving of auxiliaries characterised by type of power supply, or power transmission, e.g. by using electric power or steam
- B63J2003/002—Driving of auxiliaries characterised by type of power supply, or power transmission, e.g. by using electric power or steam by using electric power
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B63—SHIPS OR OTHER WATERBORNE VESSELS; RELATED EQUIPMENT
- B63J—AUXILIARIES ON VESSELS
- B63J3/00—Driving of auxiliaries
- B63J3/04—Driving of auxiliaries from power plant other than propulsion power plant
- B63J2003/043—Driving of auxiliaries from power plant other than propulsion power plant using shore connectors for electric power supply from shore-borne mains, or other electric energy sources external to the vessel, e.g. for docked, or moored vessels
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
Definitions
- the present invention relates to a liquid crystal display (LCD) device, and more particularly, to a double pixel gate in panel (DGIP) type LCD device and a method of driving the DGIP type LCD device.
- LCD liquid crystal display
- DGIP double pixel gate in panel
- LCD devices are widely used as monitors for laptop computers and desktop computers because of their high resolution, high contrast ratio, color rendering capability and superiority in displaying moving images.
- An LCD device relies on optical anisotropy and polarizability of liquid crystal molecules to produce an image.
- An LCD device includes a liquid crystal display (LCD) panel having two substrates and a liquid crystal layer interposed therebetween and a backlight assembly supplying light to the LCD panel.
- the liquid crystal molecules are aligned along the direction of an electric field generated between electrodes formed on the two respective substrates of the LCD panel.
- LCD liquid crystal display
- AM-LCD active matrix LCD
- TFTs thin film transistors
- pixel electrodes arranged in a matrix form are the subjects of significant research and development because of their high resolution and superior ability in displaying moving images.
- FIG. 1 is a schematic block diagram showing a liquid crystal display device according to the related art.
- a liquid crystal display (LCD) device includes an LCD panel 10 and a driving circuit unit 20 .
- the LCD panel 10 displays images and the driving circuit unit 20 supplies several electric signals for displaying images to the LCD panel 10 .
- the LCD panel 10 includes a first substrate, a second substrate and a liquid crystal layer between the first and second substrates.
- Gate lines 12 and data lines 14 are formed on the first substrate, which is referred to as an array substrate.
- the gate line 12 crosses the data line 14 to define a pixel region “P.”
- a thin film transistor (TFT) “T” is connected to the gate line 12 and the data line 14 , and a pixel region connected to the TFT “T” is formed in the pixel region “P.”
- a color filter layer including red, green and blue color filters is formed on the second substrate, which is referred as to a color filter substrate.
- a common electrode is formed on the color filter layer.
- the liquid crystal layer constitutes a liquid crystal capacitor “Clc” with the pixel electrode and the common electrode.
- the driving circuit unit 20 includes an interface 22 , a timing controller 24 , a gate driver 26 , a data driver 28 , a reference voltage generator 30 and a source voltage generator 32 .
- the interface 22 transmits signals from an external driving system such as a computer to the timing controller 24 .
- the timing controller 24 treats the signals to supply a data signal, a data control signal and a gate control signal to the gate and data drivers 26 and 28 .
- the gate and data drivers 26 and 28 are connected to the gate and data lines 12 and 14 , respectively.
- the gate driver 26 generates a gate signal for turning on/off the TFT “T” of the LCD panel 10 using the gate control signal from the timing controller 24 , and the gate lines 12 are sequentially enabled by the gate signals in each frame.
- the data driver 28 generates gamma voltages using the data signal and the data control signal from the timing controller 24 , and the gamma voltages are supplied to the data lines 14 .
- the TFT “T” is turned on by the gate signal, the gamma voltage corresponding to the data signal is supplied to the corresponding pixel electrode through the TFT “T,” and an electric field generated between the pixel electrode and common electrode drives the liquid crystal layer.
- the reference voltage generator 30 generates a gamma reference voltage for a digital to analog converter (DAC) of the data driver 28 .
- the source voltage generator 32 generates a source voltage for elements of the driving unit 20 and a common voltage for the LCD panel 10 .
- an LCD device when a direct current (DC) voltage is applied to the liquid crystal layer for a long time section, polar impurities in the liquid crystal layer are fixed to interfaces between the liquid crystal layer and one of the first and second substrates due to the electric field. Accordingly, a pretilt angle of the liquid crystal molecules is changed and the liquid crystal layer is not controlled as required, which deteriorate the display quality. To prevent the above deterioration, the LCD device is driven by an inversion method where the polarity of the data signal is inverted in each frame.
- DC direct current
- FIG. 2 is a timing chart showing signals supplied to a liquid crystal display device according to the related art.
- a common voltage “Vcom” is applied to a common electrode and a gate signal “Vgate” is applied to the gate lines.
- a data signal “Vdata” is applied to the data lines and is transmitted to pixel electrodes so that the pixel electrode has a pixel voltage.
- the gate signal “Vgate” having a rectangular wave shape, a gate-high voltage “Vgh” and a gate-low voltage “Vgl” are alternately repeated.
- the gate-high voltage “Vgh” and the gate-low voltage “Vgl” correspond to a turn-on time section and a turn-off time section, respectively.
- the data signal “Vdata” has opposite polarities in two sequential frames. Accordingly, the data signal “Vdata” has a positive polarity (+) during the t th frame, while the data signal “Vdata” has a negative polarity ( ⁇ ) during the (t+1) th frame.
- Vp [Cgd /( Clc+Cst+Cgd )]( Vgh ⁇ Vgl )
- Vp is a pixel voltage difference
- Clc is a capacitance of the liquid crystal capacitor
- Cst is a capacitance of the storage capacitor
- Cgd is a capacitance of the parasitic capacitor of the TFT
- Vgh and Vgl are the gate-high voltage and the gate-low voltage, respectively.
- the pixel voltage difference “ ⁇ Vp” has a deviation according to the position of the pixel electrode in the LCD panel. Accordingly, the pixel voltage is asymmetrically distorted due to the non-uniform pixel voltage difference “ ⁇ Vp,” which causes the deviation in brightness. As a result, a display quality is degraded due to deterioration such as a flicker.
- a driving method where the gate signal “Vgate” is modulated according to a flicker signal having a rectangular wave shape has been suggested. In the driving method using a flicker signal, a rear portion of the gate signal “Vgate” in the turn-on time section has a voltage value lower than the gate-high voltage “Vgh” so that the pixel voltage difference “ ⁇ Vp” can be reduced.
- An LCD device having a relatively low cost has been the subject of recent research and development.
- an LCD device having a reduced number of driving integrated circuits (ICs) has been suggested.
- the reduction in the number of driving ICs may be obtained by reducing the number of data lines.
- DGIP double pixel gate in panel
- FIG. 3 is a schematic view showing a DGIP type LCD device according to the related art.
- a sub pixel region “Psub” and a pixel region “P” are defined in an LCD panel. Red, green and blue colors are displayed in three adjacent sub pixel regions “Psub,” respectively, and the three adjacent sub pixel regions “Psub” constitute a single pixel region “P.”
- the sub pixel regions “Psub” are arranged in a stripe shape where the subs pixel regions “Psub” displaying red “R,” green “G” and blue “B” colors are sequentially repeated along a pixel row and the sub pixel regions displaying the same color are arranged along a pixel column in the LCD panel.
- two adjacent sub pixel regions “Psub” along the pixel row have a single data line in common, and two gate lines are disposed between two adjacent sub pixel regions “Psub” along the pixel column.
- the pixel row is disposed between the m th and (m+1) th gate lines “Gm” and “Gm+1” and between the (m+2) th and (m+3) th gate lines “Gm+2” and “Gm+3,” while the (m+1) th and (m+2) th gate lines “Gm+1” and “Gm+2” are adjacent to each other without the pixel row.
- a gate signal is sequentially supplied to the gate lines “G1, . . . , Gm, Gm+1, Gm+2, . . . ” and a TFT connected to the selected gate line is turned on. Accordingly, a data signal is supplied to the data lines “D1, D2, D3 . . . ” and the sub pixel regions “Psub” are driven by the data signal to display a corresponding color.
- FIG. 4 is a schematic timing chart showing gate signals and a flicker signal supplied to an LCD device according to the related art.
- the m th , (m+1) th , (m+2) th and (m+3) th gate signals “Vgm,” “Vgm+1,” “Vgm+2'and “Vgm+3” are supplied to the m th , (m+1) th , (m+2) th and (m+3) th gate lines “Gm,” “Gm+1,” “Gm+2” and “Gm+3,” respectively.
- the pixel regions “P” in the pixel row may be classified into odd pixel regions “Po” and even pixel regions “Pe” with the left outermost pixel column as a reference. Accordingly, in the pixel row between the m th and (m+1) th gate lines “Gm” and “Gm+1,” the red and blue sub pixel regions “Ro” and “Bo” of the odd pixel regions “Po” and the green sub pixel regions “Ge” of the even pixel region “Pe” are driven by the m th gate signal “Vgm” of the m th gate line “Gm.” Further, the green sub pixel regions “Go” of the odd pixel regions “Po” and the red and blue sub pixel regions “Re” and “Be” of the even pixel regions “Pe” are driven by the (m+1) th gate signal “Vgm+1” of the (m+1) th gate line “Gm+1.” Similarly, in the pixel row between the (m+2) th and (m+
- the m th and (m+2) th gate signals “Vgm” and “Vgm+2” have a time difference of one period “T,” and the (m+1) th and (m+3) th gate signals “Vgm+1” and “Vgm+3” have a time difference of one period “T.”
- the m th and (m+1) th gate signals “Vgm” and “Vgm+1” have a time difference of a half period “T/2.”
- the m th , (m+1) th , (m+2) th and (m+3) th gate signals “Vgm,” “Vgm+1, “Vgm+2” and “Vgm+3” are sequentially delayed by the half period “T/2.”
- the m th , (m+1) th , (m+2) th and (m+3) th gate signals “Vgm,” “Vgm+1,” “Vgm+2” and “Vgm+3” are modulated according to a flicker signal “FLK” to prevent deterioration such as a flicker.
- the flicker signal “FLK” is synchronized with the m th gate signal “Vgm,” the m th and (m+2) th gate signals “Vgm” and “Vgm+2” having the one period “T” are modulated such that rear portions “a” of the m th and (m+2) th gate signals “Vgm” and “Vgm+2” in the turn-on time section have a voltage value lower than the gate-high voltage “Vgh.”
- the deterioration such as a flicker is prevented in the sub pixel regions “Psub” connected to the m th and (m+2) th gate lines “Gm” and “Gm+2.”
- the gate signal modulation in the front portion of the turn-on time section causes brightness reduction in the sub pixel regions “Psub” connected to the (m+1) th and (m+3) th gate lines “Gm+1” and “Gm+3,” thereby degrading the display quality.
- the present invention is directed to a liquid crystal display device and a method of driving the same that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
- An object of the present invention is to provide a liquid crystal device where the display quality degradation due to an erroneous gate signal modulation is prevented and a method of driving the liquid crystal display device using a flicker signal.
- a liquid crystal display device includes: a liquid crystal panel; a m th gate line, a (m+1) th gate line, a (m+2) th gate line and a (m+3) th gate line in the liquid crystal panel, wherein m is a natural number; at least one data line crossing the m th gate line, the (m+1) th gate line, the (m+2) th gate line and the (m+3) th gate line; a timing controller generating a data signal, a control signal, a first flicker signal and a second flicker signal; a gate driver generating a m th gate signal and a (m+2) th gate signal using the first flicker signal and generating a (m+1) th gate signal and a (m+3) th gate signal using the second flicker signal, the m th gate signal and the (m+2) th gate signal being supplied to the
- a method of driving a liquid crystal display device including a m th gate line, a (m+1) th gate line, a (m+2) th gate line, a (m+3) th gate line and at least one data line crossing the m th gate line, the (m+1) th gate line, the (m+2) th gate line and the (m+3) th gate line, includes: supplying a m th gate signal and a (m+2) th gate signal modulated with a first flicker signal to the m th gate line and the (m+2) th gate line, respectively; and supplying a (m+1) th gate signal and a (m+3) th gate signal modulated with a second flicker signal to the (m+1) th gate line and the (m+3) th gate line, respectively.
- a driver for a liquid crystal display device includes: a timing controller generating a first flicker signal and a second flicker signal; and a gate driver generating a m th gate signal and a (m+2) th gate signal using the first flicker signal and generating a (m+1) th gate signal and a (m+3) th gate signal using the second flicker signal, the m th gate signal and the (m+2) th gate signal being supplied to a m th gate line and a (m+2) th gate line, respectively, the (m+1) th gate signal and the (m+3) th gate signal being supplied to a (m+1) th gate line and a (m+3) th gate line, respectively, wherein m is a natural number.
- FIG. 1 is a schematic block diagram showing a liquid crystal display device according to the related art.
- FIG. 2 is a timing chart showing signals supplied to a liquid crystal display device according to the related art.
- FIG. 3 is a schematic view showing a DGIP type LCD device according to the related art.
- FIG. 4 is a schematic timing chart showing gate signals and a flicker signal supplied to an LCD device according to the related art.
- FIG. 5 is a schematic view showing a DGIP type LCD device according to an embodiment of the present invention.
- FIG. 6 is a schematic timing chart showing gate signals and a flicker signal supplied to an LCD device according to an embodiment of the present invention.
- FIG. 7 is a schematic block diagram showing a gate driver in an LCD device according to an embodiment of the present invention.
- FIG. 5 is a schematic view showing a DGIP type LCD device according to an embodiment of the present invention.
- a liquid crystal display (LCD) device includes a liquid crystal display (LCD) panel 50 and a data driver 82 connected to the LCD panel 50 . Since the LCD panel 50 has a double pixel gate in panel (DGIP) type, a gate driver 62 is integrated in the LCD panel 50 . Although not shown in FIG. 5 , the LCD panel 50 includes a first substrate, a second substrate and a liquid crystal layer between the first and second substrates. A plurality of gate lines “G1, . . . , Gm, Gm+1, Gm+2, Gm+3, . . . ” and a plurality of data lines “D1, D2, D3, D4, . . . ” are formed on the first substrate.
- DGIP double pixel gate in panel
- the plurality of gate lines “G1, . . . , Gm, Gm+1, Gm+2, Gm+3, . . . ” (m is a natural number) and the plurality of data lines “D1, D2, D3, D4, . . . ” are arranged in a matrix manner to define pixel rows “PR” and pixel columns “PC.”
- a thin film transistor (TFT) “T” is connected to the gate line and the data line, and a pixel electrode (not shown) is connected to the TFT “T.”
- a color filter layer having red, green and blue color filters and a common electrode are formed on the second substrate.
- the pixel electrode, the common electrode and the liquid crystal layer between the pixel electrode and the common electrode constitute a liquid crystal capacitor (not shown).
- a sub pixel region “Psub” and a pixel region “P” are defined in the LCD panel 50 . Red, green and blue colors are displayed in three adjacent sub pixel regions “Psub,” respectively, and the three adjacent sub pixel regions “Psub” constitute the single pixel region “P.”
- the sub pixel regions “Psub” are arranged in a stripe shape where the subs pixel regions “Psub” displaying red “R,” green “G” and blue “B” colors are sequentially repeated in the pixel row “PR” and the sub pixel regions “Psub” displaying the same color are arranged in the same pixel column “PC.”
- two adjacent sub pixel regions “Psub” in the pixel row “PR” have a single data line in common, and two gate lines are disposed between two adjacent sub pixel regions “Psub” in the pixel column “PC.” Accordingly, the two adjacent pixel columns “PC” are disposed at both sides of the single data line, and the two adjacent gate lines are disposed between the two adjacent pixel rows “PR.”
- the pixel row “PR” is disposed between the m th and (m+1) th gate lines “Gm” and “Gm+1” and between the (m+2) th and (m+3) th gate lines “Gm+2” and “Gm+3,” while the (m+1) th and (m+ 2 ) th gate lines “Gm+1” and “Gm+2” are adjacent to each other without the pixel row “PR.”
- the pixel regions “P” in the pixel row “PR” may be classified into odd pixel regions “Po” and even pixel regions “Pe” with the left outermost pixel column as a reference.
- the odd and even pixel regions “Po” and “Pe” are alternately disposed in the pixel row “PR.” Accordingly, in the pixel row “PR” between the m th and (m+1) th gate lines “Gm” and “Gm+1,” the red and blue sub pixel regions “Ro” and “Bo” of the odd pixel regions “Po” and the green sub pixel regions “Ge” of the even pixel region “Pe” are connected to the m th gate line “Gm.” Further, the green sub pixel regions “Go” of the odd pixel regions “Po” and the red and blue sub pixel regions “Re” and “Be” of the even pixel regions “Pe” are connected to the (m+1) th gate line “Gm+1.” Similarly, in the pixel row between the (m
- the red and green sub pixel regions “Ro” and “Go” of the odd pixel regions “Po” are connected to the first data line “D1.” Further, the blue sub pixel region “Bo” of the odd pixel region “Po” and the red sub pixel region “Re” of the even pixel region “Pe” are connected to the second data line “D2,” and the green and blue sub pixel regions “Ge” and “Be” of the even pixel region “Pe” are connected to the third data line “D3.”
- the plurality of gate lines “G1, . . . , Gm, Gm+1, Gm+2, Gm+3, . . . ” are connected to the gate driver 62 , and the plurality of data lines “D1, D2, D3, D4, . . . ” are connected to the data driver 82 .
- a gate signal is sequentially supplied to the gate lines “G1, . . . , Gm, Gm+1, Gm+2, Gm+3, . . . ” and a TFT connected to the selected gate line is turned on. Accordingly, a data signal is supplied to the data lines “D1, D2, D3, D4, . . . ” and the sub pixel regions “Psub” are driven by the data signal to display corresponding colors.
- FIG. 6 is a schematic timing chart showing gate signals and a flicker signal supplied to an LCD device according to an embodiment of the present invention.
- the m th , (m+1) th , (m+2) th and (m+3) th gate signals “Vgm,” “Vgm+1,” Vgm+2 and Vgm+3” are supplied to the m th , (m+1) th , (m+2) th and (m+3) th gate lines “Gm,” “Gm+1,” “Gm+2” and “Gm+3,” respectively.
- the m th and (m+2) th gate signals “Vgm” and “Vgm+2” have a time difference of a period “T,” and the (m+1) th and (m+3) th gate signals “Vgm+1” and “Vgm+3” have a time difference of the period “T.”
- the m th and (m+1) th gate signals “Vgm” and “Vgm+1” have a time difference of a half of the period “T.” (T/2)
- the m th , (m+1) th , (m+2) th and (m+3) th gate signals “Vgm,” “Vgm+1,” “Vgm+2” and “Vgm+3” are sequentially delayed by the half of the period “T.” (T/2)
- Each of the gate signals “Vgm,” “Vgm+1,” “Vgm+2” and “Vgm+3” has a rectangular wave shape except for a rear portion of each of the gate signals.
- a gate-high voltage “Vgh” and a gate-low voltage “Vgl” are alternately repeated.
- the gate-high voltage “Vgh” and the gate-low voltage “Vgl” correspond to a turn-on time section and a turn-off time section, respectively. Accordingly, each of the gate signals “Vgm,” “Vgm+1,” “Vgm+2” and “Vgm+3” has a pulse repeated with a frame as a period.
- the m th , (m+1) th , (m+2) th and (m+3) th gate signals “Vgm,” “Vgm+1, “Vgm+2” and “Vgm+3” are obtained by modulating original gate signals (not shown) having a perfect rectangular wave shape using first and second flicker signals “FLK1” and “FLK2” from a timing controller (not shown).
- the original gate signals have the same timing as the modulated gate signals, respectively.
- the first and second flicker signals “FLK1” and “FLK2” have a rectangular wave shape and a time difference between the first and second flicker signals “FLK1” and “FLK2” is a half of the period “T.” (T/2)
- the first and second flicker signals “FLK1” and “FLK2” are synchronized with the m th and (m+1) th gate signals “Vgm” and “Vgm+1,” respectively.
- the first flicker signal “FLK1” is used for obtaining the m th and (m+2) th gate signals “Vgm” and “Vgm+2,” and the second flicker signal “FLK2” is used for obtaining the (m+1) th and (m+3) th gate signals “Vgm+1” and “Vgm+3.”
- an adjusted time section “a” of each of the m th , (m+1) th , (m+2) th and (m+3) th gate signals “Vgm,” “Vgm+1,” “Vgm+2” and “Vgm+3” in a rear portion of the turn-on time section has a voltage value lower than the gate-high voltage “Vgh” and higher than the gate-low voltage “Vgl.”
- the m th and (m+2) th gate signals “Vgm” and “Vgm+2” are obtained by modulating m th and (m+2) th original gate signals using the first flicker signal “FLK1” synchronized with the m th gate signal “Vgm,” and the (m+1) th and the (m+3) th gate signals “Vgm+1” and “Vgm+3” are obtained by modulating (m+1) th and the (m+3) th original gate signals using the second flicker signal “FLK2” synchronized with the (m+1) th gate signals “Vgm+1.” Since the (m+1) th original gate signal having a time difference of the half of the period “T” (T/2) from the m th original gate signal is modulated using the second flicker signal “FLK2” having a time difference of the half of the period “T” (T/2) from the first flicker signal “FLK1,” the (m+1) th gate signal “Vgm+1”
- each of the m th , (m+1) th , (m+2) th and (m+3) th gate signals “Vgm,” “Vgm+1,” “Vgm+2” and “Vgm+3” has a voltage value lower than the gate-high voltage “Vgh” to reduce the pixel voltage difference “ ⁇ Vp.”
- the voltage value of each of the m th , (m+1) th , (m+2) th and (m+3) th gate signals “Vgm,” “Vgm+1,” “Vgm+2” and “Vgm+3” in the adjusted time section “a” may vary along a curve connecting the gate-high voltage “Vgh” and a voltage between the gate-high and gate-low voltages “Vgh” and “Vgl.”
- an erroneous gate signal modulation is prevented using the first and second flicker signals having a time difference of a half of the time period. As a result, deterioration such as a flicker is prevented and uniformity in brightness is improved.
- FIG. 7 is a schematic block diagram showing a gate driver in an LCD device according to an embodiment of the present invention.
- a gate driver 62 integrated in an LCD device includes a pulse width modulation (PWM) part 64 , a first gate pulse modulation (GPM) part 66 , a second GPM part 68 , a first level shifter (LS) part 70 , a second LS part 72 , a third LS part 74 and a fourth LS part 76 .
- the first, second, third and fourth LS parts 70 , 72 , 74 and 76 are connected to m th , (m+1) th , (m+2) th and (m+3) th gate lines “Gm,” “Gm+1,” “Gm+2” and “Gm+3,” respectively.
- gate driver 62 for the m th , (m+1) th , (m+2) th and (m+3) th gate lines “Gm,” “Gm+1,” “Gm+2” and “Gm+3,” the gate driver may be similarly formed for the other gate lines.
- the PWM part 64 treats a control signal from a timing controller (not shown) to generate first, second, third and fourth clocks “CGm,” “CGm+1,” “CGm+2” and “CGm+3” for original gate signals before modulation and a gate-high voltage “Vgh.”
- the gate-high voltage “Vgh,” the first clock “CGm” and the third clock “CGm+2” are transmitted to the first GPM part 66
- the gate-high voltage “Vgh” and the second clock “CGm+1” and the fourth clock “CGm+3” are transmitted to the second GPM part 68 .
- the first GPM part 66 generates m th and (m+2) th original gate signals (not shown) using the gate-high voltage “Vgh,” the first clock “CGm” and the third clock “CGm+2” from the PWM part 64 , and modulates the m th and (m+2) th original gate signals using the first flicker signal “FLK1” from the timing controller to generate m th and (m+2) th gate signals “Vgm” and “Vgm+2” each having an adjusted time section “a” at a rear portion of the turn-on time section.
- the second GPM part 68 generates (m+1) th and (m+3) th original gate signals (not shown) using the gate-high voltage “Vgh,” the second clock “CGm+1” and the fourth clock “CGm+3” from the PWM part 64 , and modulates the (m+1) th and (m+3) th original gate signals using the second flicker signal “FLK2” from the timing controller to generate (m+1) th and (m+3) th gate signals “Vgm+1” and “Vgm+3” each having an adjusted time section “a” at a rear portion of the turn-on time section. Additional clocks from the timing controller may be supplied to the first and second GPM parts 66 and 68 .
- the m th and (m+2) th gate signals “Vgm” and “Vgm+2” modulated by using the first flicker signal “FLK1” are supplied to the first and third LS parts 70 and 74 , respectively.
- Voltage levels of the m th and (m+2) th gate signals “Vgm” and “Vgm+2” are changed in the in the first and third LS parts 70 and 74 , respectively, and then the voltage level changed m th and (m+2) th gate signals “Vgm” and “Vgm+2” are supplied to the m th and (m+2) th gate lines “Gm” and “Gm+2,” respectively.
- the (m+1) th and (m+3) th gate signals “Vgm+1” and “Vgm+3” modulated by using the second flicker signal “FLK2” are supplied to the second and fourth LS parts 72 and 76 , respectively.
- Voltage levels of the (m+1) th and (m+3) th gate signals “Vgm+1” and “Vgm+3” are changed in the in the second and fourth LS parts 72 and 76 , respectively, and then the voltage level changed (m+1) th and (m+3) th gate signals “Vgm+1” and “Vgm+3” are supplied to the (m+1) th and (m+3) th gate lines “Gm+1” and “Gm+3,” respectively.
- each modulated gate signal has an adjusted time section at a rear portion of the turn-on time section. As a result, a flicker is prevented and uniformity in brightness is improved.
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Abstract
Description
- This Nonprovisional Application claims priority under 35 U.S.C. §119(a) on Patent Application No. 10-2006-0025222 filed in Korea on Mar. 20, 2006, the entire contents of which are hereby incorporated by reference.
- 1. Field of the Invention
- The present invention relates to a liquid crystal display (LCD) device, and more particularly, to a double pixel gate in panel (DGIP) type LCD device and a method of driving the DGIP type LCD device.
- 2. Discussion of the Related Art
- Liquid crystal display (LCD) devices are widely used as monitors for laptop computers and desktop computers because of their high resolution, high contrast ratio, color rendering capability and superiority in displaying moving images. An LCD device relies on optical anisotropy and polarizability of liquid crystal molecules to produce an image. An LCD device includes a liquid crystal display (LCD) panel having two substrates and a liquid crystal layer interposed therebetween and a backlight assembly supplying light to the LCD panel. The liquid crystal molecules are aligned along the direction of an electric field generated between electrodes formed on the two respective substrates of the LCD panel. By refracting and transmitting incident light from a backlight assembly below an LCD panel and controlling the electric field applied to a group of liquid crystal molecules within particular pixel regions, a desired image can be obtained.
- Of the different types of known liquid crystal display (LCD) devices, active matrix LCD (AM-LCD) devices, which have thin film transistors (TFTs) and pixel electrodes arranged in a matrix form, are the subjects of significant research and development because of their high resolution and superior ability in displaying moving images.
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FIG. 1 is a schematic block diagram showing a liquid crystal display device according to the related art. InFIG. 1 , a liquid crystal display (LCD) device includes anLCD panel 10 and adriving circuit unit 20. TheLCD panel 10 displays images and thedriving circuit unit 20 supplies several electric signals for displaying images to theLCD panel 10. - The
LCD panel 10 includes a first substrate, a second substrate and a liquid crystal layer between the first and second substrates.Gate lines 12 anddata lines 14 are formed on the first substrate, which is referred to as an array substrate. Thegate line 12 crosses thedata line 14 to define a pixel region “P.” A thin film transistor (TFT) “T” is connected to thegate line 12 and thedata line 14, and a pixel region connected to the TFT “T” is formed in the pixel region “P.” A color filter layer including red, green and blue color filters is formed on the second substrate, which is referred as to a color filter substrate. A common electrode is formed on the color filter layer. The liquid crystal layer constitutes a liquid crystal capacitor “Clc” with the pixel electrode and the common electrode. - The
driving circuit unit 20 includes aninterface 22, atiming controller 24, agate driver 26, adata driver 28, areference voltage generator 30 and asource voltage generator 32. Theinterface 22 transmits signals from an external driving system such as a computer to thetiming controller 24. Thetiming controller 24 treats the signals to supply a data signal, a data control signal and a gate control signal to the gate anddata drivers data drivers data lines gate driver 26 generates a gate signal for turning on/off the TFT “T” of theLCD panel 10 using the gate control signal from thetiming controller 24, and thegate lines 12 are sequentially enabled by the gate signals in each frame. Thedata driver 28 generates gamma voltages using the data signal and the data control signal from thetiming controller 24, and the gamma voltages are supplied to thedata lines 14. As a result, when the TFT “T” is turned on by the gate signal, the gamma voltage corresponding to the data signal is supplied to the corresponding pixel electrode through the TFT “T,” and an electric field generated between the pixel electrode and common electrode drives the liquid crystal layer. - The
reference voltage generator 30 generates a gamma reference voltage for a digital to analog converter (DAC) of thedata driver 28. In addition, thesource voltage generator 32 generates a source voltage for elements of thedriving unit 20 and a common voltage for theLCD panel 10. - In an LCD device, when a direct current (DC) voltage is applied to the liquid crystal layer for a long time section, polar impurities in the liquid crystal layer are fixed to interfaces between the liquid crystal layer and one of the first and second substrates due to the electric field. Accordingly, a pretilt angle of the liquid crystal molecules is changed and the liquid crystal layer is not controlled as required, which deteriorate the display quality. To prevent the above deterioration, the LCD device is driven by an inversion method where the polarity of the data signal is inverted in each frame.
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FIG. 2 is a timing chart showing signals supplied to a liquid crystal display device according to the related art. InFIG. 2 , a common voltage “Vcom” is applied to a common electrode and a gate signal “Vgate” is applied to the gate lines. In addition, a data signal “Vdata” is applied to the data lines and is transmitted to pixel electrodes so that the pixel electrode has a pixel voltage. In the gate signal “Vgate” having a rectangular wave shape, a gate-high voltage “Vgh” and a gate-low voltage “Vgl” are alternately repeated. The gate-high voltage “Vgh” and the gate-low voltage “Vgl” correspond to a turn-on time section and a turn-off time section, respectively. The data signal “Vdata” has opposite polarities in two sequential frames. Accordingly, the data signal “Vdata” has a positive polarity (+) during the tth frame, while the data signal “Vdata” has a negative polarity (−) during the (t+1)th frame. - In addition, when the gate signal “Vgate” is changed from the gate-high voltage “Vgh” to the gate-low voltage “Vgl” at a border between the turn-on time section and the turn-off time section, the capacitance of the liquid crystal capacitor “Clc” and the pixel voltage are changed due to the charge re-distribution among the TFT “T,” the liquid crystal capacitor “Clc” and a storage capacitor (not shown). A difference in the pixel voltage may be expressed as the following equation.
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ΔVp=[Cgd/(Clc+Cst+Cgd)](Vgh−Vgl) - where ΔVp is a pixel voltage difference, Clc is a capacitance of the liquid crystal capacitor, Cst is a capacitance of the storage capacitor, Cgd is a capacitance of the parasitic capacitor of the TFT, and Vgh and Vgl are the gate-high voltage and the gate-low voltage, respectively.
- The pixel voltage difference “ΔVp” has a deviation according to the position of the pixel electrode in the LCD panel. Accordingly, the pixel voltage is asymmetrically distorted due to the non-uniform pixel voltage difference “ΔVp,” which causes the deviation in brightness. As a result, a display quality is degraded due to deterioration such as a flicker. To prevent the deterioration such as a flicker, a driving method where the gate signal “Vgate” is modulated according to a flicker signal having a rectangular wave shape has been suggested. In the driving method using a flicker signal, a rear portion of the gate signal “Vgate” in the turn-on time section has a voltage value lower than the gate-high voltage “Vgh” so that the pixel voltage difference “ΔVp” can be reduced.
- An LCD device having a relatively low cost has been the subject of recent research and development. For the purpose of reducing the production cost, an LCD device having a reduced number of driving integrated circuits (ICs) has been suggested. For example, the reduction in the number of driving ICs may be obtained by reducing the number of data lines. Accordingly, a double pixel gate in panel (DGIP) type LCD device, where two adjacent pixel electrodes are connected to a single data line, has been suggested.
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FIG. 3 is a schematic view showing a DGIP type LCD device according to the related art. InFIG. 3 , a sub pixel region “Psub” and a pixel region “P” are defined in an LCD panel. Red, green and blue colors are displayed in three adjacent sub pixel regions “Psub,” respectively, and the three adjacent sub pixel regions “Psub” constitute a single pixel region “P.” The sub pixel regions “Psub” are arranged in a stripe shape where the subs pixel regions “Psub” displaying red “R,” green “G” and blue “B” colors are sequentially repeated along a pixel row and the sub pixel regions displaying the same color are arranged along a pixel column in the LCD panel. - In addition, two adjacent sub pixel regions “Psub” along the pixel row have a single data line in common, and two gate lines are disposed between two adjacent sub pixel regions “Psub” along the pixel column. For example, the pixel row is disposed between the mth and (m+1)th gate lines “Gm” and “Gm+1” and between the (m+2)th and (m+3)th gate lines “Gm+2” and “Gm+3,” while the (m+1)th and (m+2)th gate lines “Gm+1” and “Gm+2” are adjacent to each other without the pixel row.
- In the LCD panel, a gate signal is sequentially supplied to the gate lines “G1, . . . , Gm, Gm+1, Gm+2, . . . ” and a TFT connected to the selected gate line is turned on. Accordingly, a data signal is supplied to the data lines “D1, D2, D3 . . . ” and the sub pixel regions “Psub” are driven by the data signal to display a corresponding color.
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FIG. 4 is a schematic timing chart showing gate signals and a flicker signal supplied to an LCD device according to the related art. As shown inFIGS. 3 and 4 , the mth, (m+1)th, (m+2)th and (m+3)th gate signals “Vgm,” “Vgm+1,” “Vgm+2'and “Vgm+3” are supplied to the mth, (m+1)th, (m+2)th and (m+3)th gate lines “Gm,” “Gm+1,” “Gm+2” and “Gm+3,” respectively. The pixel regions “P” in the pixel row may be classified into odd pixel regions “Po” and even pixel regions “Pe” with the left outermost pixel column as a reference. Accordingly, in the pixel row between the mth and (m+1)th gate lines “Gm” and “Gm+1,” the red and blue sub pixel regions “Ro” and “Bo” of the odd pixel regions “Po” and the green sub pixel regions “Ge” of the even pixel region “Pe” are driven by the mth gate signal “Vgm” of the mth gate line “Gm.” Further, the green sub pixel regions “Go” of the odd pixel regions “Po” and the red and blue sub pixel regions “Re” and “Be” of the even pixel regions “Pe” are driven by the (m+1)th gate signal “Vgm+1” of the (m+1)th gate line “Gm+1.” Similarly, in the pixel row between the (m+2)th and (m+3)th gate lines “Gm+2” and “Gm+3,” the red and blue sub pixel regions “Ro” and “Bo” of the odd pixel regions “Po” and the green sub pixel regions “Ge” of the even pixel region “Pe” are driven by the (m+2)th gate signal “Vgm+2” of the (m+2)th gate line “Gm+2.” Further, the green sub pixel regions “Go” of the odd pixel regions “Po” and the red and blue sub pixel regions “Re” and “Be” of the even pixel regions “Pe” are driven by the (m+3)th gate signal “Vgm+3” of the (m+3)th gate line “Gm+3.” - The mth and (m+2)th gate signals “Vgm” and “Vgm+2” have a time difference of one period “T,” and the (m+1)th and (m+3)th gate signals “Vgm+1” and “Vgm+3” have a time difference of one period “T.” In addition, the mth and (m+1)th gate signals “Vgm” and “Vgm+1” have a time difference of a half period “T/2.” As a result, the mth, (m+1)th, (m+2)th and (m+3)th gate signals “Vgm,” “Vgm+1, “Vgm+2” and “Vgm+3” are sequentially delayed by the half period “T/2.”
- The mth, (m+1)th, (m+2)th and (m+3)th gate signals “Vgm,” “Vgm+1,” “Vgm+2” and “Vgm+3” are modulated according to a flicker signal “FLK” to prevent deterioration such as a flicker. Since the flicker signal “FLK” is synchronized with the mth gate signal “Vgm,” the mth and (m+2)th gate signals “Vgm” and “Vgm+2” having the one period “T” are modulated such that rear portions “a” of the mth and (m+2)th gate signals “Vgm” and “Vgm+2” in the turn-on time section have a voltage value lower than the gate-high voltage “Vgh.” As a result, the deterioration such as a flicker is prevented in the sub pixel regions “Psub” connected to the mth and (m+2)th gate lines “Gm” and “Gm+2.” However, the (m+1)th and the (m+3)th gate signals “Vgm+1” and “Vgm+3,” which have a time difference of the half period “T/2” with respect to the mth and (m+2)th gate signals “Vgm” and “Vgm+2,” respectively, are modulated according to the flicker signal “FLK” such that front potions of the (m+1)th and (m+3)th gate signals “Vgm+1” and “Vgm+3” in the turn-on time section have a voltage value lower than the gate-high voltage “Vgh.” The deterioration such as a flicker is not prevented by the gate signal modulation in the front portion of the turn-on time section. Instead, the gate signal modulation in the front portion of the turn-on time section causes brightness reduction in the sub pixel regions “Psub” connected to the (m+1)th and (m+3)th gate lines “Gm+1” and “Gm+3,” thereby degrading the display quality.
- Accordingly, the present invention is directed to a liquid crystal display device and a method of driving the same that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.
- An object of the present invention is to provide a liquid crystal device where the display quality degradation due to an erroneous gate signal modulation is prevented and a method of driving the liquid crystal display device using a flicker signal.
- Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. These and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
- To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a liquid crystal display device includes: a liquid crystal panel; a mth gate line, a (m+1)th gate line, a (m+2)th gate line and a (m+3)th gate line in the liquid crystal panel, wherein m is a natural number; at least one data line crossing the mth gate line, the (m+1)th gate line, the (m+2)th gate line and the (m+3)th gate line; a timing controller generating a data signal, a control signal, a first flicker signal and a second flicker signal; a gate driver generating a mth gate signal and a (m+2)th gate signal using the first flicker signal and generating a (m+1)th gate signal and a (m+3)th gate signal using the second flicker signal, the mth gate signal and the (m+2)th gate signal being supplied to the mth gate line and the (m+2)th gate line, respectively, the (m+1)th gate signal and the (m+3)th gate signal being supplied to the (m+1)th gate line and the (m+3)th gate line, respectively.
- In another aspect, as embodied, a method of driving a liquid crystal display device including a mth gate line, a (m+1)th gate line, a (m+2)th gate line, a (m+3)th gate line and at least one data line crossing the mth gate line, the (m+1)th gate line, the (m+2)th gate line and the (m+3)th gate line, includes: supplying a mth gate signal and a (m+2)th gate signal modulated with a first flicker signal to the mth gate line and the (m+2)th gate line, respectively; and supplying a (m+1)th gate signal and a (m+3)th gate signal modulated with a second flicker signal to the (m+1)th gate line and the (m+3)th gate line, respectively.
- In another aspect, as embodied, a driver for a liquid crystal display device, includes: a timing controller generating a first flicker signal and a second flicker signal; and a gate driver generating a mth gate signal and a (m+2)th gate signal using the first flicker signal and generating a (m+1)th gate signal and a (m+3)th gate signal using the second flicker signal, the mth gate signal and the (m+2)th gate signal being supplied to a mth gate line and a (m+2)th gate line, respectively, the (m+1)th gate signal and the (m+3)th gate signal being supplied to a (m+1)th gate line and a (m+3)th gate line, respectively, wherein m is a natural number.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
-
FIG. 1 is a schematic block diagram showing a liquid crystal display device according to the related art. -
FIG. 2 is a timing chart showing signals supplied to a liquid crystal display device according to the related art. -
FIG. 3 is a schematic view showing a DGIP type LCD device according to the related art. -
FIG. 4 is a schematic timing chart showing gate signals and a flicker signal supplied to an LCD device according to the related art. -
FIG. 5 is a schematic view showing a DGIP type LCD device according to an embodiment of the present invention. -
FIG. 6 is a schematic timing chart showing gate signals and a flicker signal supplied to an LCD device according to an embodiment of the present invention. -
FIG. 7 is a schematic block diagram showing a gate driver in an LCD device according to an embodiment of the present invention. - Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, similar reference numbers will be used to refer to the same or similar parts.
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FIG. 5 is a schematic view showing a DGIP type LCD device according to an embodiment of the present invention. - In
FIG. 5 , a liquid crystal display (LCD) device includes a liquid crystal display (LCD)panel 50 and adata driver 82 connected to theLCD panel 50. Since theLCD panel 50 has a double pixel gate in panel (DGIP) type, agate driver 62 is integrated in theLCD panel 50. Although not shown inFIG. 5 , theLCD panel 50 includes a first substrate, a second substrate and a liquid crystal layer between the first and second substrates. A plurality of gate lines “G1, . . . , Gm, Gm+1, Gm+2, Gm+3, . . . ” and a plurality of data lines “D1, D2, D3, D4, . . . ” are formed on the first substrate. The plurality of gate lines “G1, . . . , Gm, Gm+1, Gm+2, Gm+3, . . . ” (m is a natural number) and the plurality of data lines “D1, D2, D3, D4, . . . ” are arranged in a matrix manner to define pixel rows “PR” and pixel columns “PC.” A thin film transistor (TFT) “T” is connected to the gate line and the data line, and a pixel electrode (not shown) is connected to the TFT “T.” Although not shown inFIG. 5 , a color filter layer having red, green and blue color filters and a common electrode are formed on the second substrate. The pixel electrode, the common electrode and the liquid crystal layer between the pixel electrode and the common electrode constitute a liquid crystal capacitor (not shown). - A sub pixel region “Psub” and a pixel region “P” are defined in the
LCD panel 50. Red, green and blue colors are displayed in three adjacent sub pixel regions “Psub,” respectively, and the three adjacent sub pixel regions “Psub” constitute the single pixel region “P.” The sub pixel regions “Psub” are arranged in a stripe shape where the subs pixel regions “Psub” displaying red “R,” green “G” and blue “B” colors are sequentially repeated in the pixel row “PR” and the sub pixel regions “Psub” displaying the same color are arranged in the same pixel column “PC.” - In the
LCD panel 50, two adjacent sub pixel regions “Psub” in the pixel row “PR” have a single data line in common, and two gate lines are disposed between two adjacent sub pixel regions “Psub” in the pixel column “PC.” Accordingly, the two adjacent pixel columns “PC” are disposed at both sides of the single data line, and the two adjacent gate lines are disposed between the two adjacent pixel rows “PR.” For example, the pixel row “PR” is disposed between the mth and (m+1)th gate lines “Gm” and “Gm+1” and between the (m+2)th and (m+3)th gate lines “Gm+2” and “Gm+3,” while the (m+1)th and (m+2)th gate lines “Gm+1” and “Gm+2” are adjacent to each other without the pixel row “PR.” - The pixel regions “P” in the pixel row “PR” may be classified into odd pixel regions “Po” and even pixel regions “Pe” with the left outermost pixel column as a reference. The odd and even pixel regions “Po” and “Pe” are alternately disposed in the pixel row “PR.” Accordingly, in the pixel row “PR” between the mth and (m+1)th gate lines “Gm” and “Gm+1,” the red and blue sub pixel regions “Ro” and “Bo” of the odd pixel regions “Po” and the green sub pixel regions “Ge” of the even pixel region “Pe” are connected to the mth gate line “Gm.” Further, the green sub pixel regions “Go” of the odd pixel regions “Po” and the red and blue sub pixel regions “Re” and “Be” of the even pixel regions “Pe” are connected to the (m+1)th gate line “Gm+1.” Similarly, in the pixel row between the (m+2)th and (m+3)th gate lines “Gm+2” and “Gm+3,” the red and blue sub pixel regions “Ro” and “Bo” of the odd pixel regions “Po” and the green sub pixel regions “Ge” of the even pixel region “Pe” are connected to the (m+2)th gate line “Gm+2.” Further, the green sub pixel regions “Go” of the odd pixel regions “Po” and the red and blue sub pixel regions “Re” and “Be” of the even pixel regions “Pe” are connected to the (m+3)th gate line “Gm+3.”
- In the pixel columns “PC,” the red and green sub pixel regions “Ro” and “Go” of the odd pixel regions “Po” are connected to the first data line “D1.” Further, the blue sub pixel region “Bo” of the odd pixel region “Po” and the red sub pixel region “Re” of the even pixel region “Pe” are connected to the second data line “D2,” and the green and blue sub pixel regions “Ge” and “Be” of the even pixel region “Pe” are connected to the third data line “D3.”
- The plurality of gate lines “G1, . . . , Gm, Gm+1, Gm+2, Gm+3, . . . ” are connected to the
gate driver 62, and the plurality of data lines “D1, D2, D3, D4, . . . ” are connected to thedata driver 82. A gate signal is sequentially supplied to the gate lines “G1, . . . , Gm, Gm+1, Gm+2, Gm+3, . . . ” and a TFT connected to the selected gate line is turned on. Accordingly, a data signal is supplied to the data lines “D1, D2, D3, D4, . . . ” and the sub pixel regions “Psub” are driven by the data signal to display corresponding colors. -
FIG. 6 is a schematic timing chart showing gate signals and a flicker signal supplied to an LCD device according to an embodiment of the present invention. - In
FIGS. 5 and 6 , the mth, (m+1)th, (m+2)th and (m+3)th gate signals “Vgm,” “Vgm+1,” Vgm+2 and Vgm+3” are supplied to the mth, (m+1)th, (m+2)th and (m+3)th gate lines “Gm,” “Gm+1,” “Gm+2” and “Gm+3,” respectively. The mth and (m+2)th gate signals “Vgm” and “Vgm+2” have a time difference of a period “T,” and the (m+1)th and (m+3)th gate signals “Vgm+1” and “Vgm+3” have a time difference of the period “T.” In addition, the mth and (m+1)th gate signals “Vgm” and “Vgm+1” have a time difference of a half of the period “T.” (T/2) As a result, the mth, (m+1)th, (m+2)th and (m+3)th gate signals “Vgm,” “Vgm+1,” “Vgm+2” and “Vgm+3” are sequentially delayed by the half of the period “T.” (T/2) - Each of the gate signals “Vgm,” “Vgm+1,” “Vgm+2” and “Vgm+3” has a rectangular wave shape except for a rear portion of each of the gate signals. A gate-high voltage “Vgh” and a gate-low voltage “Vgl” are alternately repeated. The gate-high voltage “Vgh” and the gate-low voltage “Vgl” correspond to a turn-on time section and a turn-off time section, respectively. Accordingly, each of the gate signals “Vgm,” “Vgm+1,” “Vgm+2” and “Vgm+3” has a pulse repeated with a frame as a period.
- The mth, (m+1)th, (m+2)th and (m+3)th gate signals “Vgm,” “Vgm+1, “Vgm+2” and “Vgm+3” are obtained by modulating original gate signals (not shown) having a perfect rectangular wave shape using first and second flicker signals “FLK1” and “FLK2” from a timing controller (not shown). The original gate signals have the same timing as the modulated gate signals, respectively. The first and second flicker signals “FLK1” and “FLK2” have a rectangular wave shape and a time difference between the first and second flicker signals “FLK1” and “FLK2” is a half of the period “T.” (T/2) In addition, the first and second flicker signals “FLK1” and “FLK2” are synchronized with the mth and (m+1)th gate signals “Vgm” and “Vgm+1,” respectively. The first flicker signal “FLK1” is used for obtaining the mth and (m+2)th gate signals “Vgm” and “Vgm+2,” and the second flicker signal “FLK2” is used for obtaining the (m+1)th and (m+3)th gate signals “Vgm+1” and “
Vgm+ 3.” Accordingly, an adjusted time section “a” of each of the mth, (m+1)th, (m+2)th and (m+3)th gate signals “Vgm,” “Vgm+1,” “Vgm+2” and “Vgm+3” in a rear portion of the turn-on time section has a voltage value lower than the gate-high voltage “Vgh” and higher than the gate-low voltage “Vgl.” - Therefore, the mth and (m+2)th gate signals “Vgm” and “Vgm+2” are obtained by modulating mth and (m+2)th original gate signals using the first flicker signal “FLK1” synchronized with the mth gate signal “Vgm,” and the (m+1)th and the (m+3)th gate signals “Vgm+1” and “Vgm+3” are obtained by modulating (m+1)th and the (m+3)th original gate signals using the second flicker signal “FLK2” synchronized with the (m+1)th gate signals “
Vgm+ 1.” Since the (m+1)th original gate signal having a time difference of the half of the period “T” (T/2) from the mth original gate signal is modulated using the second flicker signal “FLK2” having a time difference of the half of the period “T” (T/2) from the first flicker signal “FLK1,” the (m+1)th gate signal “Vgm+1” has the adjusted time section “a” at the rear portion of the turn-on time section instead at the front portion of the turn-on time section as in the related art. - In the adjusted time section “a,” each of the mth, (m+1)th, (m+2)th and (m+3)th gate signals “Vgm,” “Vgm+1,” “Vgm+2” and “Vgm+3” has a voltage value lower than the gate-high voltage “Vgh” to reduce the pixel voltage difference “ΔVp.” For example, the voltage value of each of the mth, (m+1)th, (m+2)th and (m+3)th gate signals “Vgm,” “Vgm+1,” “Vgm+2” and “Vgm+3” in the adjusted time section “a” may vary along a curve connecting the gate-high voltage “Vgh” and a voltage between the gate-high and gate-low voltages “Vgh” and “Vgl.” Thus, the voltage value of each of the mth, (m+1)th, (m+2)th and (m+3)th gate signals “Vgm,” “Vgm+1,” “Vgm+2” and “Vgm+3” may nonlinearly vary from the gate-high voltage “Vgh” to the voltage between the gate-high and gate-low voltages “Vgh” and “Vgl” in the adjusted time section “a.”
- In the LCD device according to an embodiment of the present invention, an erroneous gate signal modulation is prevented using the first and second flicker signals having a time difference of a half of the time period. As a result, deterioration such as a flicker is prevented and uniformity in brightness is improved.
-
FIG. 7 is a schematic block diagram showing a gate driver in an LCD device according to an embodiment of the present invention. - In
FIG. 7 , agate driver 62 integrated in an LCD device includes a pulse width modulation (PWM)part 64, a first gate pulse modulation (GPM)part 66, asecond GPM part 68, a first level shifter (LS)part 70, asecond LS part 72, athird LS part 74 and afourth LS part 76. The first, second, third andfourth LS parts FIG. 7 show thegate driver 62 for the mth, (m+1)th, (m+2)th and (m+3)th gate lines “Gm,” “Gm+1,” “Gm+2” and “Gm+3,” the gate driver may be similarly formed for the other gate lines. - The
PWM part 64 treats a control signal from a timing controller (not shown) to generate first, second, third and fourth clocks “CGm,” “CGm+1,” “CGm+2” and “CGm+3” for original gate signals before modulation and a gate-high voltage “Vgh.” The gate-high voltage “Vgh,” the first clock “CGm” and the third clock “CGm+2” are transmitted to thefirst GPM part 66, while the gate-high voltage “Vgh,” and the second clock “CGm+1” and the fourth clock “CGm+3” are transmitted to thesecond GPM part 68. - The
first GPM part 66 generates mth and (m+2)th original gate signals (not shown) using the gate-high voltage “Vgh,” the first clock “CGm” and the third clock “CGm+2” from thePWM part 64, and modulates the mth and (m+2)th original gate signals using the first flicker signal “FLK1” from the timing controller to generate mth and (m+2)th gate signals “Vgm” and “Vgm+2” each having an adjusted time section “a” at a rear portion of the turn-on time section. In addition, thesecond GPM part 68 generates (m+1)th and (m+3)th original gate signals (not shown) using the gate-high voltage “Vgh,” the second clock “CGm+1” and the fourth clock “CGm+3” from thePWM part 64, and modulates the (m+1)th and (m+3)th original gate signals using the second flicker signal “FLK2” from the timing controller to generate (m+1)th and (m+3)th gate signals “Vgm+1” and “Vgm+3” each having an adjusted time section “a” at a rear portion of the turn-on time section. Additional clocks from the timing controller may be supplied to the first andsecond GPM parts - The mth and (m+2)th gate signals “Vgm” and “Vgm+2” modulated by using the first flicker signal “FLK1” are supplied to the first and
third LS parts third LS parts fourth LS parts fourth LS parts - Consequently, in the DGIP type LCD device according to the illustrated embodiments of the present invention, the display quality deterioration due to erroneous gate signal modulation is alleviated. Specifically, since the original gate signals having a time difference of a half of one period are modulated by two flicker signals having a time difference of the half of one period, respectively, each modulated gate signal has an adjusted time section at a rear portion of the turn-on time section. As a result, a flicker is prevented and uniformity in brightness is improved.
- It will be apparent to those skilled in the art that various modifications and variations can be made in the liquid crystal display device and the method of driving the liquid crystal display device of the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Claims (34)
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KR1020060025222A KR101235698B1 (en) | 2006-03-20 | 2006-03-20 | Liquid Crystal Display device and display methode using the same |
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Also Published As
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JP4668892B2 (en) | 2011-04-13 |
CN101042479A (en) | 2007-09-26 |
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KR20070095044A (en) | 2007-09-28 |
US7764262B2 (en) | 2010-07-27 |
KR101235698B1 (en) | 2013-02-21 |
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