US20070210337A1 - Contact hole formation method - Google Patents

Contact hole formation method Download PDF

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US20070210337A1
US20070210337A1 US11798122 US79812207A US2007210337A1 US 20070210337 A1 US20070210337 A1 US 20070210337A1 US 11798122 US11798122 US 11798122 US 79812207 A US79812207 A US 79812207A US 2007210337 A1 US2007210337 A1 US 2007210337A1
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film
bpsg
formed
dielectric
gate
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Tetsuya Matsutani
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Tetsuya Matsutani
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819Smoothing of the dielectric
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76828Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. thermal treatment
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

Abstract

A contact hole formation method includes a process of depositing a BPSG film 4 on a semiconductor substrate 1 on which transistors are formed, a process of planarizing the BPSG film 4, a process of depositing a dielectric film 5 on the BPSG film 4, and a process of forming contact holes 8 through the BPSG film 4 and the dielectric film 5 so as to reach the semiconductor substrate 1, in a case in which gate electrodes are densely formed in some areas and sparsely formed in other areas. The above-described contact hole formation method allows a thickness of the BPSG film 4 to be uniform irrespective of the density of the gate electrodes, whereby an etching rate becomes uniform over the entire area of the semiconductor device. Thus, it is possible to form contact holes having minimized variations in a contact resistance and a value of leakage current.

Description

    BACKGROUND OF THE INVENTION
  • [0001]
    1. Field of the Invention
  • [0002]
    The present invention relates to a contact hole formation method. More particularly, the present invention relates to a method for forming contact holes in an area in which gate electrodes are densely formed and an area in which gate electrodes are sparsely formed.
  • [0003]
    2. Description of the Background Art
  • [0004]
    In recent years, a width of a gate electrode and a pitch between the gate electrodes has become increasingly narrow with the achievement of a high degree of integration of a semiconductor device. Specifically, if a process rule is equal to or smaller than 0.18 μm, the minimum space between adjacent gate electrodes is approximately 0.3 μm, which is extremely narrow. As a result, in the case where the above-described narrow space between the adjacent gate electrodes is filled with an interlayer dielectric, there arises a problem of void formation in the interlayer dielectric between the adjacent gate electrodes.
  • [0005]
    Therefore, heat treatment is performed for the interlayer dielectric in order to eliminate voids formed between the adjacent gate electrodes. The heat treatment is a process performed for reflowing the interlayer dielectric by heating the interlayer dielectric. The above-described process allows the voids formed between the adjacent gate electrodes to be eliminated.
  • [0006]
    As a material of the interlayer dielectric for which the above-described heat treatment is performed, it is preferable to use a material which is softened at a low temperature. Because the material softens at a low temperature, transistor characteristics are prevented from being impaired by exposure to an elevated temperature during the heat treatment. For that reason, a boron phosphorous silicate glass (BPSG) film, which reflows at approximately 800 degrees centigrade, is used as the interlayer dielectric. Note that the BPSG film is a dielectric film made out of a silicon oxide film doped with boron (B) and phosphorus (P).
  • [0007]
    Hereinafter, referring to the drawings, a conventional method for forming contact holes in a semiconductor device using the above-described BPSG film as an interlayer dielectric is described. FIGS. 5A to 5D are cross section views of a semiconductor device in the process of opening contact holes. Before contact holes are opened through the semiconductor device, transistors are formed on a silicon substrate, and an interlayer dielectric is further formed thereon. Note that a cross section view shown in FIG. 5 illustrates a portion of the semiconductor device which functions as a switching device used in a memory, etc.
  • [0008]
    First, MOS field effect transistors are formed on a silicon substrate 1. Specifically, a gate oxide film (not shown) is formed, and gate electrodes 2 (for example, a polysilicon film) are formed on the gate oxide film. A source region (not shown) and a drain region (not shown) are formed after formation of a gate oxide film (not shown), gate electrodes 2 (for example, a polysilicon film), and side walls 3 (for example, a TEOS film)
  • [0009]
    Next, a BPSG film 4 is deposited on the gate electrode 2 as an interlayer dielectric. Then, heat treatment is performed for the BPSG film 4 in order to reflow the BPSG film 4. Thus, voids formed between the adjacent gate electrodes 2 are eliminated to the outside of the BPSG film 4. A cross section view of the semiconductor device after the above-described process is shown in FIG. 5A. After completion of the heat treatment, a non-doped oxide film 5 such as a TEOS film, for example, is deposited on the BPSG film 4.
  • [0010]
    Here, the non-doped oxide film 5 is deposited on the BPSG film 4 for the following reason. The BPSG film 4 is highly hygroscopic. Specifically, when the BPSG film 4 is exposed to the air, boron or phosphorus contained in the BPSG film 4 reacts with water in the air. As a result, compounds of boron, phosphorus, and oxygen, such as BPO4, B2O3, and PO4, for example, are formed and precipitated on the BPSG film 4. The above-described compounds are foreign substances on the BPSG film 4, and substantially reduce yield in the subsequent semiconductor device manufacturing process. Thus, the non-doped oxide film 5, which functions as a protective coat, is deposited on the BPSG film 4 so as to prevent the BPSG film 4 from being exposed to the air.
  • [0011]
    After deposition of the non-doped oxide film 5 is completed, a surface of the non-doped oxide film 5 is planarized by means of chemical-mechanical polishing (CMP) as shown in FIG. 5B. The above-described planarization is performed so that a photoresist can be accurately formed on the non-doped oxide film 5 in the following process.
  • [0012]
    Next, a photoresist 6 having an opening 7 is formed on the planarized non-doped oxide film 5 by photolithography. FIG. 5C illustrates the cross section view of the semiconductor device after the above-described process.
  • [0013]
    Next, as shown in FIG. 5D, dry etching is performed for the non-doped oxide film 5 and the BPSG film 4 using the photoresist 6 as a protective mask for opening a contact hole 8. After the above-described dry etching, the contact hole 8 is filled with metal (for example, tungsten), thereby completing formation of a contact connecting the transistor in the silicon substrate 1 and an interconnection (not shown) formed in an upper layer.
  • [0014]
    Note that the gate electrodes 2 of the respective transistors are not formed at regular intervals on the silicon substrate 1. As a result, on the silicon substrate 1, gate electrodes 2 are densely formed in some areas and sparsely formed in other areas. The above-described two types of areas, that is, an area in which the gate electrodes 2 are densely formed and an area in which the gate electrodes 2 are sparsely formed, will cause the following problem, which will be described in a concrete manner with reference to the drawings. FIG. 6 is a cross section view of a semiconductor device having an area in which the gate electrodes 2 are densely formed and an area in which the gate electrodes 2 are sparsely formed.
  • [0015]
    First, as described in FIG. 5A, the BPSG film 4 is formed on the silicon substrate 1 and reflowed by the heat treatment, whereby the voids in the BPSG film 4 are eliminated and the surface of the BPSG film 4 is planarized.
  • [0016]
    However, if the gate electrodes 2 are densely formed in some areas and sparsely formed in other areas, the surface of the BPSG film 4 becomes uneven, as shown in FIG. 6, because density of the gate electrodes 2 varies from area to area even after the above-described heat treatment is performed. Specifically, in the area in which the gate electrodes 2 are densely formed, a film thickness De of the BPSG film 4 becomes thick. On the other hand, in the area in which the gate electrodes 2 are sparsely formed, a film thickness Df of the BPSG film 4 becomes thin. As described above, the heat treatment allows the surface of the BPSG film 4 to be planarized in terms of a local area, such as an area in which the gate electrodes 2 are densely formed or an area in which the gate electrodes 2 are sparsely formed. In terms of the entire area of the semiconductor device, however, the surface of the BPSG film 4 is not planarized. If the non-doped oxide film 5 is deposited on the above-described BPSG film 4 whose surface is not evenly planarized, and the surface of the non-doped oxide film 5 is planarized by means of CMP, a layer composed of the BPSG film 4 and the non-doped oxide film 5 is uniform in thickness, but a thickness ratio of the BPSG film 4 to the non-doped oxide film 5 varies from area to area.
  • [0017]
    The above-described variations in the thickness ratio cause the following problem at the time of opening of the contact holes. Specifically, the contact holes are opened by removing the BPSG film 4 and the non-doped oxide film 5 by means of dry etching using CxFy gas (for example, C4F8, C5F8, C4F6). Here, an etching rate of the BPSG film 4 is higher than that of the non-doped oxide film 5. As a result, if a thickness ratio of the BPSG film 4 to the non-doped oxide film 5 varies from area to area on the semiconductor device, an etching rate of the interlayer dielectric (that is, a layer composed of the BPSG film 4 and the non-doped oxide film 5) varies from area to area on the semiconductor device. Due to the above-described variations in the etching rate, the opened contact holes vary in depth from area to area on the semiconductor device.
  • [0018]
    With reference to FIG. 6, a comparison between a depth of a contact hole 8 e opened in an area in which the gate electrodes 2 are densely formed and a depth of a contact hole 8 f opened in an area in which the gate electrodes 2 are sparsely formed will be described below in a concrete manner. Note that film thicknesses of the BPSG film 4 and the non-doped oxide film 5 are assumed to be De and de, respectively, in an area in which the gate electrodes 2 are densely formed. On the other hand, film thicknesses of the BPSG film 4 and the non-doped oxide film 5 are assumed to be Df and df, respectively, in an area in which the gate electrodes 2 are sparsely formed. Also, note that there are relationships De>Df and de>df among the above-described four film thicknesses.
  • [0019]
    As shown in FIG. 6, in the area in which the gate electrodes 2 are densely formed, a film of the non-doped oxide film 5 (whose etching rate is relatively higher than that of the BPSG film 4) is thicker, and a film of the BPSG film 4 (whose etching rate is relatively lower than that of the non-doped oxide film 5) is thinner, compared to the area in which the gate electrodes 2 are sparsely formed. As a result, in the area in which the gate electrodes 2 are densely formed, an etching rate of the interlayer dielectric is higher, compared to the area in which the gate electrodes 2 are sparsely formed. Due to the above-described higher etching rate, the bottom of the contact hole 8 e reaches the silicon substrate 1 before the bottom of the contact hole 8 f reaches the silicon substrate 1, in the case where the contact hole 8 e and the contact hole 8 f are concurrently formed. As a result, the silicon substrate 1 is also etched in the area in which the gate electrodes 2 are densely formed. If the silicon substrate 1 is also etched as described above, a leakage current occurs, which results in a malfunction of the semiconductor device. On the other hand, in the area in which the gate electrodes 2 are sparsely formed, there is a likelihood that the bottom of the contact hole will not reach the silicon substrate 1, which results in high incidence of breaks within the semiconductor device.
  • [0020]
    Moreover, the variations in depth of the contact hole, which tapers gently down from an opening to the bottom, results in variations in the area of the bottom of the contact hole, thereby increasing variations in contact resistance.
  • [0021]
    Note that, in the above descriptions, the silicon substrate 1 having an area in which the gate electrodes 2 are densely formed and an area in which the gate electrodes 2 are sparsely formed has been described. However, the same problem will arise in the case where interconnections are formed on the silicon substrate 1. Specifically, in an area in which a distance between interconnections is narrow, deep contact holes are formed, as in the case of the area in which the gate electrodes 2 are densely formed. On the other hand, in an area in which a distance between interconnections is wide, shallow contact holes are formed, as in the case of the area in which the gate electrodes 2 are sparsely formed. Furthermore, a width of the interconnection as well as the distance between the interconnections also affects the depth of the contact hole. Specifically, in an area in which wide interconnections are formed, deep contact holes are formed, as in the case of the area in which the gate electrodes 2 are densely formed. On the other hand, in an area in which narrow interconnections are formed, shallow contact holes are formed, as in the case of the area in which the gate electrodes 2 are sparsely formed.
  • SUMMARY OF THE INVENTION
  • [0022]
    Therefore, an object of the present invention is to provide a method for forming contact holes of uniform depth through a dielectric layer composed of two types of dielectric films having different etching rates, even if transistors are densely formed in some areas and sparsely formed in other areas, or a distance between interconnections is narrow in some areas and wide in other areas, and even if a width of the interconnection varies from area to area on the semiconductor device.
  • [0023]
    The present invention has the following features to attain the object mentioned above.
  • [0024]
    In the present aspect, after deposition of a first dielectric film on a semiconductor substrate having an area in which gate electrodes are densely formed and an area in which gate electrodes are sparsely formed, the first dielectric film is planarized. On the planarized first dielectric film, a second dielectric film whose etching rate is different from an etching rate of the first dielectric film is deposited, and contact holes are formed through the first and second dielectric films. If the first dielectric film is deposited on the semiconductor substrate having variations in the distribution of the gate electrodes, a film thickness of the first dielectric film becomes nonuniform due to the variations in the distribution of the gate electrodes. If the second dielectric film, whose etching rate is different from an etching rate of the first dielectric film, is deposited on the first dielectric film having a nonuniform film thickness, there arises a problem that an etching rate of a dielectric layer composed of the first and second dielectric films varies from area to area on the semiconductor device. As a result, it is difficult to form the contact holes of uniform depth over the entire area of the semiconductor device. Therefore, in the present aspect, thicknesses of the first and second dielectric films are made uniform over the entire area of the semiconductor device by planarizing the first dielectric film, thereby obtaining a uniform etching rate of the dielectric layer composed of the first and second dielectric films over the entire area of the semiconductor device. As a result, it is possible to form the contact holes of uniform depth.
  • [0025]
    The second dielectric film is deposited on the planarized first dielectric film, whereby it is possible to deposit the second dielectric film so as to have a uniform thickness. In order to further improve uniformity of the film thickness of the second dielectric film, the surface of the second dielectric film may be planarized.
  • [0026]
    As the above-described first dielectric film, a BPSG film, for example, is used. The BPSG film is reflowed at approximately 800 degrees centigrade, which is a relatively low temperature. Thus, it is possible to prevent a transistor from being damaged due to a high temperature when eliminating voids formed in the dielectric film by heat treatment.
  • [0027]
    After planarization of the first dielectric film, the second dielectric film is preferably deposited thereon before formation of a precipitate on the surface of the first dielectric film because the above-described precipitate will interfere with the uniform deposition of the second dielectric film. Specifically, the second dielectric film is preferably deposited within 24 hours after planarization of the first dielectric film.
  • [0028]
    If a precipitate is formed on the surface of the first dielectric film before deposition of the second dielectric film, the above-described precipitate may be eliminated. After elimination of the above-described precipitate, it is possible to deposit the second dielectric film of uniform thickness.
  • [0029]
    Also, the contact holes may be formed so as to reach the semiconductor substrate, or formed so as to reach the respective gate electrodes.
  • [0030]
    Furthermore, it is possible to apply the present aspect to a case in which the contact holes are formed in a semiconductor device having an area in which interconnections are densely formed and an area in which interconnections are sparsely formed, or a case in which the contact holes are formed in a semiconductor device on which a plurality of interconnections of different widths are formed.
  • [0031]
    Note that the present aspect is directed to a contact hole formation method, but also directed to a semiconductor device fabricated using the above-described contact hole formation method.
  • [0032]
    These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0033]
    FIGS. 1A to 1E are cross section views of a semiconductor device in a process described in a first embodiment of the present invention;
  • [0034]
    FIG. 2 is a line graph showing a relationship between the length of time that a wafer is left untouched and the number of foreign substances;
  • [0035]
    FIG. 3 is a cross section view of a semiconductor device after contact holes are formed in accordance with a contact hole formation method of the present invention;
  • [0036]
    FIG. 4 is a cross section view of a semiconductor device after contact holes are formed on respective gate electrode interconnections in accordance with the contact hole formation method of the present invention;
  • [0037]
    FIGS. 5A to 5D are cross section views of a semiconductor device processed in accordance with a conventional contact hole formation method; and
  • [0038]
    FIG. 6 is a cross section view of a semiconductor device after contact holes are formed in accordance with the conventional contact hole formation method.
  • DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment
  • [0039]
    Hereinafter, referring to the drawings, a contact hole formation method according to a first embodiment of the present invention will be described. According to the contact hole formation method of the present embodiment, contact holes are opened in a semiconductor device having a silicon substrate on which an interlayer dielectric film composed of a BPSG film layer and a non-doped oxide film layer is deposited. A main feature of the contact hole formation method of the present embodiment is that the BPSG film and the non-doped oxide film, which are deposited on the silicon substrate, are planarized, whereby contact holes of uniform depth can be opened even if the semiconductor device has an area in which gate electrodes of a transistor are densely formed and an area in which gate electrodes are sparsely formed. Here, FIGS. 1A to 1E are cross section views of a semiconductor device in the process of having contact holes opened therein. The semiconductor device shown in FIG. 1 includes the silicon substrate, and transistors formed thereon, and an interlayer dielectric further formed thereon. Note that a cross section views shown in FIG. 1 illustrates a portion of the semiconductor device which functions as a switching device used for a memory, etc.
  • [0040]
    First, MOS field effect transistors are formed on the silicon substrate 1. Specifically, the gate oxide film (not shown) and the gate electrodes 2 (for example, a polysilicon film whose film thickness is approximately 200 nm) are formed. Next, the TEOS film, whose film thickness is approximately 200 nm, is deposited, and the side walls 3 are formed by performing an etch back process for the TEOS film. Then, the source region (not shown) and the drain region (not shown) are formed.
  • [0041]
    Next, on the silicon substrate 1 on which the transistors are formed, the BPSG film 4 functioning as an interlayer dielectric is deposited by means of chemical-vapor deposition (CVD). Note that the BPSG film 4 has a thickness of approximately 1000 nm, and contains about 3.0 wt % of boron (B) and about 5.0 wt % of phosphorus (P).
  • [0042]
    Then, heat treatment is performed for reflowing the BPSG film 4, thereby eliminating voids formed between the adjacent gate electrodes 2 to the outside of the BPSG film 4. Note that the heat treatment is performed, for example, by heating the semiconductor device at approximately 800 degrees centigrade for about 30 minutes. FIG. 1A illustrates the cross section of the semiconductor device after performing the above-described heat treatment.
  • [0043]
    Next, as shown in FIG. 1B, the surface of the BPSG film 4 is planarized by means of CMP. For performing the above-described CMP, various conditions such as processing time, etc., are adjusted so that a film thickness of the planarized BPSG film 4 becomes approximately 600 nm. The CMP allows the BPSG film 4 to have a uniform thickness, irrespective of whether or not there is a gate electrode 2 on the silicon substrate 1, by global planarization of the surface of the BPSG film 4. Note that the above-described process is a main feature of the present invention.
  • [0044]
    Next, as shown in FIG. 1C, the non-doped oxide film 5 is deposited on the surface of the BPSG film 4, which has been planarized by means of CMP. Specifically, the TEOS film, whose film thickness is approximately 50 nm, is deposited by means of CVD. Here, when the surface of the BPSG film 4 is exposed to the air, boron or phosphorus contained in the BPSG film 4 reacts with water in the air. As a result, compounds such as BPO4, B2O3, and PO4, for example, are formed and precipitated on the surface of the BPSG film 4. The above-described compounds are foreign substances on the surface of the BPSG film 4, and substantially reduce yield in the subsequent semiconductor device manufacturing process. Thus, the non-doped oxide film 5, which functions as a protective coat, is deposited on the BPSG film 4.
  • [0045]
    As described above, when the surface of the BPSG film 4 is exposed to the air, compounds such as BPO4, B2O3, and PO4, for example, are precipitated on the surface of the BPSG film 4 as foreign substances. Thus, it is necessary to deposit the non-doped oxide film 5 immediately after the BPSG film 4 is planarized by means of CMP. Hereinafter, with reference to the drawing, a time limit to deposit the non-doped oxide film 5 after planarization of the surface of the BPSG film 4 will be described. FIG. 2 is a line graph showing a relationship between the length of time that an 8-inch wafer is left untouched and the number of foreign substances when the wafer is left untouched in a clean room generally used for manufacturing the semiconductor device. Specifically, the horizontal axis of the graph indicates the length of time that the wafer is left untouched after planarization of the BPSG film 4, and the vertical axis indicates the number of foreign substances per wafer.
  • [0046]
    As shown in FIG. 2, the number of foreign substances is sharply increased after a lapse of 48 hours after planarization of the BPSG film 4. Thus, in this embodiment, allowing for a margin of a certain amount of time, the non-doped oxide film 5 (for example, a TEOS film) is deposited within about 24 hours after planarization of the BPSG film 4 by means of CMP. As a result, it is possible to prevent the formation of foreign substances on the planarized BPSG film 4, and to deposit the non-doped oxide film 5 so as to be more uniform than before.
  • [0047]
    After deposition of the non-doped oxide film 5, the photoresist 6 having an opening 7 in a predetermined area as shown in FIG. 1D is formed on the non-doped oxide film 5 by photolithography.
  • [0048]
    Next, as shown in FIG. 1E, dry etching is performed using the photoresist 6 as a protective mask for opening a contact hole 8 penetrating through the BPSG film 4 and the non-doped oxide film 5 and reaching the silicon substrate 1. For the above-described dry etching, CxFy gas (for example, C4F8, C5F8, C4F6) is used.
  • [0049]
    Then, ashing, etc., is performed for removing the photoresist 6, and the contact hole 8 is filled with metal (for example, tungsten) . Specifically, the contact hole 8 is filled with metal by means of CVD or plating, etc., and the excess metal is removed by means of CMP, thereby completing formation of a contact electrically connecting an interconnection (not shown) formed in an upper layer and the transistor, etc., on the silicon substrate 1.
  • [0050]
    Here, the effects obtained from planarization of the BPSG film 4 will be described with reference to the drawing. Note that the planarization of the BPSG film 4 is a main feature of the contact hole formation method according to the present embodiment. FIG. 3 is a cross section view of a semiconductor device after contact holes are formed through the interlayer dielectric in accordance with a contact hole formation method of the present embodiment.
  • [0051]
    As aforementioned, in the present embodiment, the non-doped oxide film 5 is deposited on the planarized BPSG film 4, and the non-doped oxide film 5 is also planarized. Thus, it is possible to form the BPSG film 4 and the non-doped oxide film 5 each having a uniform thickness over the entire area of the semiconductor device as shown in FIG. 3, irrespective of whether the gate electrodes 2 formed on the silicon substrate 1 are densely or sparsely distributed. Specifically, a film thickness Da of the BPSG film 4 in an area in which the gate electrodes 2 are densely formed is equal to a film thickness Db of the BPSG film 4 in an area in which the gate electrodes 2 are sparsely formed, and a film thickness da of the non-doped oxide film 5 in the area in which the gate electrodes 2 are densely formed is equal to a film thickness db of the non-doped oxide film 5 in the area in which the gate electrodes 2 are sparsely formed. Thus, it is possible to equalize an etching rate of the interlayer dielectric (in this embodiment, a dielectric layer composed of the BPSG film 4 and the non-doped oxide film 5) over the entire area of the semiconductor device. As a result, it is possible to open a plurality of contact holes of uniform depth in the entire area of a dielectric film by means of dry etching. The above-described dielectric film is composed of more than 1 type of dielectric film each having different etching rates, and deposited on the silicon substrate 1 having an area in which the gate electrodes 2 are densely formed and an area in which the gate electrodes 2 are sparsely formed. Thus, the contact hole formation method according to the present embodiment can prevent the following adverse phenomenon, for example, a phenomenon in which leakage of current occurs because the substrate is also etched due to an increased etching rate in an area in which the gate electrodes 2 are densely formed, or a phenomenon in which an interconnection between the semiconductor device and its lower layer tends to be broken because the bottom of the contact hole does not reach the substrate due to a reduced etching rate in an area in which the gate electrodes 2 are sparsely formed.
  • [0052]
    Also, a uniform etching rate allows the contact holes of the same depth to be opened in the semiconductor device in the same etching time, thereby reducing variations in the area of the bottom of the contact hole and minimizing variations in contact resistance. As a result, it is possible to form the contact holes of uniform depth over the entire area of the semiconductor device irrespective of whether the gate electrodes 2 are densely or sparsely distributed.
  • Second Embodiment
  • [0053]
    A contact hole formation method according to a second embodiment differs from the contact hole formation method according to the first embodiment in that a cleaning process is additionally included. Specifically, in the present embodiment, after planarization of the surface of the BPSG film 4 (see FIG. 1B), the surface of the BPSG film 4 is cleaned with a chemical solution such as acid, for example, before deposition of the non-doped oxide film 5 (see FIG. 1C). Note that processes of the second embodiment are identical to those described in the first embodiment except for the above-described cleaning process. Hereinafter, a contact hole formation method according to the second embodiment will be described with reference to the drawing.
  • [0054]
    First, MOS field effect transistors are formed on the silicon substrate 1. Specifically, the gate oxide film (not shown) and the gate electrodes 2 (for example, a polysilicon film whose film thickness is approximately 200 nm) are formed. Next, the TEOS film, whose film thickness is approximately 200 nm, is deposited, and the side walls 3 are formed by performing an etch back process for the TEOS film. Then, the source region (not shown) and the drain region (not shown) are formed.
  • [0055]
    Next, on the silicon substrate 1 on which the transistors are formed, the BPSG film 4 functioning as an interlayer dielectric is deposited by means of chemical-vapor deposition (CVD). Note that the BPSG film 4 has a thickness of approximately 1000 nm, and contains about 3.0 wt % of boron (B) and about 5.0 wt % of phosphorus (P).
  • [0056]
    Then, heat treatment is performed for reflowing the BPSG film 4, thereby eliminating voids formed between the adjacent gate electrodes 2 to the outside of the BPSG film 4. Note that the above-described heat treatment is performed, for example, by heating the semiconductor device at approximately 800 degrees centigrade for about 30 minutes. FIG. 1A illustrates the cross section of the semiconductor device after the above-described heat treatment is performed. Note that the processes as described above are identical to those of the first embodiment.
  • [0057]
    Next, as shown in FIG. 1B, the surface of the BPSG film 4 is planarized by means of CMP. For performing the above-described CMP, various conditions such as processing time, etc., are adjusted so that a film thickness of the planarized BPSG film 4 becomes approximately 600 nm. The CMP allows the BPSG film 4 to have a uniform thickness, irrespective of whether or not there is the gate electrode 2, by global planarization of the surface of the BPSG film 4. Note that the above-described process is also identical to that of the first embodiment.
  • [0058]
    After completion of CMP, the surface of the BPSG film 4 is cleaned with the chemical solution such as acid, for example, for eliminating impurities. Specifically, the semiconductor device is immersed in sulfuric acid at approximately 110 degrees centigrade for cleaning the surface of the BPSG film 4. Then, sulfuric acid coating the semiconductor device is washed off with water, and the semiconductor device is dried.
  • [0059]
    Here, the above-described cleaning process is described in detail. As shown in FIG. 2, after planarization of the surface of the BPSG film 4, if 24 hours or more have elapsed before the non-dopes oxide film 5 is deposited in the next process (FIG. 1C), boron (B) or phosphorus (P) contained in the BPSG film 4 may react with oxygen in the air to form and precipitate compounds such as BPO4, B2O3, and PO4, for example, in large quantity on the surface of the BPSG film 4. Therefore, if the above-described compounds are precipitated on the surface of the BPSG film 4 during a time period from planarization of the surface of the BPSG film 4 to deposition of the non-doped oxide film 5, the precipitated compounds have to be eliminated. Thus, in the present embodiment, the surface of the BPSG film 4 is cleaned with the chemical solution such as acid, etc., which dissolves the compounds such as BPO4, B2O3, and PO4, for example. Note that, as acid for dissolving the above-described compounds, hydrochloric acid, nitric acid, or hydrofluoric acid may be used other than sulfuric acid.
  • [0060]
    In the cleaning process of the present embodiment, only the precipitated compounds are dissolved. However, the BPSG film 4 is not dissolved in the same cleaning process. Thus, even if the surface of the BPSG film 4 is repeatedly cleaned, it is possible to eliminate only the compounds (that is, impurities) without reducing the thickness of the BPSG film 4. As a result, even if the compounds are precipitated again on the once-cleaned surface of the BPSG film 4 due to long hours elapsed before the non-doped oxide film 5 is deposited in the next process, it is possible to clean the surface of the BPSG film 4 again without regard to reduction of the thickness of the BPSG film 4, thereby improving yield of a semiconductor substrate.
  • [0061]
    After completion of cleaning of the surface of the BPSG film 4, the non-doped oxide film 5 is deposited on the surface of the BPSG film 4 as shown in FIG. 1C. Specifically, the TEOS film, whose film thickness is approximately 50 nm, is deposited by means of CVD. Here, when the surface of the BPSG film 4 is exposed to the air, boron or phosphorus contained in the BPSG film 4 reacts with water in the air. As a result, the compounds such as BPO4, B2O3, and PO4, for example, are formed and precipitated on the surface of the BPSG film 4. The above-described compounds are foreign substances on the surface of the BPSG film 4, and substantially reduce yield in the subsequent semiconductor device manufacturing process. Thus, the non-doped oxide film 5, which functions as a protective coat, is deposited on the BPSG film 4. Note that the above-described process is also identical to that of the first embodiment.
  • [0062]
    After deposition of the non-doped oxide film 5, the photoresist 6 having an opening 7 in a predetermined area as shown in FIG. 1D is formed on the non-doped oxide film 5 by photolithography. Note that the above-described process is also identical to that of the first embodiment.
  • [0063]
    Next, as shown in FIG. 1E, dry etching is performed using the photoresist 6 as a protective mask for opening a contact hole 8 penetrating through the BPSG film 4 and the non-doped oxide film 5 and reaching the silicon substrate 1. For the above-described dry etching, CxFy gas (for example, C4F8, C5F8, C4F6) is used. Note that the above-described process is also identical to that of the first embodiment.
  • [0064]
    Then, ashing, etc., is performed for removing the photoresist 6, and the contact hole 8 is filled with metal (for example, tungsten). Specifically, the contact hole 8 is filled with metal by means of CVD or plating, etc., and the excess metal is removed by means of CMP, thereby completing formation of a contact electrically connecting an interconnection (not shown) formed in an upper layer and the transistor, etc., on the silicon substrate 1.
  • [0065]
    As described above, according to the contact hole formation method of the present embodiment, even if compounds are precipitated on the surface of the BPSG film 4 after a predetermined time period (for example, 24 hours or more) has elapsed after planarization of the BPSG film 4, it is possible to eliminate the compounds precipitated on the surface of the BPSG film 4. As a result, the non-doped oxide film 5 can be uniformly deposited. That is, it is not necessary to control the time elapsed after planarization of the BPSG film 4 because foreign substances on the surface of the BPSG film 4 are reliably eliminated. Thus, even if the wafer is left untouched after deposition of the BPSG film 4 for a predetermined time period, and compounds are precipitated on the surface of the BPSG film 4 during the predetermined time period before deposition of the non-doped oxide film 5, it is possible to form contact holes of uniform depth, thereby preventing yield from being reduced in the subsequent semiconductor device manufacturing process.
  • [0066]
    Note that the non-doped oxide film 5 in the first and second embodiments may be a film other than the TEOS film as long as the film is a dielectric film containing no impurities such as boron (B) and phosphorus (P), or a dielectric film whose impurity concentration is extremely low. For example, a silicon nitride film may be used as the above-described dielectric film.
  • [0067]
    Also, the interlayer dielectric deposited on the silicon substrate 1 in the first and second embodiments is not limited to the BPSG film 4, and a film whose surface shows pits and projections of the transistor, etc., formed on the silicon substrate 1 may be used as the interlayer dielectric. For example, an oxide film formed by coating, a low dielectric constant film, a PSG film which is a film made out of a silicon oxide film doped with phosphorus, or a BSG film which is a film made out of a silicon oxide film doped with boron may be used as the above-described interlayer dielectric. Note that the above-described low dielectric constant film may be a SiOC film, an organic film, or a porous film, for example.
  • [0068]
    Also, in the first and second embodiments, the BPSG film 4 is planarized by means of CMP, but the BPSG film 4 may be planarized by an etch back process in place of CMP. Specifically, the surface of the BPSG film 4 to be planarized is evenly coated with a resist having the same etching rate as the BPSG film 4. Then, dry etching is performed for the resist and the surface of the BPSG film 4 using the above-described resist as a sacrificial film. Thus, the resist is completely removed, and a portion of the BPSG film 4 is removed. Due to the same etching rate of the above-described resist and the BPSG film 4, the BPSG film 4 having an even surface can be obtained by the above-described etch back process. Note that the non-doped oxide film 5 can also be planarized by the above-described etch back process, as in the case of the BPSG film 4.
  • [0069]
    Note that, in the first and second embodiments, the contact holes are opened between the gate electrodes of the transistor. However, the contact holes maybe opened in other places. For example, the contact holes may be opened on the respective gate electrodes, or may be opened on respective gate electrode interconnections 12 as shown in FIG. 4. Here, the gate electrode interconnection 12 is an interconnection formed on an STI (Shallow Trench Isolation) dielectric film 11 on the silicon substrate 1, and the gate electrode interconnection 12 is connected to a gate electrode of the transistor. Also in this case, the gate electrode interconnections 12 are densely formed in some areas and sparsely formed in other areas, whereby there arises the same problem as the one which arises in the case of the gate electrode 2. However, the contact hole formation method according to the present invention allows the contact holes of uniform depth to be opened on the respective gate electrode interconnections 12, as is the case with the gate electrode 2.
  • [0070]
    While the invention has been described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is understood that numerous other modifications and variations can be devised without departing from the scope of the invention.

Claims (21)

  1. 1-14. (canceled)
  2. 15. A semiconductor device, comprising:
    a substrate having an area in which gate electrodes are densely arranged and an area in which gate electrodes are sparsely arranged;
    a first dielectric film on said substrate and provided with a planarized surface; and
    a second dielectric film on said planarized surface of said first dielectric film and having an etching rate different from an etching rate of said first dielectric film,
    wherein contact holes are formed through said first and second dielectric films.
  3. 16. The semiconductor device according to claim 15, wherein said second dielectric film is planarized.
  4. 17. The semiconductor device according to claim 15, wherein each of said contact holes extends to a surface or a corresponding one of said gate electrodes.
  5. 18. The semiconductor device according to claim 15, wherein a distance between at least two adjacent ones of said gate electrodes in the area in which gate electrodes are densely arranged is at most 0.3 μm.
  6. 19. The semiconductor device according to claim 15, wherein an entire surface of said first dielectric film is continuously higher than a top surface of said gate electrodes.
  7. 20. The semiconductor device according to claim 15, wherein said first dielectric film is one selected from the group consisting of: a BPSG film, a PSG film, a BSG film, an oxide film which is formed by coating, a low dielectric constant film, an organic film, and a porous film.
  8. 21. The semiconductor device according to claim 15, wherein said second dielectric film is a TEOS film or a silicon nitride film.
  9. 22. A semiconductor device, comprising:
    a substrate having an area in which interconnections are densely arranged and an area in which interconnections are sparsely arranged;
    a first dielectric film on said substrate and provided with a planarized surface; and
    a second dielectric film on said planarized surface of said first dielectric film and having an etching rate different from an etching rate of said first dielectric film,
    wherein contact holes are formed through said first and second dielectric films.
  10. 23. The semiconductor device according to claim 22, wherein said second dielectric film is planarized.
  11. 24. The semiconductor device according to claim 22, wherein each of said contact holes extends to a surface or a corresponding one of said interconnections.
  12. 25. The semiconductor device according to claim 22, wherein a distance between at least two adjacent ones of said interconnections in the area in which interconnections are densely arranged is at most 0.3 μm.
  13. 26. The semiconductor device according to claim 22, wherein an entire surface of said first dielectric film is continuously higher than a top surface of said interconnections.
  14. 27. The semiconductor device according to claim 22, wherein said first dielectric film is one selected from the group consisting of: a BPSG film, a PSG film, a BSG film, an oxide film which is formed by coating, a low dielectric constant film, an organic film, and a porous film.
  15. 28. The semiconductor device according to claim 22, wherein said second dielectric film is a TEOS film or a silicon nitride film.
  16. 29. A semiconductor device, comprising:
    a substrate having thereon interconnections spaced at different intervals;
    a first dielectric film on said substrate and provided with a planarized surface; and
    a second dielectric film on said planarized surface of said first dielectric film and having an etching rate different from an etching rate of said first dielectric film,
    wherein contact holes are formed through said first and second dielectric films.
  17. 30. The semiconductor device according to claim 29, wherein said second dielectric film is planarized.
  18. 31. The semiconductor device according to claim 29, wherein each of said contact holes extends to a surface or a corresponding one of said interconnections.
  19. 32. The semiconductor device according to claim 29, wherein an entire surface of said first dielectric film is continuously higher than a top surface of said interconnections.
  20. 33. The semiconductor device according to claim 29, wherein said first dielectric film is one selected from the group consisting of: a BPSG film, a PSG film, a BSG film, an oxide film which is formed by coating, a low dielectric constant film, an organic film, and a porous film.
  21. 34. The semiconductor device according to claim 29, wherein said second dielectric film is a TEOS film or a silicon nitride film.
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Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184121B2 (en) *
US5441915A (en) * 1992-09-01 1995-08-15 Taiwan Semiconductor Manufacturing Company Ltd. Process of fabrication planarized metallurgy structure for a semiconductor device
US5549786A (en) * 1995-08-29 1996-08-27 Advanced Micro Devices, Inc. Highly selective, highly uniform plasma etch process for spin-on glass
US5656556A (en) * 1996-07-22 1997-08-12 Vanguard International Semiconductor Method for fabricating planarized borophosphosilicate glass films having low anneal temperatures
US5893750A (en) * 1995-11-13 1999-04-13 Advanced Micro Devices, Inc. Method for forming a highly planarized interlevel dielectric structure
US6110775A (en) * 1997-02-04 2000-08-29 Matsushita Electronics Corporation Process for fabrication of a dram cell having a stacked capacitor
US6184121B1 (en) * 1997-07-10 2001-02-06 International Business Machines Corporation Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
US6271117B1 (en) * 1997-06-23 2001-08-07 Vanguard International Semiconductor Corporation Process for a nail shaped landing pad plug
US6277720B1 (en) * 1997-06-30 2001-08-21 Texas Instruments Incorporated Silicon nitride dopant diffusion barrier in integrated circuits
US6329251B1 (en) * 2000-08-10 2001-12-11 Taiwan Semiconductor Manufacturing Company, Ltd Microelectronic fabrication method employing self-aligned selectively deposited silicon layer
US6350665B1 (en) * 2000-04-28 2002-02-26 Cypress Semiconductor Corporation Semiconductor structure and method of making contacts and source and/or drain junctions in a semiconductor device
US20020055250A1 (en) * 1999-10-12 2002-05-09 Manoj K Jain Dielectric structure and method for minimizing erosion during chemical mechanical polishing of metals
US6518130B1 (en) * 1999-10-01 2003-02-11 Sony Corporation Method for forming a semiconductor device having a DRAM region and a logic region on the substrate

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11512877A (en) 1995-09-29 1999-11-02 インテル・コーポレーション Capped interlayer dielectric for chemical mechanical polishing
JPH09266252A (en) 1996-03-28 1997-10-07 Nec Corp Semiconductor device manufacturing method
JPH09289247A (en) 1996-04-19 1997-11-04 Sony Corp Formation method of contact
JPH10163205A (en) 1996-11-27 1998-06-19 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor device
JP3676034B2 (en) 1997-05-23 2005-07-27 富士通株式会社 Semiconductor device and manufacturing method thereof
JP3349937B2 (en) 1997-12-22 2002-11-25 沖電気工業株式会社 A method of manufacturing a semiconductor device
JPH11204520A (en) 1998-01-08 1999-07-30 Hitachi Ltd Semiconductor integrated circuit device and its manufacture
EP0967640A3 (en) 1998-06-25 2000-01-05 International Business Machines Corporation Method of making a self-aligned contact
JP2000058531A (en) 1998-08-17 2000-02-25 Seiko Epson Corp Manufacture of semiconductor device
JP3666560B2 (en) 1999-06-30 2005-06-29 松下電器産業株式会社 A method of manufacturing a semiconductor device
JP2001189306A (en) 1999-12-28 2001-07-10 Sony Corp Belt-driven atmospheric pressure cvd system

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6184121B2 (en) *
US5789313A (en) * 1992-09-01 1998-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Process for producing a semiconductor device with a planar top surface
US5441915A (en) * 1992-09-01 1995-08-15 Taiwan Semiconductor Manufacturing Company Ltd. Process of fabrication planarized metallurgy structure for a semiconductor device
US5549786A (en) * 1995-08-29 1996-08-27 Advanced Micro Devices, Inc. Highly selective, highly uniform plasma etch process for spin-on glass
US5893750A (en) * 1995-11-13 1999-04-13 Advanced Micro Devices, Inc. Method for forming a highly planarized interlevel dielectric structure
US5656556A (en) * 1996-07-22 1997-08-12 Vanguard International Semiconductor Method for fabricating planarized borophosphosilicate glass films having low anneal temperatures
US6110775A (en) * 1997-02-04 2000-08-29 Matsushita Electronics Corporation Process for fabrication of a dram cell having a stacked capacitor
US6271117B1 (en) * 1997-06-23 2001-08-07 Vanguard International Semiconductor Corporation Process for a nail shaped landing pad plug
US6277720B1 (en) * 1997-06-30 2001-08-21 Texas Instruments Incorporated Silicon nitride dopant diffusion barrier in integrated circuits
US6184121B1 (en) * 1997-07-10 2001-02-06 International Business Machines Corporation Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same
US6518130B1 (en) * 1999-10-01 2003-02-11 Sony Corporation Method for forming a semiconductor device having a DRAM region and a logic region on the substrate
US20020055250A1 (en) * 1999-10-12 2002-05-09 Manoj K Jain Dielectric structure and method for minimizing erosion during chemical mechanical polishing of metals
US6350665B1 (en) * 2000-04-28 2002-02-26 Cypress Semiconductor Corporation Semiconductor structure and method of making contacts and source and/or drain junctions in a semiconductor device
US6329251B1 (en) * 2000-08-10 2001-12-11 Taiwan Semiconductor Manufacturing Company, Ltd Microelectronic fabrication method employing self-aligned selectively deposited silicon layer

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US7316972B2 (en) 2008-01-08 grant
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US20040067630A1 (en) 2004-04-08 application

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