US20070151860A1 - Method for forming a copper metal interconnection of a semiconductor device - Google Patents

Method for forming a copper metal interconnection of a semiconductor device Download PDF

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Publication number
US20070151860A1
US20070151860A1 US11/617,153 US61715306A US2007151860A1 US 20070151860 A1 US20070151860 A1 US 20070151860A1 US 61715306 A US61715306 A US 61715306A US 2007151860 A1 US2007151860 A1 US 2007151860A1
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United States
Prior art keywords
plating
copper
distance
layer
plating layer
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Abandoned
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US11/617,153
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English (en)
Inventor
Ji Ho Hong
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DB HiTek Co Ltd
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Dongbu Electronics Co Ltd
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Publication date
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Assigned to DONGBU ELECTRONICS CO., LTD. reassignment DONGBU ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HONG, JI HO
Publication of US20070151860A1 publication Critical patent/US20070151860A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method

Definitions

  • FEOL front end of the line
  • BEOL back end of the line
  • the BEOL process may refer to a process of forming power supply and signal transfer paths on a silicon substrate to connect transistors to each other to constitute an integrated circuit.
  • Copper which is a material that may have high EM (Electro-migration) tolerance, may be used for such a BEOL process.
  • EM Electro-migration
  • copper may not be easily etched, and may be oxidized during an interconnection process, it may be difficult to pattern copper using a typical photo process technology.
  • a dual damascene process technology may be used as an alternative to photo technology.
  • the dual damascene process may form a via and a trench in an interlayer dielectric layer formed on a semiconductor substrate.
  • the via and trench may be filled with copper through an electro-chemical plating (ECP) scheme
  • ECP electro-chemical plating
  • the upper surface of the semiconductor substrate may be planarized through a CMP (Chemical Mechanical Polishing) process.
  • defects may occur due to copper residue after the CMP process.
  • FIG. 1 shows an image of copper residue observed through a scan electro microscope, which may remain after the CMP process.
  • FIG. 1 shows that lattice pattern 40 may be formed on a wafer, and copper residue 42 may be formed on lattice pattern 40 .
  • a stripe pattern 41 may be formed The stripe pattern may be irregular due to copper residue 42 formed on the stripe pattern. Since such copper residue 42 may disconnect the patterns from each other, the copper residue may be a factor that reduce a performance and yield rate of a semiconductor device.
  • Copper residue may be generated by various factors.
  • copper residue may be generated due to non-uniformity of a copper plating layer formed through a copper ECP process.
  • bubbles may accumulate in a plating solution, an unexpected current may be induced into the wafer.
  • the uniformity of the copper plating layer may be degraded.
  • the bubbles of the plating solution may be centralized at a center part of the wafer. Accordingly, the center part of the wafer may be plated more thinly than an edge part of the wafer.
  • barrier metal layer 12 may be formed on first interlayer dielectric layer 10 to prevent diffusion of copper atoms, and a prescribed damascene pattern (e.g., a via hole or a trench) may be formed on the resultant structure. Thereafter, a copper seed layer (not shown) may be formed on barrier metal layer 12 . An ECP process may then be performed such that copper plating layer 14 may be formed on interlayer dielectric layer 10 .
  • FIG. 2A shows a state in which bulk plating may be performed up to a prescribed height from interlayer dielectric layer 10 after sufficiently filling the damascene pattern with copper during the ECP process. Since a plating rate may vary depending on the size of a damascene pattern, the bulk plating may be performed to form a copper layer such that the entire damascene pattern may be sufficiently gap filled.
  • a thickness of a plating layer formed at center part 30 of the wafer may be thinner than the thickness of the plating layer formed at edge part 31 of the wafer.
  • the following copper CMP process may be divided into a main CMP process for removing the bulk plating layer and a final CMP process for removing barrier metal layer 12 formed on first interlayer dielectric layer 10 .
  • FIG. 2B is a schematic view showing the surface of the wafer after performing the main CMP process, in which concave part 14 a may be formed at center part 30 of the wafer. Since a similar removal rate may be applied to center part 30 and edge part 31 of the wafer during the main CMP process, center part 30 , which may be formed with a relatively thin plating layer, may be excessively polished.
  • the profile of such concave part 14 a remains as the profile of a concave part on first interlayer dielectric layer 10 , which may be a lower layer, even in the final CMP process as shown in FIG. 2C .
  • a damascene process may be performed again. Accordingly, second interlayer dielectric layer 20 may be formed on first interlayer dielectric layer 10 . At this time, barrier insulating layer 18 , which may be used as an etch stop layer when the damascene pattern is formed, may be interposed between first interlayer dielectric layer 10 and second interlayer dielectric layer 20 .
  • first interlayer dielectric layer 10 may have a profile of a concave part formed at the center part thereof, the same profile may be shown in the surface of second interlayer dielectric layer 20 formed on first interlayer dielectric layer 10 . Accordingly, barrier metal layer 22 may be formed.
  • Upper copper plating layer 24 may be formed through the copper ECP process as shown in FIG. 2E . If upper copper plating layer 24 is subject to the main CMP process, copper residue 42 may remain as shown in FIG. 2F . However, even after the final CMP process has been performed to remove barrier metal layer 22 , copper residue 42 are not removed, but remain on second interlayer dielectric layer 20 as shown in FIG. 2G .
  • Embodiments relate to a method for forming a copper metal interconnection of a semiconductor device.
  • Embodiments relate to a method for forming a copper metal interconnection through a damascene process that may be capable of minimizing the creation of copper residue.
  • a method for forming a copper metal interconnection of a semiconductor device through a damascene process may include forming a first copper plating layer on an interlayer dielectric layer of a semiconductor substrate in a plating tank through an electrical-chemical plating scheme for copper while maintaining a first plating distance, determining existence of a concave part by measuring surface uniformity of the first copper plating layer, and forming a second copper plating layer on the first copper plating layer by adjusting a plating distance in the plating tank if the concave part exists in the first copper plating layer.
  • a method for forming a copper metal interconnection of a semiconductor device through a damascene process may include forming a first copper plating layer on an interlayer dielectric layer of the semiconductor substrate by performing an electrical-chemical plating scheme with a first plating distance, measuring surface uniformity of the first copper plating layer, and forming a second copper plating layer on the first copper plating layer by adjusting a plating distance according to the surface uniformity of the first copper plating layer.
  • FIG. is an example illustration of state in which copper residue is generated in a copper metal interconnection created through a dual damascene process according to a related art
  • FIGS. 2A to 2 G are example sectional diagrams illustrating a generation of copper residue illustrated in FIG. 1 ;
  • FIGS. 3A and 3B are example sectional diagrams illustrating a method for forming a copper metal interconnection according to embodiments.
  • FIGS. 4A and 4B are example diagram illustrating a profile variation of a copper plating layer according to a plating distance in the method for forming the copper metal interconnection according to embodiments.
  • a copper seed layer (not shown) may be formed on barrier metal layer 12 .
  • Copper plating layer 14 may be formed on interlayer dielectric layer 10 , for example by performing an ECP process. If bubbles are centralized at center part 30 of a wafer in a plating tank, a thickness of the plating layer at center part 30 of the wafer may be thinner than a thickness of the plating layer at an edge part of the wafer. Accordingly, concave part 14 a may be formed in copper plating layer 14 .
  • the copper ECP process may be performed in the plating tank in which a plating solution is contained.
  • FIGS. 4A and 4B show states in which the wafer is arranged in plating tank 100 in which plating solution 110 is contained.
  • a distance that is, a plating distance
  • an electric field may be formed between anode electrode 120 and the wafer as indicated by arrow 130 a.
  • the plating distance is short as described above, since a stronger electric field may be formed at the center part of the wafer, copper atoms may be mainly plated at the center part of the wafer.
  • copper plating layer 140 a formed on the wafer may have a greater thickness in a center part of the wafer than at an edge part of the wafer.
  • copper atoms may be mainly plated at the edge part of the wafer. Accordingly, copper plating layer 140 b formed on the wafer may have a greater thickness in the edge part of the wafer than in the center part of the wafer.
  • the ECP process may be performed by measuring the optimized plating distance.
  • plating solution 110 may be circulated in plating tank 100 , and an electric field may be abnormally formed due to bubbles created during the ECP process. Accordingly, the copper plating layer may not always be uniformly formed on the wafer even if a specific plating distance is maintained.
  • second copper plating layer 15 may be formed on first copper plating layer 14 by performing the ECP process while adjusting the plating distance as shown in FIG. 3B .
  • a surface uniformity of the first copper plating layer may be measured so as to determine whether concave part 14 a exists.
  • the existence of concave part 14 a may be predicted by measuring the flow rate of the plating solution in the plating tank or measuring an electric field formed between the copper anode and the wafer. If the initially formed first copper plating layer is formed while maintaining a first plating distance, second plating may be performed by adjusting the plating distance to a distance shorter than the first plating distance. In embodiments, as shown in FIG. 4A , since many more copper atoms may be plated at the center part of the wafer, the concave part exiting in the first copper plating layer may be compensated.
  • a copper plating layer may be formed with improved uniformity, copper residue described with reference to FIGS. 2A to 2 G may not remain.
  • first plating distance is relatively long, a concave part may be created at an edge part of the wafer.
  • second plating may be performed by adjusting a plating distance to a plating distance longer than the first plating distance.
  • the method for forming a copper metal interconnection may be adaptable for a single damascene process as well as a dual damascene process.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
US11/617,153 2005-12-29 2006-12-28 Method for forming a copper metal interconnection of a semiconductor device Abandoned US20070151860A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020050134077A KR100731107B1 (ko) 2005-12-29 2005-12-29 다마신 공정을 이용한 반도체 소자의 구리 금속 배선의형성 방법
KR10-2005-0134077 2005-12-29

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080014746A1 (en) * 2006-07-14 2008-01-17 Chikarmane Vinay B Reducing corrosion in copper damascene processes

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030230491A1 (en) * 2001-01-17 2003-12-18 Basol Bulent M. Method and system monitoring and controlling film thickness profile during plating and electroetching
US20040195106A1 (en) * 2000-09-20 2004-10-07 Koji Mishima Plating method and plating apparatus

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5567300A (en) 1994-09-02 1996-10-22 Ibm Corporation Electrochemical metal removal technique for planarization of surfaces
JP2002093761A (ja) * 2000-09-19 2002-03-29 Sony Corp 研磨方法、研磨装置、メッキ方法およびメッキ装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040195106A1 (en) * 2000-09-20 2004-10-07 Koji Mishima Plating method and plating apparatus
US20030230491A1 (en) * 2001-01-17 2003-12-18 Basol Bulent M. Method and system monitoring and controlling film thickness profile during plating and electroetching

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080014746A1 (en) * 2006-07-14 2008-01-17 Chikarmane Vinay B Reducing corrosion in copper damascene processes
US7582558B2 (en) * 2006-07-14 2009-09-01 Intel Corporation Reducing corrosion in copper damascene processes

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Owner name: DONGBU ELECTRONICS CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HONG, JI HO;REEL/FRAME:018692/0764

Effective date: 20061226

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION