US20070069799A1

US20070069799A1 - Internal voltage generator for preventing voltage drop of internal voltage

Info

Publication number: US20070069799A1
Application number: US11/528,643
Authority: US
Inventors: Kang-Seol Lee; Seok-Cheol Yoon
Original assignee: Hynix Semiconductor Inc
Current assignee: SK Hynix Inc
Priority date: 2005-09-29
Filing date: 2006-09-28
Publication date: 2007-03-29
Also published as: US20110234288A1; US7977966B2; US8970236B2

Abstract

An internal voltage generating circuit is utilized to perform a TDBI (Test During Burn-in) operation for a semiconductor device. The internal voltage generator produces an internal voltage at a high voltage level, as an internal voltage, in not only a standby section but also in an active section in response to a test operation signal activated in a test operation. Accordingly, dropping of the internal voltage in the standby section of the test operation and failure due to open or short circuiting are prevented. As a result, reliability of the semiconductor chip, by preventing the generation of latch-up caused by breakdown of internal circuits, is assured.

Description

FIELD OF INVENTION

The present invention relates to a semiconductor device; and, more particularly, to an internal voltage generating circuit capable of making it possible to perform a TDBI (Test During Burn-in) operation.

BACKGROUND

Generally, semiconductor manufacturing processes are classified into a pre-process which is called a batch fabrication process (FAB) and a post-process which is called a packaging/test process. The pre-process is to set up circuit devices in a silicon substrate through a plurality of processes, such as diffusion, photo, etching, ion-implantation and thin film processes. After testing the characteristics of each device which is formed in a wafer by the pre-processes, the post-process individually performs a burn-in test, as a final test, on the unit device with the processes of sawing, bonding and molding the wafer by unit devices and a trim/form process. The burn-in test is performed in order to increase the productivity of the final test. The burn-in test is carried out at a temperature of approximately 125° C. and a pattern test is thereafter carried out in a range of approximately 60° C. to 75° C. after the burn-in test. The result of the test is sorted at a room temperature. The time required in the burn-in test may vary, depending on the use of the device. The equipment for semiconductor fabrication for the burn-in test is classified into first to third generation MBTs (Memory Burn-in Tester). The first generation MBT is a monitoring burn-in test capable of monitoring the burn-in results, the second generation MBT has a fast operation with a data management capability, and the third generation MBT is TDBI (Test During Burn-in) which includes the features of the first and second generation MBTs and further measures the characteristics of devices themselves.
As semiconductor chips become more and more integrated, the cell size is more and more miniaturized. Due to the integration in small cell size, the operating voltage is also reduced. In case of the DRAM (Dynamic random access memory), an internal power supply is generated by an external power supply provided from an external circuit; however, the external power supply can undergo a variation in voltage level because of noise and other environmental effects. Therefore, an internal voltage generating circuit should be designed in order to generate a stable voltage regardless of the deterioration of the exterior voltage.
FIG. 1 is a block diagram of a conventional internal voltage generating circuit. Referring to FIG. 1, a band gap reference circuit 10 produces a power supply voltage Vbg which is insensitive to a PVT (Process, Voltage, and Temperature) fluctuation. This power supply voltage Vbg is applied to a reference voltage generating circuit 20 to generate a reference voltage Vref and an internal voltage generating circuit 60 generates an internal voltage based on the reference voltage Vref.
The internal voltage generating circuit 60 includes a standby internal voltage generating circuit 30, an active internal voltage generating circuit 40, and an internal voltage control circuit 50. The standby internal voltage generating circuit 30, which is always active during the standby and active operations, is employed to stabilize an early voltage level with a low drivability. The active internal voltage generating circuit 40 is designed to supply the large driving force needed in the active mode by a plurality of active internal voltage generating circuits that are formed to provide sufficient driving force. When the semiconductor device operates, the internal voltage control circuit 50 outputs an active signal Act to activate the active internal voltage generating circuit 40.
A plurality of the active internal voltage generating circuits 40 are employed in the semiconductor device and are respectively activated depending on the corresponding active signals Act.
FIG. 2 is a block diagram of the internal voltage generating circuit in FIG. 1. For the sake of convenience, a high voltage power supply VPP, which is used for activating a word line, is illustrated as one of the internal voltage sources in the semiconductor device.
As described above, when the semiconductor device operates, that is, when the semiconductor device is in an active mode, the active internal voltage generating circuit 40 operates in order to obtain a large amount of the driving force. A high voltage generating unit 40a in FIG. 2 corresponds to the active internal voltage generating circuit 40. However, the standby internal voltage generating circuit 30 illustrated in FIG. 1, which functions in the standby or active mode, is omitted in FIG. 2.
Referring to FIG. 2, a high voltage generating circuit 60 a includes an internal voltage controller 50 a and a high voltage generator 40 a. Different internal control signals pwrup, ratv, rpcg and cke are activated in the active mode and input to the internal voltage controller 50 a. To produce an active signal Act, the internal voltage controller 50 a receives the power-up signal pwrup which is activated in the active mode, a RAS (Row Address Strobe) active signal ratv which is activated in a row active mode, a precharge signal rpcg which is activated in a precharge mode and a clock active signal cke for a low power operation.
The high voltage generating unit 40 a includes a high voltage detecting unit 42 a and a high voltage pumping unit 44 a. A reference voltage Vref is applied to the high voltage detecting unit 42 a and the high voltage detecting unit 42 a is activated in response to the active signal Act. The high voltage pumping unit 44 a, which receives an output signal PEE of the high voltage detecting unit 42 a, carries out a charge pumping operation.
FIG. 3 is a circuit diagram of the high voltage detecting unit 42 a of FIG. 2. Referring to FIG. 3, the high voltage detecting unit 42 a includes resistors R1 and R2 for dividing a high voltage VPP which is a feedback voltage from the high voltage pumping unit 44 a, a comparator 46 a having a current mirror amplifier structure operated in response to the active signal Act, and an inverter INV2 inverting an output signal of the comparator 46 a.
The high voltage detecting unit 42 a compares the divided voltage of the resistor R2 with the reference voltage Vref. When the divided voltage of the resistor R2 is higher than the reference voltage Vref, the high voltage detecting unit 42 a outputs the output signal PEE in a high level. To the contrary, when the divided voltage of the resistor R2 is lower than the reference voltage Vref, the high voltage detecting unit 42 a outputs the output signal PEE in a low level.
In other words, the active signal Act output from the internal voltage controller 50 a of FIG. 2 activates the high voltage detecting unit 42 a and the high voltage detecting unit 42 a outputs the output signal PEE. The high voltage pumping unit 44 a supplies the internal power, which is needed in the active mode, through the charge pumping operation in response to the output signal PEE.
FIG. 4 is a circuit diagram of the internal voltage controller of FIG. 2. Referring to FIG. 4, the internal voltage controller 50 a includes: a PMOS transistor P1 having a gate to receive the power-up signal pwrup during the power-up operation; a PMOS transistor P2 to receive the precharge signal rpcg activated in the precharge mode; an inverter INV4 for receiving and inverting the RAS active signal ratv in the row active mode; an NMOS transistor N1 having a gate to receive an output signal of the inverter INV4; a latch circuit having two inverters INV5 and INV6 for latching a logic level on node 1; an inverter INV8 for receiving and inverting an output signal of the latch circuit; an inverter INV7 for receiving and inverting the clock active signal cke for the low power operation; and a NOR gate NOR2 to receive output signals of the inverter INV8 and the inverter INV7.
FIGS. 5A and 5B are timing charts illustrating the operating characteristics of the internal voltage controller 50 a of FIG. 4. FIG. 5A is a timing chart illustrating the operating characteristics at the time of a normal operation. Referring to FIG. 5A, the active signal Act is kept in a high level in an active section in response to the internal control signals cke, ratv and rpcg. Thereafter, the activate signal Act is kept in a low level in a standby section in response to the transition of the precharge signal prcg which goes from a low level to a high level. Therefore, the high voltage generating unit 40 a of FIG. 2, which receives the active signal Act, is driven in the active section and does not function in the standby section.
FIG. 5B is a timing chart illustrating the operating characteristics at the time of a test operation. Referring to FIG. 5B, the active signal Act is kept in a high level just in the active section at the time of the test operation. That is, the high voltage generating unit 40 a does not operate in the standby section.
However, at the time of TDBI (Test During Burn-in) test operation, the repeated accesses at a high voltage and high temperature cause a large amount of leakage current to exponentially increase and then cause a fast voltage drop of the internal voltage in the standby section in which the internal voltage is kept in a relatively low level. The fast dropping of the internal voltage produces greater leakage paths, causing the semiconductor device to be burned by the highly increased temperature or a failure of O/Sl (Open/Short) In this case, the breakdown of the internal elements is caused so that a latch-up phenomenon is created. As a result, it is impossible to perform the stable test operation and the reliability of the semiconductor chips deteriorates.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide an internal voltage generating circuit which is driven in a standby section at the test operation time, by generating different active signals output from the internal voltage controller based on a normal operation or a test operation.
In accordance with an aspect of the present invention, there is provided an internal voltage generating circuit which produces a first voltage level in a standby section and a second voltage level in an active section, wherein the second voltage level is higher than the first voltage level. The internal voltage generating circuit comprises an internal voltage generator to produce an internal voltage in the second voltage level, as the internal voltage, in not only the standby section but also the active section in response to a test operation signal activated in a test operation.
In accordance with another aspect of the present invention, there is provided a semiconductor device, including a controller for generating an enable signal, regardless an operating section, in response to a test operation signal activated in a test operation and a voltage generator to produce an voltage having a second voltage level, as an internal voltage, in response to the enable signal.
In the present invention, an active internal voltage generator is driven not only in the active section but also in the standby section at the time of the test operation, by using a test operating signal output from a mode register set (MRS) at the time of the test operation, so that the internal voltage is prevented from being dropped in the standby section.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and features of the present invention will become better understood with respect to the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which:
FIG. 1 is a block diagram of a conventional internal voltage generating circuit;
FIG. 2 is a block diagram of an internal voltage generating circuit in FIG. 1;
FIG. 3 is a circuit diagram of the high voltage detector of FIG. 2;
FIG. 4 is a circuit diagram illustrating the internal voltage controller of FIG. 2;
FIGS. 5A and 5B are timing charts illustrating the operating characteristics of the internal voltage controller of FIG. 4;
FIG. 6 is a block diagram of an internal voltage generating circuit according to the present invention;
FIG. 7 is a circuit diagram of an internal voltage controller according to one embodiment of the present invention; and
FIGS. 8A and 8B are timing charts illustrating the operation characteristics of the internal voltage controller of FIG. 7.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, a semiconductor device for use in a semiconductor memory device in accordance with specific embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 6 is a block diagram of an internal voltage generating circuit according to the present invention. For the sake of convenience, a high voltage generating unit 400 a to produce a high voltage VPP will be illustrated as an element to receive an active signal Act. That is, the high voltage generating unit 400 a is shown as the active internal voltage generating circuit in FIG. 6 and the standby internal voltage generating unit which has been shown in FIG. 1 is omitted from FIG. 6.
Referring to FIG. 6, an internal voltage controlling unit 500 a receives a power-up signal pwrup which is activated at the time of a power-up operation, a RAS active signal ratv which is activated at the time of a low active operation, a precharge signal rpcg which is activated at the time of a precharge operation, a clock enable signal cke for a low power operation and a test operating signal Tm_bi which is output from a mode register set (MRS) at the time of a test operation. The internal voltage controlling unit 500 a outputs the active signal Act for activating the high voltage generating unit 400 a.
A high voltage detecting unit 420 a in the high voltage generating unit 400 a detects a potential level of the high voltage, as a feedback signal, which is activated by the active signal Act. A high voltage pumping unit 440 a, which receives an output signal PEE of the high voltage detecting unit 420 a, produces a high voltage VPP by carrying out a desired charge pumping operation.
FIG. 7 is a circuit diagram of the internal voltage controlling unit 500 a of FIG. 6 in accordance with one embodiment of the present invention and the same elements shown in FIGS. 4 and 7 are designated with the same reference numerals.
Referring FIG. 7, the internal voltage controlling unit 500 a includes a first internal voltage controlling unit 520 a, which receives internal control signals pwrup, ratv, rpcg and cke, and a second internal voltage controlling unit 540 a into which an output signal of the first internal voltage controlling unit 520 a and the test operation signal Tm_bi are input in order to output the active signal Act.
The first internal voltage controlling unit 520 a includes: a first PMOS transistor P1 having a gate to receive the power-up signal pwrup during the power-up operation, being electrically connected between a power supply voltage and node 1; a second PMOS transistor P2 having a gate to receive the precharge signal rpcg activated in the precharge mode, being electrically connected between a power supply voltage VDD and node 1; a first inverter INV4 for receiving and inverting the RAS active signal ratv in a row active mode; a fist NMOS transistor N1 having a gate to receive and invert an output signal of the inverter INV4, being electrically connected between node 1 and a ground voltage level VSS; a latch circuit having two inverters INV5 and INV6 for latching a logic level on node 1; a second inverter INV7 for receiving and inverting the clock active signal cke for the low power operation; a third inverter INV8 for receiving and inverting an output signal from the latch circuit; and a first NOR gate NOR2 to receive output signals from both the third inverter INV8 and the second inverter INV7.
The latch circuit of the first internal voltage controlling unit 520 a includes a fourth inverter INV5 having an input terminal which is connected to node 1 and a fifth inverter INV6 having an input terminal which is connected to an output terminal of the fourth inverter INV5 and an output terminal which is connected to node 1.
The second internal voltage controlling unit 540 a includes a second NOR gate NOR4, which receives an output signal of the first voltage controlling unit 520 a and the test operation signal Tm_bi, and a sixth inverter INV9 to invert an output signal of the second NOR gate NOR4.
FIGS. 8A and 8B are timing charts illustrating the operation characteristics of the internal voltage controlling unit 500 a of FIG. 7.
FIG. 8A is a timing chart illustrating the operation characteristics at the time of the normal operation. Referring to FIG. 8A, the test operation signal Tm_bi is kept in a low level at the time of the normal operation. The activate signal Act is kept in a high level in an active section in response to the internal control signal cke, ratv and rpcg and thereafter is kept in a low level in a standby section in response to a rising edge of the precharge signal prcg which goes from a low level to a high level. Therefore, the active internal voltage generating circuit (that is, the high voltage generating unit 400 a of FIG. 6) to receive the active signal Act operates in the active section and does not operate in the standby interval. That is, the operation characteristics at the time of the normal operation of the present invention are the same as those at the time of the conventional operation.
FIG. 8B is a timing chart illustrating the operation characteristics at the time of the test operation. Referring to FIG. 8B, the test operation signal Tm_bi is kept in a high level at the time of the test operation. Accordingly, the active signal Act is in a high level based on the test operation signal Tm_bi. That is, since the active signal Act is always kept in a high level in the active and standby sections, the active internal voltage generating circuit (that is, the high voltage generating unit 400 a of FIG. 6) is always driven in the active and standby sections at the time of the test operation.
In conclusion, even though the internal voltage of the internal voltage generating circuit suddenly drops in the standby section, the present invention prevents such a sudden drop of the internal voltage in the standby section by driving the active internal voltage generating circuit in not only the active sections but also the standby sections using the test operation signal Tm_bi.
As apparent from above, the present invention prevents the internal voltage from dropping in the standby section of the test operation and also prevents the semiconductor device from bunring and a failure of O/Sl (Open/Short). As a result, the present invention secures the reliability of the semiconductor chip by preventing the generation of latch-up which is caused by breakdown of the internal circuits unit.
The present application contains subject matter related to the Korean patent applications Nos. KR 10-2005-0091589 and KR 10-2006-0040696, filed in the Korean Patent Office on Sep. 29, 2005 and on May 4, 2006 respectively, the entire contents of which being incorporated herein by references.
While the present invention has been described with respect to certain specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

Claims

1. An internal voltage generating circuit which produces a first voltage level in a standby section and a second voltage level in an active section, wherein the second voltage level is higher than the first voltage level, the internal voltage generating circuit comprising:

an internal voltage generator to produce an internal voltage in the second voltage level, as an internal voltage, in not only the standby section but also the active section, in response to a test operation signal activated in a test operation.

2. The internal voltage generating circuit in accordance with claim 1, wherein the internal voltage generator includes:

a first internal voltage controlling means for outputting a first control signal to produce the internal voltage in the second voltage level in a normal operation;

a second internal voltage controlling means for outputting a second control signal to produce the internal voltage in the second voltage level in the test operation; and

an internal voltage generating means for producing the higher voltage in response to the first and second control signals.

3. The internal voltage generating circuit in accordance with claim 1, further comprising a means for producing the internal voltage in the first voltage level.

4. The internal voltage generating circuit in accordance with claim 2, wherein the second internal voltage controlling means activates the internal voltage generating means in the test operation in response to the test operation signal.

5. The internal voltage generating circuit in accordance with claim 4, wherein the test operation signal is maintained in a first logic level of the test operation and wherein the test operation signal is maintained in a second logic level in the normal operation.

6. The internal voltage generating circuit in accordance with claim 5, wherein the internal voltage generating means produces the internal voltage in the second voltage level in response to the test operation signal of the first logic level.

7. The internal voltage generating circuit in accordance with claim 2, wherein the internal voltage generator includes a plurality of internal voltage generating means and wherein at least one of the internal voltage generating means is driven in response to an output signal from the first and second internal voltage controlling means.

8. The internal voltage generating circuit in accordance with claim 1, wherein the test operation signal is output from a MRS (Mode Register set).

9. The internal voltage generating circuit in accordance with claim 2, wherein the first internal voltage controlling means outputs a signal to active the internal voltage generating means in the active section of the normal operation.

10. The internal voltage generating circuit in accordance with claim 2, wherein the second internal voltage controlling means includes:

a NOR gate to receive an output signal from the first internal voltage controlling means and the test operation signal; and

an inverter to invert an output signal from the NOR gate and to output a signal for activating the internal voltage generating means.

11. An internal voltage generating circuit which produces a standby internal voltage in a standby section and an active internal voltage in an active section, wherein the active internal voltage is higher than the standby internal voltage, the internal voltage generating circuit comprising:

a standby internal voltage generating means for producing the standby internal voltage;

an active internal voltage generating means for the active internal voltage; and

a means for increasing a voltage level of the standby internal voltage which is produced in the standby section up to the active internal voltage in response to a test operation signal activated in a test operation.

12. A semiconductor device, comprising:

a controller for generating an enable signal, regardless an operating section, in response to a test operation signal activated in a test operation; and

a voltage generator to produce an voltage having a second voltage level, as an internal voltage, in response to the enable signal.

13. The semiconductor device as recited in claim 12, wherein the controller decodes inputted signals to recognize an operating section and generating an enable signal in response to the operating section when the test operation signal is inactivated.

14. The semiconductor device as recited in claim 13, wherein the voltage generator produces a first voltage level in a standby section and a second voltage level in an active section when the test operation signal is inactivated, wherein the second voltage level is higher than the first voltage level.

15. The semiconductor device as recited in claim 14, wherein the voltage generator includes:

16. The semiconductor device as recited in claim 14, further comprising a means for producing the internal voltage in the first voltage level.

17. The semiconductor device as recited in claim 14, wherein the second internal voltage controlling means activates the internal voltage generating means in the test operation in response to the test operation signal.

18. The semiconductor device as recited in claim 14, wherein the test operation signal is maintained in a first logic level of the test operation and wherein the test operation signal is maintained in a second logic level in the normal operation.

19. The semiconductor device as recited in claim 18, wherein the internal voltage generating means produces the internal voltage in the second voltage level in response to the test operation signal of the first logic level.

20. The semiconductor device as recited in claim 18, wherein the first internal voltage controlling means outputs a signal to active the internal voltage generating means in the active section of the normal operation.