US20070059918A1 - Rigid-flexible printed circuit board for package on package and manufacturing method - Google Patents

Rigid-flexible printed circuit board for package on package and manufacturing method Download PDF

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Publication number
US20070059918A1
US20070059918A1 US11/520,730 US52073006A US2007059918A1 US 20070059918 A1 US20070059918 A1 US 20070059918A1 US 52073006 A US52073006 A US 52073006A US 2007059918 A1 US2007059918 A1 US 2007059918A1
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Prior art keywords
rigid
substrate
flexible
circuit board
printed circuit
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Abandoned
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US11/520,730
Inventor
Hoe-Ku Jung
Myung-Sam Kang
Jung-Hyun Park
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Samsung Electro Mechanics Co Ltd
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Samsung Electro Mechanics Co Ltd
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Assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD. reassignment SAMSUNG ELECTRO-MECHANICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JUNG, HOE-KU, KANG, MYUNG-SAM, PARK, JUNG-HYUN
Publication of US20070059918A1 publication Critical patent/US20070059918A1/en
Priority to US12/453,832 priority Critical patent/US7802358B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H05K3/4691—Rigid-flexible multilayer circuits comprising rigid and flexible layers, e.g. having in the bending regions only flexible layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/05—Flexible printed circuits [FPCs]
    • H05K2201/056—Folded around rigid support or component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.

Definitions

  • the present invention relates to a printed circuit board, in particular, to a printed circuit board for package on package and a manufacturing method thereof in which there is a level difference in the surface of the substrate for mounting 2 or more IC chips on the bottom substrate of the printed circuit board.
  • Semiconductor packaging provides electrical connection to semiconductor chips including circuits and is seal-packaged to protect from any external impact so that it allows effect on the physical function and appearance for useful in the real life.
  • the semiconductor package is an outcome of the semiconductor packaging process to manufacture semiconductor chips as a product.
  • the semiconductor chip can be damaged easily by an external impact because the semiconductor chip has fine circuits. That is, the semiconductor chip itself cannot be a perfect product, but it may play a role as a perfect product by mounting it on a printed circuit board.
  • a packaging technology affects reduction of the size of the semiconductor chip, improvement of ability to emit heat, electrical performance, reliability and depreciation. Therefore improvement of packaging technology is required to support high integration and high efficiency of semiconductor devices.
  • the semiconductor package not only satisfies requirements of the semiconductor devices but also has packaging performance suitable for the condition when the chips are mounted on a printed circuit board.
  • the semiconductor package must follow the trend of lightness, thinness and smallness in order to raise the efficiency of packaging per unit volume. According to the above trend, a chip size package (CSP), of which the size is almost same as the size of a chip, has introduced.
  • CSP chip size package
  • SCSP stacked CSP
  • MCM multi chip module
  • POP Package on package
  • a thickness of a whole package is the most restriction for the embodiment of POP.
  • FIGS. 1 a and 1 b show the figures of the structure of POP according to a conventional technology and a recent tendency.
  • a thickness of a whole package is H 2 .
  • H 2 is larger than H 1 shown in FIG. 1 a , which is against the tendency of lightness, thinness and smallness
  • the thickness problem has been tried to solve by using a die thinning technology in order to lower the thickness of a whole package according to the tendency of lightness, thinness and smallness. But there are problems of function errors caused by operating semiconductor chips for a long period of time when thin semiconductor chips are used.
  • the present invention aims to provide a rigid-flexible printed circuit board having a cavity of a level difference in the surface of the substrate, on which semiconductor chips are mounted.
  • the present invention aims to provide a rigid-flexible printed circuit board which can lower a thickness of whole packages when same numbers of the semiconductor chips are mounted.
  • the present invention aims to provide a rigid-flexible printed circuit board in which the packaging of 2 or more semiconductor chips is possible using a space the same as a thickness of a core layer.
  • the present invention aims to provide a rigid-flexible printed circuit board which can lower board warpage by using a thick core layer.
  • the present invention aims to provide a rigid-flexible printed circuit board which can form a fine pattern using a flexible copper clad laminate (FCCL).
  • FCCL flexible copper clad laminate
  • One aspect of the present invention provides a rigid-flexible multi-layer printed circuit board comprising: a flexible substrate of which circuits are formed on both sides and which is bendable; a rigid substrate having a cavity which is laminated on the flexible substrate and of which circuits are formed on both sides and semiconductor chips can be mounted in the cavity; and a bonding sheet adhering the flexible substrate and the rigid substrate and having a insulating property.
  • the rigid substrate is thicker than the flexible substrate.
  • wire bonding pads for electrical connection with the semiconductor chips are formed on the flexible substrate within the cavity and on the rigid substrate of the edge of opening part of the cavity.
  • the flexible substrate and the rigid substrate are connected electrically therebetween through inner via holes or blind via holes.
  • a plurality of the rigid substrates having the cavity are laminated with a predetermined gap on the flexible substrate and package on package (POP) is formed by folding the flexible substrate having the predetermined gap after semiconductor chips are mounted within the cavity.
  • POP package on package
  • Another aspect of the present invention provides a method for manufacturing a multi-layer rigid-flexible printed circuit board comprising: (a) forming a single circuit on a flexible substrate; (b) laminating a rigid substrate having a circuit and a cavity on the flexible substrate; (c) drilling via holes interconnecting the flexible substrate and the rigid substrate; (d) plating the via holes; (e) forming an outer circuit on a laminate of the flexible substrate and the rigid substrate; and (f) forming wire bonding pads for electrical connection with semiconductor chips on the flexible substrate within the cavity and on the rigid substrate of the edge of the opening part of the cavity.
  • the single circuit is formed through a roll to roll process on the flexible substrate.
  • the step (b) comprises: forming the cavity on the rigid substrate by using a punch or a router.
  • the step (b) further comprises (b- 1 ) laminating with pressure by using a bonding sheet between the flexible substrate and the rigid substrate.
  • the flexible substrate and the rigid substrate are laminated on a desired position using a rivet or a pin.
  • laminating a conformal film is further comprised so that the bonding sheet does not cover the wire bonding pads.
  • step (b) a plurality of the rigid substrates are laminated on the flexible substrate with a predetermined gap, and after the step (f), (g) mounting a plurality of semiconductor chips within the each cavity, and (h) folding and molding the flexible substrate laminated with the predetermined gap are further comprised.
  • FIGS. 1 a and 1 b show the figures of the structure of POP according to the conventional technology and recent tendency
  • FIG. 2 shows a thinner package according to an embodiment of the present invention in comparison with the conventional invention
  • FIGS. 3 a to 3 j illustrate a method for forming a cavity to mount semiconductor chips on a rigid-flexible printed circuit board according to an embodiment of the present invention
  • FIG. 4 a is a cross sectional view of the rigid-flexible printed circuit board manufactured by the processes shown in FIGS. 3 a to 3 j;
  • FIG. 4 b is a plan view of the rigid-flexible printed circuit board shown in FIG. 4 a;
  • FIG. 5 a shows the unfolded rigid-flexible printed circuit board for POP according to an embodiment of the present invention
  • FIG. 5 b is an exemplary view illustrating the smaller rigid-flexible printed circuit board for POP shown in FIG. 5 a by folding itself.
  • FIG. 2 shows a thinner package according to an embodiment of the present invention, in comparison with the conventional invention.
  • a bottom substrate of a POP package is shown in FIG. 2 .
  • a package on the left side is a stack package on which 2 or more semiconductor chips 100 and 110 are mounted according to a conventional technology.
  • a package on the right side has a cavity 200 according to an embodiment of the present invention and the semiconductor chips 100 and 110 are mounted therein so that a whole thickness of the POP package is reduced to H 3 . Therefore, the whole thickness of a POP package can be thinner by using a printed circuit board having a cavity formed to have a level difference in the surface of a substrate according to the present invention.
  • FIGS. 3 a to 3 j illustrate a method for forming a cavity to mount semiconductor chips on a rigid-flexible printed circuit board according to an embodiment of the present invention.
  • circuits and a cavity 310 are formed in a core layer 30 .
  • an inner layer circuit 305 is formed on single side surface or double side surfaces of a resin layer of a copper clad laminate (CCL) 300 forming the core layer 30 .
  • the copper clad laminate 300 forming the core layer 30 is preferably a rigid substrate.
  • the inner layer circuit 305 is formed on the copper clad laminate or the substrate which copper plating is completed with a desired shape.
  • the inner layer circuit 305 is formed by spreading a photosensitive photo resist on the substrate, adhering closely a photo mask on the substrate, forming a desired circuit on the photo resist using ultraviolet rays and etching unnecessary copper using a chemical reaction.
  • the inner layer circuit 305 can be formed by a subtractive process or additive process according to a manufacturing process.
  • the subtractive process is also termed as a ‘tent and etch process’ because etching is generally performed after tenting on parts where the circuit will be formed and the inner part of holes with the photo resist.
  • the process involves exposing copper parts where circuits will be formed, etching the rest copper parts, and forming a circuit. Therefore, it is the process of removing copper used as a chemical.
  • an additive process is a process forming a circuit by adding copper.
  • the inner layer circuit 305 be formed by the subtractive process and an outer layer circuit be formed by the additive process or a semi-additive process which is modification of the additive process.
  • the inner layer circuit 305 or the outer layer circuit may be formed by various other processes.
  • the copper clad laminate 300 forming the core layer is arranged.
  • And holes 350 are formed as follows: drilling process using a mechanical drill, a punch, a router or a laser drill (namely, CO2 laser drill or Nd-Yag laser drill) and copper plating process through a chemical copper plating and an electrical copper plating.
  • a mechanical drill namely, CO2 laser drill or Nd-Yag laser drill
  • copper plating process through a chemical copper plating and an electrical copper plating.
  • the inner layer circuit 305 is formed and an inspection of the inner layer circuit 305 is performed whether it is formed properly or not.
  • the holes 350 are preferably inner via holes (IVH).
  • the inner via holes are blind and buried via holes, which interconnect between 2 or more conductive layers of a multi-layer printed circuit board but does not penetrate the multi-layer printed circuit board.
  • the cavity 310 for mounting semiconductor chips may be formed when the drilling process for forming the hole 350 is performed or separately through punching or mechanical drilling using a router or laser drilling using a CO 2 laser drill or Nd-Yag laser drill after the inner layer circuit 305 is formed.
  • the core layer 30 is preferably thicker than a flexible substrate (FCCL) 330 , by which unwanted parts of the FCCL 330 are prevented from bending. Namely, the warpage can be prevented.
  • FCCL flexible substrate
  • a FCCL 330 is prepared. And a single side surface circuit 335 is formed by a roll-to-roll process. A via land where a via will be formed and a circuit pattern are formed.
  • the roll-to-roll process is a process using rolls in order to support the FCCL 330 flatly and form a single side surface circuit 335 because the FCCL 330 is thin and bendable.
  • a feeder part and a winder part have each roll.
  • the FCCL 330 is maintained the flat while it is rolled from the feeder part to the winder part. While the FCCL 330 is moving from the feeder part to the winder part, the single side surface circuit 335 is formed through a general process such as dry film lamination, exposure, developing, drilling, routing, and plating, etc.
  • the core layer 30 and the FCCL 330 are laminated using a bonding sheet 340 .
  • a laminating using rivet or pin is performed in order to provide accurate align of the core layer 30 and the FCCL 330 .
  • the bonding sheet 340 is a sheet made of an adhesive material in order to glue each layer, and it may be a prepreg or a bonding film.
  • a pad part (A in FIG. 3 e ) is not covered by the bonding sheet 340 when the core layer 30 and the FCCL 330 are laminated by using the bonding sheet 340 , as shown in FIGS. 3 d and 3 e.
  • a conformal film 342 is used so that the bonding sheet 340 does not cover the pad part (A in FIG. 3 e ) where the circuit formed in the inner layer is connected when semiconductor chips are mounted. Also, the conformal film 342 provides uniform pressure to the substrate by filling the cavity 310 with its melted one while the laminating process. The bonding sheet 340 thus allows that the core layer 30 adheres to the FCCL 330 with the even pressure. Polyethylene film or polyvinyl chloride film can be used as the conformal film 342 .
  • a dummy board 344 is used as buffer to protect not to concentrate the pressure to the edge of the opening part of the cavity 310 and prevents damage of the circuit.
  • a release film 346 is used in order to remove easily the dummy film 344 from the substrate later.
  • the conformal film 342 , the dummy film 344 and the release film 346 are removed, and a multi-layer printed circuit board, on which the FCCL 330 and the core layer 30 , in which the cavity 310 is formed, are laminated, is formed as shown in FIG. 3 f.
  • vias 360 are formed in the insulation parts of the FCCL 330 by using a laser drill (namely, a CO 2 laser drill or Nd-Yag laser drill) on the laminate shown in FIG. 3 f .
  • the vias 360 provide electrical connection between the circuits 335 formed on the surface of the FCCL 330 and interconnect between the FCCL 330 and the core layer 30 .
  • Size of the via and drilling condition may be determined according to a thickness of the FCCL 330 and a thickness of the bonding sheet 340 .
  • the via 360 is preferably blind via hole.
  • the core layer 30 and the FCCL 330 are connected by forming a seed layer after a surface treatment (IAR: ion assisted reaction) of the part where the via 360 is formed, and plating 362 .
  • the seed layer may be formed by chemical plating or sputtering, and after plating, the via part is plated through electrolytic plating.
  • the seed layer is copper-plating having a thickness of 0.3 to 1.5 ⁇ m, and the seed layer is further plated to provide a thickness of about 10 ⁇ m through the electrolytic plating.
  • the part except the via 360 is covered with a protection film in order to protect the pad part of the core layer 30 and the FCCL 330 (A in FIG. 3 e ).
  • an outer circuit 364 is formed on both sides of the laminate in which the via 360 is formed and which is plated.
  • the outer circuit 364 is formed by laminating a dry film, etching the copper of unnecessary parts, except the part being a via or a circuit through the tenting method and forming the circuit. This is possible by the above process described referring to FIG. 3 a.
  • PSR photo solder resist
  • the outer circuit is protected by coating with the solder resist 370 .
  • PSR ink as the solder resist 370 , is used in order that solder, which is used so as to mount components on the printed circuit board, is adhered on necessary parts and is thus prevented from being adhered on unnecessary parts. Because of properties of the PSR ink, the PSR ink helps the solder not to adhere on parts where the PSR ink is remained and to adhere on parts where the PSR ink is not remained so that electronic components can be mounted on the parts where the solder is adhered. Also, the PSR ink is coated in order to protect the surface circuit of the printed circuit board from an outer environment.
  • the solder mask printing process comprises forming roughness on the outer circuit 364 in order that the PSR ink can adhere well with the printed circuit board, removing pollutants, coating with the PSR ink by using a screen printing method or a spray coating method, exposing, developing and complete hardening.
  • a wire bonding pad 320 is formed through the electrolytic gold-plating or the electroless gold-plating in order to connect electrically between the core layer 30 and the FCCL 330 .
  • the gold-plating electrical connection and protection from the outer environment are possible.
  • the electrolytic gold-plating is a plating method by extracting gold electrically, and is divided to soft gold and hard gold according to the hardness of gold. Soft gold is applied to products which bonding properties are needed, such as ball grid array and the like, and hard gold is applied to products needing high abrasion resistance and electrical properties.
  • the electroless gold-plating is a plating method by using a chemical reaction not through electric, and is divided to flash plating and thickness plating according to a thickness of the gold-plating.
  • the wire bonding pad 320 has preferably two layers each formed on the core layer 30 and the FCCL 330 in order to mount two or more semiconductor chips.
  • a bump forming pad (not shown), on which the bump can be formed for connecting electrically with another printed circuit board package laminated on the printed circuit board package in FIG. 3 j and maintaining a lamination gap, is formed on the core layer 30 .
  • the bump forming pad may also be formed through the electrolytic or electroless gold-plating. Electrical connection and protection from the outer environment is possible by the gold-plating.
  • FIG. 4 a is a cross section of the rigid-flexible printed circuit board manufactured by the processes shown in FIGS. 3 a to 3 j
  • FIG. 4 b is a plan view of the rigid-flexible printed circuit board shown in FIG. 4 a.
  • the rigid-flexible printed circuit board comprises a core layer 30 , an FCCL 330 , a bonding sheet 340 , a cavity 310 within the core layer 30 , a wire bonding pad 320 and vias 350 .
  • the core layer 30 is laminated on the FCCL 330 , and the cavity 310 , within which a semiconductor chip can be mounted, is formed in the core layer 30 .
  • the wire bonding pad 320 for electrical connection with the semiconductor chip is formed on the A part of the FCCL 330 exposed through the cavity 310 .
  • another wire bonding pad 320 for electrical connection with the semiconductor chip is formed on the edge of the opening part of the cavity 310 of the core layer 30 .
  • a bump forming pad namely a ball pad 400 , on which the bump can be formed for connecting electrically with another printed circuit board package on the printed circuit board package in FIG. 3 j and maintaining the lamination gap, is formed on the core layer 30 .
  • FIG. 5 a shows the unfolded rigid-flexible printed circuit board for POP according to an embodiment of the present invention
  • FIG. 5 b is an exemplary view illustrating the smaller rigid-flexible printed circuit board for POP shown in FIG. 5 a by folding itself.
  • two core layers 30 having the cavity 310 shown in FIG. 4 b are laminated on the FCCL 330 with a predetermined gap.
  • each core layer 30 is laminated each other by folding the center part of the FCCL 330 where the core layer 30 is not laminated as shown in FIG. 5 b .
  • the electrical connection and the gap between the packages can be maintained by forming the bump 510 on the ball pad 400 .
  • the miniaturized rigid-flexible printed circuit board for POP may be stably mounted in products by maintaining the folded shape through molding.
  • the rigid-flexible printed circuit board of the present invention is manufactured to have a level difference in the surface of a substrate by forming a cavity in the part on which semiconductor chips are mounted.
  • a thickness of the whole package can be reduced or when POP is embodied, a whole thickness of the package can be lower.
  • two or more semiconductor chips can be mounted using the same space as a thickness of the core layer, and when the number of semiconductor chip to be mounted on the bottom of the substrate is increased from 1 to 2, it becomes possible which was impossible with the conventional flexible printed circuit.
  • board warpage may be reduced by using a thick core layer.
  • a fine pattern may be formed by using a flexible substrate.

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Abstract

The present invention relates to a rigid-flexible multi-layer printed circuit board comprising: a flexible substrate of which circuits are formed on both sides and which is bendable; a rigid substrate which is laminated on the flexible substrate and circuits are formed on both sides and a cavity within which a semiconductor chip is mounted is formed; and a bonding sheet adhering the flexible substrate and the rigid substrate and having a insulating property. According the present invention, when the same numbers of the semiconductor chips are mounted or the POP is embodied, the whole thickness of the package can be lower. Also, two more semiconductor chips can be mounted using the space as the thickness of the core layer, and the structure impossible when the number of semiconductor chip mounted on the bottom substrate becomes two from one in conventional technology can be embodied.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application claims the benefit of Korean Patent Application No. 2005-0085644 filed with the Korea Industrial Property Office on Sep. 14, 2005, the disclosure of which is incorporated herein by reference in its entirety.
    • BACKGROUND
  • 1. Technical Field
  • The present invention relates to a printed circuit board, in particular, to a printed circuit board for package on package and a manufacturing method thereof in which there is a level difference in the surface of the substrate for mounting 2 or more IC chips on the bottom substrate of the printed circuit board.
  • 2. Description of the Related Art
  • Semiconductor packaging provides electrical connection to semiconductor chips including circuits and is seal-packaged to protect from any external impact so that it allows effect on the physical function and appearance for useful in the real life.
  • The semiconductor package is an outcome of the semiconductor packaging process to manufacture semiconductor chips as a product.
  • Even though from several tens to several hundreds of chips printed with identical circuits can be placed on one wafer, semiconductor chip itself cannot transfer or receive an electrical signal with electricity supplied from outside.
  • Moreover, the semiconductor chip can be damaged easily by an external impact because the semiconductor chip has fine circuits. That is, the semiconductor chip itself cannot be a perfect product, but it may play a role as a perfect product by mounting it on a printed circuit board.
  • A packaging technology affects reduction of the size of the semiconductor chip, improvement of ability to emit heat, electrical performance, reliability and depreciation. Therefore improvement of packaging technology is required to support high integration and high efficiency of semiconductor devices. The semiconductor package not only satisfies requirements of the semiconductor devices but also has packaging performance suitable for the condition when the chips are mounted on a printed circuit board.
  • Space to mount semiconductor chips currently has become smaller with high demand of miniaturized portable electronic devices and the number of semiconductor chips has currently been increased with high demand of multi-functions and high performance of products.
  • Because of the miniaturization, more capacity, and high processing speed of semiconductor chips, with rapid development of multimedia and computer communication industries, researches to find thinner semiconductor packages and higher integration with more pins have been increased.
  • Therefore, the semiconductor package must follow the trend of lightness, thinness and smallness in order to raise the efficiency of packaging per unit volume. According to the above trend, a chip size package (CSP), of which the size is almost same as the size of a chip, has introduced.
  • Beyond the package, which is minimized to the size of a chip, a stacked CSP (SCSP), which stacks one chip on another chip, or a multi chip module (MCM) package, which arranges several semiconductor chips having different functions in one package, has been also developed.
  • Package on package (POP), which stacks one package on another package, becomes popular for high density package. A thickness of a whole package is the most restriction for the embodiment of POP. There is a demand for mounting 2 or more semiconductor chips, instead of one semiconductor chip, on the bottom substrate, so that the performance of POP becomes higher.
  • FIGS. 1 a and 1 b show the figures of the structure of POP according to a conventional technology and a recent tendency.
  • Referring to FIG. 1 a, conventionally one semiconductor chip 100 is stacked on a bottom substrate 10, and a thickness of a whole package is H1.
  • Referring to FIG. 1 b, according to a recent tendency, two semiconductor chips 100 and 110 are stacked on a bottom substrate 10. In this case, a thickness of a whole package is H2. H2 is larger than H1 shown in FIG. 1 a, which is against the tendency of lightness, thinness and smallness
  • The thickness problem has been tried to solve by using a die thinning technology in order to lower the thickness of a whole package according to the tendency of lightness, thinness and smallness. But there are problems of function errors caused by operating semiconductor chips for a long period of time when thin semiconductor chips are used.
    • SUMMARY
  • Accordingly, the present invention aims to provide a rigid-flexible printed circuit board having a cavity of a level difference in the surface of the substrate, on which semiconductor chips are mounted.
  • Also, the present invention aims to provide a rigid-flexible printed circuit board which can lower a thickness of whole packages when same numbers of the semiconductor chips are mounted.
  • Also, the present invention aims to provide a rigid-flexible printed circuit board in which the packaging of 2 or more semiconductor chips is possible using a space the same as a thickness of a core layer.
  • Also, the present invention aims to provide a rigid-flexible printed circuit board which can lower board warpage by using a thick core layer.
  • Also, the present invention aims to provide a rigid-flexible printed circuit board which can form a fine pattern using a flexible copper clad laminate (FCCL).
  • One aspect of the present invention provides a rigid-flexible multi-layer printed circuit board comprising: a flexible substrate of which circuits are formed on both sides and which is bendable; a rigid substrate having a cavity which is laminated on the flexible substrate and of which circuits are formed on both sides and semiconductor chips can be mounted in the cavity; and a bonding sheet adhering the flexible substrate and the rigid substrate and having a insulating property.
  • Here, the rigid substrate is thicker than the flexible substrate.
  • Also, wire bonding pads for electrical connection with the semiconductor chips are formed on the flexible substrate within the cavity and on the rigid substrate of the edge of opening part of the cavity.
  • Further, the flexible substrate and the rigid substrate are connected electrically therebetween through inner via holes or blind via holes.
  • Also, a plurality of the rigid substrates having the cavity are laminated with a predetermined gap on the flexible substrate and package on package (POP) is formed by folding the flexible substrate having the predetermined gap after semiconductor chips are mounted within the cavity.
  • Another aspect of the present invention provides a method for manufacturing a multi-layer rigid-flexible printed circuit board comprising: (a) forming a single circuit on a flexible substrate; (b) laminating a rigid substrate having a circuit and a cavity on the flexible substrate; (c) drilling via holes interconnecting the flexible substrate and the rigid substrate; (d) plating the via holes; (e) forming an outer circuit on a laminate of the flexible substrate and the rigid substrate; and (f) forming wire bonding pads for electrical connection with semiconductor chips on the flexible substrate within the cavity and on the rigid substrate of the edge of the opening part of the cavity.
  • Here, at the step (a), the single circuit is formed through a roll to roll process on the flexible substrate.
  • Also, the step (b) comprises: forming the cavity on the rigid substrate by using a punch or a router.
  • Further, the step (b) further comprises (b-1) laminating with pressure by using a bonding sheet between the flexible substrate and the rigid substrate. Here, the flexible substrate and the rigid substrate are laminated on a desired position using a rivet or a pin. Also, before the step (b-1), laminating a conformal film is further comprised so that the bonding sheet does not cover the wire bonding pads.
  • Also, in the step (b), a plurality of the rigid substrates are laminated on the flexible substrate with a predetermined gap, and after the step (f), (g) mounting a plurality of semiconductor chips within the each cavity, and (h) folding and molding the flexible substrate laminated with the predetermined gap are further comprised.
  • Additional aspects and advantages of the present general inventive concept will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the general inventive concept.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • These and/or other aspects and advantages of the present general inventive concept will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
  • FIGS. 1 a and 1 b show the figures of the structure of POP according to the conventional technology and recent tendency;
  • FIG. 2 shows a thinner package according to an embodiment of the present invention in comparison with the conventional invention;
  • FIGS. 3 a to 3 j illustrate a method for forming a cavity to mount semiconductor chips on a rigid-flexible printed circuit board according to an embodiment of the present invention;
  • FIG. 4 a is a cross sectional view of the rigid-flexible printed circuit board manufactured by the processes shown in FIGS. 3 a to 3 j;
  • FIG. 4 b is a plan view of the rigid-flexible printed circuit board shown in FIG. 4 a;
  • FIG. 5 a shows the unfolded rigid-flexible printed circuit board for POP according to an embodiment of the present invention;
  • FIG. 5 b is an exemplary view illustrating the smaller rigid-flexible printed circuit board for POP shown in FIG. 5 a by folding itself.
    • DETAILED DESCRIPTION
  • Hereinafter, embodiments of the invention will be described in more detail with reference to the accompanying drawings. In the description with reference to the accompanying drawings, those components are rendered the same reference number that are the same or are in correspondence regardless of the figure number, and redundant explanations are omitted.
  • FIG. 2 shows a thinner package according to an embodiment of the present invention, in comparison with the conventional invention. A bottom substrate of a POP package is shown in FIG. 2.
  • Referring to FIG. 2, a package on the left side is a stack package on which 2 or more semiconductor chips 100 and 110 are mounted according to a conventional technology. A package on the right side has a cavity 200 according to an embodiment of the present invention and the semiconductor chips 100 and 110 are mounted therein so that a whole thickness of the POP package is reduced to H3. Therefore, the whole thickness of a POP package can be thinner by using a printed circuit board having a cavity formed to have a level difference in the surface of a substrate according to the present invention.
  • FIGS. 3 a to 3 j illustrate a method for forming a cavity to mount semiconductor chips on a rigid-flexible printed circuit board according to an embodiment of the present invention.
  • Referring to FIG. 3 a, circuits and a cavity 310 are formed in a core layer 30.
  • First, an inner layer circuit 305 is formed on single side surface or double side surfaces of a resin layer of a copper clad laminate (CCL) 300 forming the core layer 30. In the present invention, the copper clad laminate 300 forming the core layer 30 is preferably a rigid substrate.
  • The inner layer circuit 305 is formed on the copper clad laminate or the substrate which copper plating is completed with a desired shape. The inner layer circuit 305 is formed by spreading a photosensitive photo resist on the substrate, adhering closely a photo mask on the substrate, forming a desired circuit on the photo resist using ultraviolet rays and etching unnecessary copper using a chemical reaction.
  • The inner layer circuit 305 can be formed by a subtractive process or additive process according to a manufacturing process.
  • The subtractive process is also termed as a ‘tent and etch process’ because etching is generally performed after tenting on parts where the circuit will be formed and the inner part of holes with the photo resist. The process involves exposing copper parts where circuits will be formed, etching the rest copper parts, and forming a circuit. Therefore, it is the process of removing copper used as a chemical. On the other hand, an additive process is a process forming a circuit by adding copper.
  • It is preferable that the inner layer circuit 305 be formed by the subtractive process and an outer layer circuit be formed by the additive process or a semi-additive process which is modification of the additive process. However, it is obvious that the inner layer circuit 305 or the outer layer circuit may be formed by various other processes.
  • Although the description below will focus on a case where the inner layer circuit 305 is formed by the subtractive process, this shall not limit the scope of the present invention.
  • In FIG. 3 a, the copper clad laminate 300 forming the core layer is arranged. And holes 350 are formed as follows: drilling process using a mechanical drill, a punch, a router or a laser drill (namely, CO2 laser drill or Nd-Yag laser drill) and copper plating process through a chemical copper plating and an electrical copper plating. Through mask process and etching process, the inner layer circuit 305 is formed and an inspection of the inner layer circuit 305 is performed whether it is formed properly or not.
  • The holes 350 are preferably inner via holes (IVH). The inner via holes are blind and buried via holes, which interconnect between 2 or more conductive layers of a multi-layer printed circuit board but does not penetrate the multi-layer printed circuit board.
  • The cavity 310 for mounting semiconductor chips may be formed when the drilling process for forming the hole 350 is performed or separately through punching or mechanical drilling using a router or laser drilling using a CO2 laser drill or Nd-Yag laser drill after the inner layer circuit 305 is formed.
  • In the present invention, the core layer 30 is preferably thicker than a flexible substrate (FCCL) 330, by which unwanted parts of the FCCL 330 are prevented from bending. Namely, the warpage can be prevented.
  • Referring to FIG. 3 b, a FCCL 330 is prepared. And a single side surface circuit 335 is formed by a roll-to-roll process. A via land where a via will be formed and a circuit pattern are formed.
  • Herein, the roll-to-roll process is a process using rolls in order to support the FCCL 330 flatly and form a single side surface circuit 335 because the FCCL 330 is thin and bendable.
  • A feeder part and a winder part have each roll. The FCCL 330 is maintained the flat while it is rolled from the feeder part to the winder part. While the FCCL 330 is moving from the feeder part to the winder part, the single side surface circuit 335 is formed through a general process such as dry film lamination, exposure, developing, drilling, routing, and plating, etc.
  • Referring to FIG. 3 c, the core layer 30 and the FCCL 330, in which each circuit is formed, are laminated using a bonding sheet 340. During the above laminating, a laminating using rivet or pin is performed in order to provide accurate align of the core layer 30 and the FCCL 330. The bonding sheet 340 is a sheet made of an adhesive material in order to glue each layer, and it may be a prepreg or a bonding film.
  • A pad part (A in FIG. 3 e) is not covered by the bonding sheet 340 when the core layer 30 and the FCCL 330 are laminated by using the bonding sheet 340, as shown in FIGS. 3 d and 3 e.
  • Referring to FIGS. 3 d and 3 e, a conformal film 342 is used so that the bonding sheet 340 does not cover the pad part (A in FIG. 3 e) where the circuit formed in the inner layer is connected when semiconductor chips are mounted. Also, the conformal film 342 provides uniform pressure to the substrate by filling the cavity 310 with its melted one while the laminating process. The bonding sheet 340 thus allows that the core layer 30 adheres to the FCCL 330 with the even pressure. Polyethylene film or polyvinyl chloride film can be used as the conformal film 342.
  • At this time, a dummy board 344 is used as buffer to protect not to concentrate the pressure to the edge of the opening part of the cavity 310 and prevents damage of the circuit. And a release film 346 is used in order to remove easily the dummy film 344 from the substrate later.
  • The conformal film 342, the dummy film 344 and the release film 346 are removed, and a multi-layer printed circuit board, on which the FCCL 330 and the core layer 30, in which the cavity 310 is formed, are laminated, is formed as shown in FIG. 3 f.
  • Referring to FIG. 3 g, vias 360 are formed in the insulation parts of the FCCL 330 by using a laser drill (namely, a CO2 laser drill or Nd-Yag laser drill) on the laminate shown in FIG. 3 f. The vias 360 provide electrical connection between the circuits 335 formed on the surface of the FCCL 330 and interconnect between the FCCL 330 and the core layer 30. Size of the via and drilling condition may be determined according to a thickness of the FCCL 330 and a thickness of the bonding sheet 340. The via 360 is preferably blind via hole.
  • Referring to FIG. 3 h, the core layer 30 and the FCCL 330 are connected by forming a seed layer after a surface treatment (IAR: ion assisted reaction) of the part where the via 360 is formed, and plating 362. The seed layer may be formed by chemical plating or sputtering, and after plating, the via part is plated through electrolytic plating. For example, the seed layer is copper-plating having a thickness of 0.3 to 1.5 μm, and the seed layer is further plated to provide a thickness of about 10 μm through the electrolytic plating.
  • In the above plating process, the part except the via 360 is covered with a protection film in order to protect the pad part of the core layer 30 and the FCCL 330 (A in FIG. 3 e).
  • Referring to FIG. 3 i, an outer circuit 364 is formed on both sides of the laminate in which the via 360 is formed and which is plated. The outer circuit 364 is formed by laminating a dry film, etching the copper of unnecessary parts, except the part being a via or a circuit through the tenting method and forming the circuit. This is possible by the above process described referring to FIG. 3 a.
  • Referring to FIG. 3 j, photo solder resist (PSR) printing is performed for the protection of the outer circuit 364. The outer circuit is protected by coating with the solder resist 370. PSR ink, as the solder resist 370, is used in order that solder, which is used so as to mount components on the printed circuit board, is adhered on necessary parts and is thus prevented from being adhered on unnecessary parts. Because of properties of the PSR ink, the PSR ink helps the solder not to adhere on parts where the PSR ink is remained and to adhere on parts where the PSR ink is not remained so that electronic components can be mounted on the parts where the solder is adhered. Also, the PSR ink is coated in order to protect the surface circuit of the printed circuit board from an outer environment.
  • The solder mask printing process comprises forming roughness on the outer circuit 364 in order that the PSR ink can adhere well with the printed circuit board, removing pollutants, coating with the PSR ink by using a screen printing method or a spray coating method, exposing, developing and complete hardening.
  • Also, in the case of mounting semiconductor chip within the cavity 310, a wire bonding pad 320 is formed through the electrolytic gold-plating or the electroless gold-plating in order to connect electrically between the core layer 30 and the FCCL 330. Through the gold-plating, electrical connection and protection from the outer environment are possible.
  • The electrolytic gold-plating is a plating method by extracting gold electrically, and is divided to soft gold and hard gold according to the hardness of gold. Soft gold is applied to products which bonding properties are needed, such as ball grid array and the like, and hard gold is applied to products needing high abrasion resistance and electrical properties. The electroless gold-plating is a plating method by using a chemical reaction not through electric, and is divided to flash plating and thickness plating according to a thickness of the gold-plating.
  • In the present invention, the wire bonding pad 320 has preferably two layers each formed on the core layer 30 and the FCCL 330 in order to mount two or more semiconductor chips.
  • Also, at the time forming POP, a bump forming pad (not shown), on which the bump can be formed for connecting electrically with another printed circuit board package laminated on the printed circuit board package in FIG. 3 j and maintaining a lamination gap, is formed on the core layer 30. The bump forming pad may also be formed through the electrolytic or electroless gold-plating. Electrical connection and protection from the outer environment is possible by the gold-plating.
  • FIG. 4 a is a cross section of the rigid-flexible printed circuit board manufactured by the processes shown in FIGS. 3 a to 3 j, and FIG. 4 b is a plan view of the rigid-flexible printed circuit board shown in FIG. 4 a.
  • Referring to FIG. 4 a, the rigid-flexible printed circuit board comprises a core layer 30, an FCCL 330, a bonding sheet 340, a cavity 310 within the core layer 30, a wire bonding pad 320 and vias 350.
  • Referring to FIG. 4 b, the core layer 30 is laminated on the FCCL 330, and the cavity 310, within which a semiconductor chip can be mounted, is formed in the core layer 30. The wire bonding pad 320 for electrical connection with the semiconductor chip is formed on the A part of the FCCL 330 exposed through the cavity 310. And another wire bonding pad 320 for electrical connection with the semiconductor chip is formed on the edge of the opening part of the cavity 310 of the core layer 30.
  • And a bump forming pad, namely a ball pad 400, on which the bump can be formed for connecting electrically with another printed circuit board package on the printed circuit board package in FIG. 3 j and maintaining the lamination gap, is formed on the core layer 30.
  • FIG. 5 a shows the unfolded rigid-flexible printed circuit board for POP according to an embodiment of the present invention and FIG. 5 b is an exemplary view illustrating the smaller rigid-flexible printed circuit board for POP shown in FIG. 5 a by folding itself.
  • Referring to FIG. 5 a, two core layers 30 having the cavity 310 shown in FIG. 4 b are laminated on the FCCL 330 with a predetermined gap.
  • And then, each core layer 30 is laminated each other by folding the center part of the FCCL 330 where the core layer 30 is not laminated as shown in FIG. 5 b. At this time, the electrical connection and the gap between the packages can be maintained by forming the bump 510 on the ball pad 400.
  • The miniaturized rigid-flexible printed circuit board for POP may be stably mounted in products by maintaining the folded shape through molding.
  • As described above, the rigid-flexible printed circuit board of the present invention is manufactured to have a level difference in the surface of a substrate by forming a cavity in the part on which semiconductor chips are mounted.
  • Also, when the same numbers of semiconductor chips are mounted, a thickness of the whole package can be reduced or when POP is embodied, a whole thickness of the package can be lower.
  • Also, two or more semiconductor chips can be mounted using the same space as a thickness of the core layer, and when the number of semiconductor chip to be mounted on the bottom of the substrate is increased from 1 to 2, it becomes possible which was impossible with the conventional flexible printed circuit.
  • Also, board warpage may be reduced by using a thick core layer.
  • Also, a fine pattern may be formed by using a flexible substrate.
  • While the above description has pointed out novel features of the invention as applied to various embodiments, the skilled person will understand that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made without departing from the scope of the invention. Therefore, the scope of the invention is defined by the appended claims rather than by the foregoing description. All variations coming within the meaning and range of equivalency of the claims are embraced within their scope.

Claims (12)

1. A rigid-flexible multi-layer printed circuit board comprising:
a flexible substrate of which circuits are formed on both sides and which is bendable;
a rigid substrate having a cavity which is laminated on the flexible substrate and of which circuits are formed on both sides and semiconductor chips can be mounted in the cavity; and
a bonding sheet adhering the flexible substrate and the rigid substrate and having a insulating property.
2. The rigid-flexible multi-layer printed circuit board of claim 1, wherein the rigid substrate is thicker than the flexible substrate.
3. The rigid-flexible multi-layer printed circuit board of claim 1, wherein wire bonding pads for electrical connection with the semiconductor chips are formed on the flexible substrate within the cavity and on the rigid substrate of the edge of opening part of the cavity.
4. The rigid-flexible multi-layer printed circuit board of claim 1, wherein the flexible substrate and the rigid substrate are connected electrically therebetween through inner via holes or blind via holes.
5. The rigid-flexible multi-layer printed circuit board of claim 1, wherein a plurality of the rigid substrates having the cavity are laminated with a predetermined gap on the flexible substrate and package on package (POP) is formed by folding the flexible substrate having the predetermined gap after semiconductor chips are mounted within the cavity.
6. A method for manufacturing a multi-layer rigid-flexible printed circuit board comprising:
(a) forming a single circuit on a flexible substrate;
(b) laminating a rigid substrate having a circuit and a cavity on the flexible substrate;
(c) drilling via holes interconnecting the flexible substrate and the rigid substrate;
(d) plating the via holes;
(e) forming an outer circuit on a laminate of the flexible substrate and the rigid substrate; and
(f) forming wire bonding pads for electrical connection with semiconductor chips on the flexible substrate within the cavity and on the rigid substrate of the edge of the opening part of the cavity.
7. The method for manufacturing a multi-layer rigid-flexible printed circuit board of claim 6, wherein at the step (a), the single circuit is formed through a roll to roll process on the flexible substrate.
8. The method for manufacturing a multi-layer rigid-flexible printed circuit board of claim 6, wherein the step (b) comprises: forming the cavity on the rigid substrate by using a punch or a router.
9. The method for manufacturing a multi-layer rigid-flexible printed circuit board of claim 6, wherein the step (b) further comprises (b-1) laminating with pressure by using a bonding sheet between the flexible substrate and the rigid substrate.
10. The method for manufacturing a multi-layer rigid-flexible printed circuit board of claim 9, wherein the flexible substrate and the rigid substrate are laminated on a desired position using a rivet or a pin.
11. The method for manufacturing a multi-layer rigid-flexible printed circuit board of claim 9, wherein before the step (b-1), laminating a conformal film is further comprised so that the bonding sheet does not cover the wire bonding pads.
12. The method for manufacturing a multi-layer rigid-flexible printed circuit board of claim 6, wherein in the step (b), a plurality of the rigid substrates are laminated on the flexible substrate with a predetermined gap, and
after the step (f),
(g) mounting a plurality of semiconductor chips within the each cavity, and
(h) folding and molding the flexible substrate laminated with the predetermined gap are further comprised.
US11/520,730 2005-09-14 2006-09-14 Rigid-flexible printed circuit board for package on package and manufacturing method Abandoned US20070059918A1 (en)

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Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080258286A1 (en) * 2007-04-23 2008-10-23 Texas Instruments Incorporated High Input/Output, Low Profile Package-On-Package Semiconductor System
US20080283992A1 (en) * 2007-05-17 2008-11-20 Texas Instruments Incorporated Multi layer low cost cavity substrate fabrication for pop packages
KR100920825B1 (en) 2007-12-03 2009-10-08 삼성전기주식회사 Manufacturing method of rigid-flexible printed circuit board
US20090278255A1 (en) * 2008-05-09 2009-11-12 Kouji Oomori Semiconductor device
US20120015479A1 (en) * 2008-10-14 2012-01-19 Texas Instruments Incorporated Semiconductor Package with a Mold Material Encapsulating a Chip and a Portion of a Lead Frame
WO2012160059A1 (en) * 2011-05-23 2012-11-29 Continental Automotive Gmbh Printed circuit board for electric components, and printed circuit board system
WO2013086754A1 (en) * 2011-12-12 2013-06-20 清华大学 Universal encapsulation substrate, encapsulation structure and encapsulation method
US8482133B2 (en) 2010-08-25 2013-07-09 Samsung Electronics Co., Ltd. Semiconductor package
US20130220535A1 (en) * 2012-02-24 2013-08-29 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing rigid-flexible printed circuit board
GB2483181B (en) * 2009-06-26 2014-06-18 Intel Corp Stacked-chip packages in package-on-package apparatus,methods of assembling same, and systems containing same
US8801279B2 (en) 2010-12-28 2014-08-12 Samsung Electronics Co., Ltd. Semiconductor device with stacked structure having through electrode, semiconductor memory device, semiconductor memory system, and operating method thereof
CN105006463A (en) * 2014-04-16 2015-10-28 英飞凌科技股份有限公司 Method for fabricating a semiconductor package and semiconductor package
US9780049B2 (en) 2013-05-16 2017-10-03 Samsung Electronics Co., Ltd. Semiconductor package
US20180175323A1 (en) * 2016-12-16 2018-06-21 Samsung Display Co., Ltd. Method of manufacturing a display apparatus including a bending area
US20190081379A1 (en) * 2017-09-12 2019-03-14 Knowles Cazenovia, Inc. Vertical switched filter bank
CN112053960A (en) * 2020-09-10 2020-12-08 山东傲天环保科技有限公司 High stack package structure and forming method thereof

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5413971B2 (en) 2007-07-19 2014-02-12 日本電気株式会社 Electronic component mounting apparatus and manufacturing method thereof
KR101061175B1 (en) 2008-02-18 2011-09-01 주식회사 하이닉스반도체 Semiconductor Package Substrate
JP5370765B2 (en) * 2008-09-29 2013-12-18 日立化成株式会社 Package board for mounting semiconductor device and manufacturing method thereof
KR101547257B1 (en) * 2014-02-11 2015-08-25 국립대학법인 울산과학기술대학교 산학협력단 Manufacturing method of foldable electronics and foldable electronics using the same
KR101631625B1 (en) * 2015-05-13 2016-06-17 울산과학기술원 Electronic device and manufacturing method of the same
KR20190071023A (en) * 2017-12-13 2019-06-24 현대자동차주식회사 Door for vehicle
KR102474378B1 (en) * 2017-12-13 2022-12-06 현대자동차 주식회사 Door for vehicle
KR102546473B1 (en) * 2022-03-25 2023-06-22 주식회사 에스아이 플렉스 Interlayer registration method for flexible printed circuit board
KR102546472B1 (en) * 2022-03-25 2023-06-22 주식회사 에스아이 플렉스 Interlayer registration method for flexible printed circuit board

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4887760A (en) * 1986-08-27 1989-12-19 Kabushiki Kaisha Toshiba Bonding sheet for electronic component and method of bonding electronic component using the same
US5622588A (en) * 1995-02-02 1997-04-22 Hestia Technologies, Inc. Methods of making multi-tier laminate substrates for electronic device packaging
US5776797A (en) * 1995-12-22 1998-07-07 Fairchild Space And Defense Corporation Three-dimensional flexible assembly of integrated circuits
US6417026B2 (en) * 1998-02-27 2002-07-09 Tdk Corporation Acoustic wave device face-down mounted on a substrate
US20030020153A1 (en) * 2001-07-24 2003-01-30 Ted Bruce Chip stack with differing chip package types

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0595080A (en) * 1991-10-01 1993-04-16 Ibiden Co Ltd Multi-integrated circuit mounting substrate
JPH0637408A (en) * 1992-07-13 1994-02-10 Sumitomo Electric Ind Ltd Flex-ridged printed wiring board
JP3064780B2 (en) * 1993-01-12 2000-07-12 イビデン株式会社 Manufacturing method of flex-rigid multilayer printed wiring board
JP3224889B2 (en) * 1993-01-13 2001-11-05 イビデン株式会社 Printed wiring board and its manufacturing method
JPH06334098A (en) * 1993-05-20 1994-12-02 Shinko Electric Ind Co Ltd Semiconductor device
KR100271656B1 (en) * 1998-05-30 2000-11-15 김영환 Bga semiconductor package and fabrication method thereof
KR20000059562A (en) * 1999-03-05 2000-10-05 이형도 Flexible Substrates of Multi Metal Layer
KR20020053253A (en) * 2000-12-27 2002-07-05 이중구 TBGA semiconductor package and fabrication method of the same
JP3892259B2 (en) * 2001-09-14 2007-03-14 カシオ計算機株式会社 Manufacturing method of semiconductor device
JP2003332743A (en) * 2002-05-14 2003-11-21 Olympus Optical Co Ltd Rigid flexible substrate
JP4191169B2 (en) * 2005-05-23 2008-12-03 エルピーダメモリ株式会社 Semiconductor device and mounting body

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4887760A (en) * 1986-08-27 1989-12-19 Kabushiki Kaisha Toshiba Bonding sheet for electronic component and method of bonding electronic component using the same
US5622588A (en) * 1995-02-02 1997-04-22 Hestia Technologies, Inc. Methods of making multi-tier laminate substrates for electronic device packaging
US5776797A (en) * 1995-12-22 1998-07-07 Fairchild Space And Defense Corporation Three-dimensional flexible assembly of integrated circuits
US6417026B2 (en) * 1998-02-27 2002-07-09 Tdk Corporation Acoustic wave device face-down mounted on a substrate
US20030020153A1 (en) * 2001-07-24 2003-01-30 Ted Bruce Chip stack with differing chip package types

Cited By (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080258286A1 (en) * 2007-04-23 2008-10-23 Texas Instruments Incorporated High Input/Output, Low Profile Package-On-Package Semiconductor System
US20080283992A1 (en) * 2007-05-17 2008-11-20 Texas Instruments Incorporated Multi layer low cost cavity substrate fabrication for pop packages
WO2008144460A1 (en) * 2007-05-17 2008-11-27 Texas Instruments Incorporated Multi layer low cost cavity substrate fabrication for pop packages
US7635914B2 (en) 2007-05-17 2009-12-22 Texas Instruments Incorporated Multi layer low cost cavity substrate fabrication for pop packages
WO2009026224A2 (en) * 2007-08-16 2009-02-26 Texas Instruments Incorporated High input/output, low profile package-on-package semiconductor system
WO2009026224A3 (en) * 2007-08-16 2009-05-22 Texas Instruments Inc High input/output, low profile package-on-package semiconductor system
KR100920825B1 (en) 2007-12-03 2009-10-08 삼성전기주식회사 Manufacturing method of rigid-flexible printed circuit board
US8907468B2 (en) 2008-05-09 2014-12-09 Panasonic Corporation Semiconductor device
US20090278255A1 (en) * 2008-05-09 2009-11-12 Kouji Oomori Semiconductor device
US8097962B2 (en) * 2008-05-09 2012-01-17 Panasonic Corporation Semiconductor device
US20120015479A1 (en) * 2008-10-14 2012-01-19 Texas Instruments Incorporated Semiconductor Package with a Mold Material Encapsulating a Chip and a Portion of a Lead Frame
US8569082B2 (en) * 2008-10-14 2013-10-29 Texas Instruments Incorporated Semiconductor package with a mold material encapsulating a chip and a portion of a lead frame
US11217516B2 (en) 2009-06-26 2022-01-04 Intel Corporation Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
GB2483181B (en) * 2009-06-26 2014-06-18 Intel Corp Stacked-chip packages in package-on-package apparatus,methods of assembling same, and systems containing same
US10186480B2 (en) 2009-06-26 2019-01-22 Intel Corporation Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
US8482133B2 (en) 2010-08-25 2013-07-09 Samsung Electronics Co., Ltd. Semiconductor package
US8801279B2 (en) 2010-12-28 2014-08-12 Samsung Electronics Co., Ltd. Semiconductor device with stacked structure having through electrode, semiconductor memory device, semiconductor memory system, and operating method thereof
US9185803B2 (en) 2011-05-23 2015-11-10 Continental Automotive Gmbh Circuit board for electric components and circuit board system
WO2012160059A1 (en) * 2011-05-23 2012-11-29 Continental Automotive Gmbh Printed circuit board for electric components, and printed circuit board system
WO2013086754A1 (en) * 2011-12-12 2013-06-20 清华大学 Universal encapsulation substrate, encapsulation structure and encapsulation method
US9955580B2 (en) 2012-02-24 2018-04-24 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing rigid-flexible printed circuit board
US10299373B2 (en) 2012-02-24 2019-05-21 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing rigid-flexible printed circuit board
US10091871B2 (en) 2012-02-24 2018-10-02 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing rigid-flexible printed circuit board
US8882954B2 (en) * 2012-02-24 2014-11-11 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing rigid-flexible printed circuit board
US20130220535A1 (en) * 2012-02-24 2013-08-29 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing rigid-flexible printed circuit board
US9780049B2 (en) 2013-05-16 2017-10-03 Samsung Electronics Co., Ltd. Semiconductor package
CN105006463A (en) * 2014-04-16 2015-10-28 英飞凌科技股份有限公司 Method for fabricating a semiconductor package and semiconductor package
US20180175323A1 (en) * 2016-12-16 2018-06-21 Samsung Display Co., Ltd. Method of manufacturing a display apparatus including a bending area
US10355241B2 (en) * 2016-12-16 2019-07-16 Samsung Display Co., Ltd. Method of manufacturing a display apparatus including a bending area
WO2019055436A1 (en) * 2017-09-12 2019-03-21 Knowles Cazenovia, Inc. Vertical switched filter bank
WO2019055435A1 (en) * 2017-09-12 2019-03-21 Knowles Cazenovia, Inc. Vertical switched filter bank
WO2019055438A1 (en) * 2017-09-12 2019-03-21 Knowles Cazenovia, Inc. Vertical switched filter bank
US10770776B2 (en) 2017-09-12 2020-09-08 Knowles Cazenovia, Inc. Vertical switched filter bank
US20190081379A1 (en) * 2017-09-12 2019-03-14 Knowles Cazenovia, Inc. Vertical switched filter bank
US11355829B2 (en) * 2017-09-12 2022-06-07 Knowles Cazenovia, Inc. Vertical switched filter bank
US11437696B2 (en) 2017-09-12 2022-09-06 Knowles Cazenovia, Inc. RF devices and methods thereof involving a vertical switched filter bank
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US20090233400A1 (en) 2009-09-17

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