CN112053960A - High stack package structure and forming method thereof - Google Patents
High stack package structure and forming method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention relates to a high stack package structure and a forming method thereof, wherein the method comprises the following steps: forming a first package assembly, forming a second package assembly, forming a third package assembly, disposing the first package assembly at a middle region of a flexible substrate, disposing the second package assembly at opposite side regions of the flexible substrate, then respectively forming a plurality of first through holes and second through holes disposed at intervals, then depositing a metal material in the first through holes and the second through holes to respectively form first metal pillars and second metal pillars, then disposing the third package assembly on the first package assembly, then bending the opposite side regions of the flexible substrate upward so that each of the second package assemblies is attached to a side wall of the first package assembly and a side wall of the third package assembly, and then providing a wiring substrate electrically connecting the third package assembly to the wiring substrate.
Description
Technical Field
The present invention relates to the field of semiconductor packaging, and more particularly, to a high stack package structure and a method for forming the same.
Background
With the continuous pursuit of miniaturization, systematization, multifunction and the like of electronic products, the feature size of the super-large-scale integrated circuit is continuously reduced. However, as the feature size of ICs is approaching physical limits, one has to seek new technologies, new designs, and new materials to "go beyond moore's law". The system-in-package technology represented by pop (package on package) stack is a milestone that people have on the way of exceeding moore's law. In the existing POP package structure, a small package structure is usually stacked on a side surface of a main package structure to improve the integration level of the POP package structure, and how to improve the stability of the POP package structure, which has attracted much attention.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned deficiencies in the prior art and providing a high stack package structure and a method for forming the same.
In order to achieve the above object, the present invention provides a method for forming a high stack package structure, which includes the following steps:
(1) providing a first circuit substrate, forming first conductive bumps on the edge areas of two sides of the first circuit substrate, attaching a first semiconductor die on the first circuit substrate, then forming a first plastic package layer on the first circuit substrate, wherein the first plastic package layer wraps the first conductive bumps and the first semiconductor die, a part of the first conductive bumps is exposed from the side surface of the first plastic package layer, and then planting balls on the back surface of the first circuit substrate to form a first packaging assembly.
(2) Providing a second circuit substrate, mounting a second semiconductor tube core on the second circuit substrate, forming a second plastic package layer on the second circuit substrate, wrapping the second semiconductor tube core by the first plastic package layer, and planting balls on the back surface of the second circuit substrate to form a second packaging assembly.
(3) Providing a third circuit substrate, forming second conductive bumps on the edge areas of two sides of the third circuit substrate, forming a third conductive bump on the third circuit substrate, attaching a third semiconductor die on the third circuit substrate, then forming a third plastic package layer on the third circuit substrate, wrapping the third plastic package layer on the second conductive bump, the third conductive bump and the third semiconductor die, exposing one part of the second conductive bump from the side surface of the third plastic package layer, exposing one part of the third conductive bump from the top surface of the third plastic package layer, and then planting balls on the back surface of the third circuit substrate to form a third package assembly.
(4) Providing a flexible substrate, arranging the first packaging assembly in the middle area of the flexible substrate in a mode that the top surface of the first plastic packaging layer faces the flexible substrate, arranging two second packaging assemblies in two opposite side areas of the flexible substrate respectively in a mode that the top surface of the second plastic packaging layer faces the flexible substrate, and then arranging a first temporary bearing substrate on the first packaging assembly and the second packaging assembly.
(5) And then, etching the middle region of the flexible substrate, the first molding layer and the first semiconductor die from the back side of the flexible substrate to form a plurality of first through holes arranged at intervals in the first semiconductor die, wherein the depth of the first through holes in the middle region of the first semiconductor die is shallow, and the depth of the first through holes in the edge region of the first semiconductor die is deep.
(6) And then, etching the two opposite side edge regions of the flexible substrate, the second molding layer and the second semiconductor die from the back surface of the flexible substrate to form a plurality of second through holes arranged at intervals in the second semiconductor die, wherein the depth of the second through holes in the middle region of the second semiconductor die is shallow, and the depth of the second through holes in the edge region of the second semiconductor die is deep.
(7) A metal material is then deposited in the first and second vias to form first and second metal pillars, respectively.
(8) And arranging a second temporary bearing substrate on the bottom surface of the flexible substrate, removing the first temporary bearing substrate, arranging the third packaging assembly on the first packaging assembly, enabling the welding balls of the first packaging assembly to be in direct contact with the third conductive bumps of the third packaging assembly, and bending two opposite side edge areas of the flexible substrate upwards, so that each second packaging assembly is attached to the side wall of the first packaging assembly and the side wall of the third packaging assembly, and each second packaging assembly is electrically connected to the first packaging assembly and the third packaging assembly.
(9) Providing a circuit substrate, electrically connecting the third package assembly to the circuit substrate, and then removing the second temporary carrier substrate.
Preferably, in the step (1), a first photoresist mask is formed on the first circuit substrate, the first photoresist mask is reserved with an opening, then a conductive material is deposited in the opening and on the upper surface of the first photoresist mask to form a first conductive layer, then the first conductive layer is subjected to patterning treatment, then the first photoresist mask is removed to form
The first conductive bump is patterned.
Preferably, in the step (3), a second photoresist mask is formed on the third circuit substrate, a first opening is formed in the second photoresist mask, a conductive material is deposited in the first opening to form the third conductive bump, then a portion of the second photoresist mask is thinned to form a third photoresist mask, a second opening is formed in the third photoresist mask, then a second conductive layer is formed in the second opening and a portion of an upper surface of the third photoresist mask, then the second conductive layer is patterned, and then the third photoresist mask is removed to form the third photoresist mask
The second conductive bump is of a type.
Preferably, in the step (4), the flexible substrate is one of a polyimide substrate, a polyethylene terephthalate substrate, a polyethersulfone substrate, a thermoplastic polyurethane substrate, a polycarbonate substrate, an epoxy resin substrate, and a phenol resin substrate, and the first temporary carrier substrate is one of a stainless steel substrate, a copper substrate, an iron substrate, and a ceramic substrate.
Preferably, in the step (5), the plurality of spaced first through holes extend along a straight line, wherein the depth of the first through hole located in the middle region of the first semiconductor die is 50-90 microns, and the depth of the first through hole located in the edge region of the first semiconductor die is 100-180 microns.
Preferably, in step (6), the plurality of spaced apart second perforations extend along a straight line, wherein the second perforations located in the middle region of the second semiconductor die have a depth of 30-60 microns and the second perforations located in the edge region of the second semiconductor die have a depth of 80-150 microns.
Preferably, in the step (7), the metal material is one of copper, aluminum and silver, and the first metal pillar and the second metal pillar each have a portion protruding from the flexible substrate.
Preferably, in the step (8), an adhesion preventing layer is coated on a peripheral region of the second temporary carrier substrate, and then a temporary adhesion layer is coated on a middle region of the second temporary carrier substrate, the flexible substrate corresponding to the first encapsulation member is adhered to the temporary adhesion layer, and the flexible substrate corresponding to the second encapsulation member is disposed on the adhesion preventing layer.
The invention also provides a high stack packaging structure which is formed by adopting the method.
Compared with the prior art, the invention has the following advantages:
in the formation process of the high stack package structure of the present invention, the first conductive bump exposed from the side surface of the first plastic package layer is formed in the first package component, and the second conductive bump exposed from the side surface of the third plastic package layer and the third conductive bump exposed from the top surface of the third plastic package layer are formed in the third package component, so as to facilitate the electrical connection of the first, second and third package components. The first packaging assembly is arranged in the middle area of the flexible substrate, the two second packaging assemblies are arranged in the two opposite side areas of the flexible substrate respectively, the first through holes and the second through holes are formed through an etching treatment process respectively, the stability of the packaging structure can be improved on the one hand by optimizing the specific sizes of the first through holes and the second through holes, and on the other hand, the function of a semiconductor tube core is not influenced. Through deposit metal material in first perforation and second perforation in order to form first metal post and second metal post respectively, the joint steadiness between encapsulation subassembly and the flexible substrate can be strengthened to this first metal post and second metal post's existence, can effectively prevent high stacked package structure breakage.
Drawings
Fig. 1-8 are schematic structural diagrams illustrating processes for forming a high package on package structure according to an embodiment of the invention.
Detailed Description
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements thereof are described below to simplify the description of the disclosure. These are, of course, merely examples and are not intended to limit the disclosure. For example, the following disclosure describes forming a first feature over or on a second feature, including embodiments in which the first feature and the second feature are formed in direct contact, and also including embodiments in which additional features may be formed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact. In addition, various examples of the disclosure may use repeated reference characters and/or wording. The repeated symbols or words are for purposes of simplicity and clarity, and
and are not intended to limit the relationship between the various embodiments and/or the appearance structures.
Furthermore, spatially relative terms, such as "under", "below", "lower", "over", "upper" and the like, may be used herein for convenience in describing the relationship of one element or component to another element(s) or component(s) in the figures. Spatially relative terms may also encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate. In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
Please refer to fig. 1 to 8. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1 to 8, the present embodiment provides a high stack package structure and a method for forming the same.
In this embodiment, as shown in fig. 1, step (1) is performed to provide a first circuit substrate 100, form first conductive bumps 101 on two side edge regions of the first circuit substrate 100, attach a first semiconductor die 102 to the first circuit substrate 100, then form a first molding layer 103 on the first circuit substrate 100, the first molding layer 103 wraps the first conductive bumps 101 and the first semiconductor die 102, a portion of the first conductive bumps 101 is exposed from a side surface of the first molding layer 103, and then attach balls 104 on a back surface of the first circuit substrate 100 to form a first package assembly.
The specific process for forming the first conductive bump 101 is as follows: forming a first photoresist mask on the first circuit substrate 100, wherein an opening is reserved in the first photoresist mask, depositing a conductive material in the opening and on the upper surface of the first photoresist mask to form a first conductive layer, patterning the first conductive layer, and removing the first photoresist mask to form a second conductive layer
The first conductive bump 101, wherein the conductive material may be one or more of copper, aluminum, nickel, titanium, palladium, silver, tungsten, and chromium, and the thermally conductive material is formed by electroplating, electroless plating, chemical vapor deposition, or physical vapor deposition. More specifically, the conductive material includes copper, which is formed through an electroplating process.
In a specific embodiment, the first circuit substrate 100 may specifically be a printed circuit board, a ceramic circuit substrate, or a metal circuit substrate, and the first semiconductor die 102 may be a transistor, a thyristor, a diode, a logic processing chip, an SOC chip, or other suitable chip.
In other embodiments, a first semiconductor die 102 may be mounted on the first circuit substrate 100, a molding compound is formed to wrap the first circuit substrate 100 and the first semiconductor die 102, and then two side regions of the molding compound are thinned, and then two side regions of the molding compound are mounted on the first circuit substrate 100 and the first semiconductor die 102The side region forms an opening exposing the first circuit substrate 100, and then a conductive material is deposited in the both side regions and the opening to form a first conductive layer, followed by patterning the first conductive layer to form
Then, a molding layer is formed on the two side regions to cover the upper surface of the first conductive bump 101, and a portion of the first conductive bump 101 is exposed from the side surface of the molding layer.
In this embodiment, as shown in fig. 2, step (2) is performed to provide a second circuit substrate 200, attach a second semiconductor die 201 on the second circuit substrate 200, form a second molding layer 202 on the second circuit substrate 200, wrap the second semiconductor die 201 with the first molding layer 202, and then plant balls 203 on the back surface of the second circuit substrate 200 to form a second package assembly.
In a specific embodiment, the second circuit substrate 200 may be a printed circuit board, a ceramic circuit substrate, or a metal circuit substrate, and the second semiconductor die 201 may be a transistor, a thyristor, a diode, a logic processing chip, an SOC chip, or other suitable chips.
In this embodiment, as shown in fig. 3, step (3) is performed to provide a third circuit substrate 300, form second conductive bumps 301 on two side edge regions of the third circuit substrate 300, form a third conductive bump 302 on the third circuit substrate 300, attach a third semiconductor die 303 on the third circuit substrate 300, form a third molding layer 304 on the third circuit substrate 300, the third molding layer 304 wraps the second conductive bumps 301, the third conductive bumps 302 and the third semiconductor die 303, a portion of the second conductive bumps 301 is exposed from a side surface of the third molding layer 304, a portion of the third conductive bumps 302 is exposed from a top surface of the third molding layer 304, and then implant balls 305 on a back surface of the third circuit substrate 300 to form a third package assembly.
The specific process for forming the second conductive bump 301 and the third conductive bump 302 is as follows: forming a second photoresist mask on the third circuit substrate 300, forming a first opening in the second photoresist mask, depositing a conductive material in the first opening to form the third conductive bump 302, then performing a thinning process on a portion of the second photoresist mask to form a third photoresist mask, forming a second opening in the third photoresist mask, then forming a second conductive layer in the second opening and a portion of an upper surface of the third photoresist mask, then performing a patterning process on the second conductive layer, and then removing the third photoresist mask to form a third conductive bump 302
The second conductive bump 301 is of a type. Wherein the conductive material can be one or more of copper, aluminum, nickel, titanium, palladium, silver, tungsten and chromium, and the conductive material is formed by electroplating, chemical plating, chemical vapor deposition or physical vapor deposition. More specifically, the conductive material includes copper, which is formed through an electroplating process.
In a specific embodiment, the third circuit substrate 300 may be a printed circuit board, a ceramic circuit substrate, or a metal circuit substrate, and the third semiconductor die 303 may be a transistor, a thyristor, a diode, a logic processing chip, an SOC chip, or other suitable chips.
In other embodiments, a third semiconductor die 303 may be mounted on the third circuit substrate 300, a molding compound is formed to wrap the third circuit substrate 300 and the third semiconductor die 303, a first opening is formed in the molding compound, a conductive material is deposited in the first opening to form the third conductive bump 302, two side regions of the molding compound are thinned, a second opening is formed in the two side regions, a conductive material is deposited in the two side regions and the second opening to form a second conductive layer, and the second conductive layer is patternedPatterning to form
Then, a molding layer is formed on the two side regions to cover the upper surface of the second conductive bump 301, such that a portion of the second conductive bump 301 is exposed from the side surface of the molding layer, and a portion of the third conductive bump 302 is exposed from the top surface of the molding layer 304.
In this embodiment, as shown in fig. 4, step (4) is performed to provide a flexible substrate 400, to dispose the first package assembly on the middle region of the flexible substrate 400 with the top surface of the first molding compound layer 103 facing the flexible substrate 400, to dispose two second package assemblies on two opposite side regions of the flexible substrate 400 with the top surface of the second molding compound layer 202 facing the flexible substrate 400, and to dispose a first temporary carrier substrate 401 on the first and second package assemblies.
Wherein, in the step (4), the flexible substrate 400 is one of a polyimide substrate, a polyethylene terephthalate substrate, a polyethersulfone substrate, a thermoplastic polyurethane substrate, a polycarbonate substrate, an epoxy resin substrate, and a phenol resin substrate, and the first temporary carrier substrate 401 is one of a stainless steel substrate, a copper substrate, an iron substrate, and a ceramic substrate. In a specific embodiment, the flexible substrate 400 is a polyimide substrate, and the first temporary carrier substrate 401 is a stainless steel substrate.
In this embodiment, as shown in fig. 5, step (5) is performed, and then an etching process is performed on the middle region of the flexible substrate 400, the first molding layer 103, and the first semiconductor die 102 from the back side of the flexible substrate 400 to form a plurality of first through holes 1021 arranged at intervals in the first semiconductor die, where the first through holes 1021 in the middle region of the first semiconductor die 102 have a shallow depth, and the first through holes 1021 in the edge region of the first semiconductor die 102 have a deep depth.
In the step (5), the plurality of first through holes 1021 arranged at intervals extend along a straight line, wherein the depth of the first through holes 1021 in the middle region of the first semiconductor die is 50-90 microns, and the depth of the first through holes 1021 in the edge region of the first semiconductor die is 100-180 microns.
In a specific embodiment, the first through hole 1021 is formed by wet solution etching or by a laser etching process, the depth of the first through hole 1021 in the middle region of the first semiconductor die is 50 microns, 60 microns, 70 microns, 80 microns or 90 microns, and the depth of the first through hole 1021 in the edge region of the first semiconductor die is 100 microns, 110 microns, 120 microns, 130 microns, 140 microns, 150 microns, 160 microns, 170 microns or 180 microns.
In this embodiment, as shown in fig. 5, step (6) is performed, and then, etching processes are performed on two opposite side regions of the flexible substrate, the second molding layer 202, and the second semiconductor die 201 from the back side of the flexible substrate 400 to form a plurality of second through holes 2011 arranged at intervals in the second semiconductor die 201, where the second through holes 2011 located in a middle region of the second semiconductor die have a shallow depth, and the second through holes 2011 located in an edge region of the second semiconductor die have a deep depth.
In step (6), the plurality of spaced apart second through holes 2011 extend along a straight line, wherein the second through holes 2011 in the middle region of the second semiconductor die have a depth of 30-60 microns and the second through holes 2011 in the edge region of the second semiconductor die have a depth of 80-150 microns.
In a specific embodiment, the second through-hole 2011 is formed by wet solution etching or laser etching, the depth of the second through-hole 2011 in the middle region of the second semiconductor die is 30 microns, 40 microns, 50 microns or 60 microns, and the depth of the second through-hole 2011 in the edge region of the second semiconductor die is 80 microns, 90 microns, 100 microns, 110 microns, 120 microns, 130 microns, 140 microns or 150 microns.
In the present embodiment, as shown in fig. 6, step (7) is performed next, and then a metal material is deposited in the first through hole 1021 and the second through hole 2011 to form a first metal pillar 501 and a second metal pillar 502, respectively.
In the step (7), the metal material is one of copper, aluminum and silver, and the first metal pillar 501 and the second metal pillar 502 each have a portion protruding from the flexible substrate 400.
In a specific embodiment, the widths of the portions of the first metal pillar 501 and the second metal pillar 502 protruding out of the flexible substrate 400 are greater than the widths of the first metal pillar 501 and the second metal pillar 502 in the first through hole 1021 and the second through hole 2011, so that the mechanical robustness of the flexible substrate can be effectively improved.
In this embodiment, as shown in fig. 7, next, step (8) is performed, a second temporary carrier substrate 600 is disposed on the bottom surface of the flexible substrate 400, the first temporary carrier substrate 401 is then removed, the third package component is then provided on the first package component, and the solder balls 104 of the first package component directly contact the third conductive bumps 302 of the third package component, then bending two opposite side edge regions of the flexible substrate upward so that each of the second package assemblies is attached to the side wall of the first package assembly and the side wall of the third package assembly, and each of the second package components is electrically connected to the first and third package components, such that the back-side ball-planting 203 of the second circuit substrate 200 is electrically connected to the first conductive bump 101 and the second conductive bump 301.
In the step (8), an adhesion preventing layer is coated on a peripheral region of the second temporary carrier substrate 600, and then a temporary adhesion layer is coated on a middle region of the second temporary carrier substrate 600, the flexible substrate corresponding to the first encapsulation member is adhered to the temporary adhesion layer, and the flexible substrate corresponding to the second encapsulation member is disposed on the adhesion preventing layer, so that two opposite side regions of the flexible substrate 400 are bent upward. The adhesion prevention layer may be a hydrophobic organic material.
In this embodiment, as shown in fig. 8, step (9) is performed to provide a circuit substrate 700, electrically connect the third package assembly to the circuit substrate 700, and then remove the second temporary carrier substrate 600.
As shown in fig. 8, the present invention further provides a high stack package structure formed by the above method.
In other embodiments, the present invention discloses a method for forming a high stack package structure, which includes the following steps:
(1) providing a first circuit substrate, forming first conductive bumps on the edge areas of two sides of the first circuit substrate, attaching a first semiconductor die on the first circuit substrate, then forming a first plastic package layer on the first circuit substrate, wherein the first plastic package layer wraps the first conductive bumps and the first semiconductor die, a part of the first conductive bumps is exposed from the side surface of the first plastic package layer, and then planting balls on the back surface of the first circuit substrate to form a first packaging assembly.
(2) Providing a second circuit substrate, mounting a second semiconductor tube core on the second circuit substrate, forming a second plastic package layer on the second circuit substrate, wrapping the second semiconductor tube core by the first plastic package layer, and planting balls on the back surface of the second circuit substrate to form a second packaging assembly.
(3) Providing a third circuit substrate, forming second conductive bumps on the edge areas of two sides of the third circuit substrate, forming a third conductive bump on the third circuit substrate, attaching a third semiconductor die on the third circuit substrate, then forming a third plastic package layer on the third circuit substrate, wrapping the third plastic package layer on the second conductive bump, the third conductive bump and the third semiconductor die, exposing one part of the second conductive bump from the side surface of the third plastic package layer, exposing one part of the third conductive bump from the top surface of the third plastic package layer, and then planting balls on the back surface of the third circuit substrate to form a third package assembly.
(4) Providing a flexible substrate, arranging the first packaging assembly in the middle area of the flexible substrate in a mode that the top surface of the first plastic packaging layer faces the flexible substrate, arranging two second packaging assemblies in two opposite side areas of the flexible substrate respectively in a mode that the top surface of the second plastic packaging layer faces the flexible substrate, and then arranging a first temporary bearing substrate on the first packaging assembly and the second packaging assembly.
(5) And then, etching the middle region of the flexible substrate, the first molding layer and the first semiconductor die from the back side of the flexible substrate to form a plurality of first through holes arranged at intervals in the first semiconductor die, wherein the depth of the first through holes in the middle region of the first semiconductor die is shallow, and the depth of the first through holes in the edge region of the first semiconductor die is deep.
(6) And then, etching the two opposite side edge regions of the flexible substrate, the second molding layer and the second semiconductor die from the back surface of the flexible substrate to form a plurality of second through holes arranged at intervals in the second semiconductor die, wherein the depth of the second through holes in the middle region of the second semiconductor die is shallow, and the depth of the second through holes in the edge region of the second semiconductor die is deep.
(7) A metal material is then deposited in the first and second vias to form first and second metal pillars, respectively.
(8) And arranging a second temporary bearing substrate on the bottom surface of the flexible substrate, removing the first temporary bearing substrate, arranging the third packaging assembly on the first packaging assembly, enabling the welding balls of the first packaging assembly to be in direct contact with the third conductive bumps of the third packaging assembly, and bending two opposite side edge areas of the flexible substrate upwards, so that each second packaging assembly is attached to the side wall of the first packaging assembly and the side wall of the third packaging assembly, and each second packaging assembly is electrically connected to the first packaging assembly and the third packaging assembly.
(9) Providing a circuit substrate, electrically connecting the third package assembly to the circuit substrate, and then removing the second temporary carrier substrate.
In some other embodiments, in the step (1), a first photoresist mask is formed on the first circuit substrate, the first photoresist mask having an opening reserved thereon, a conductive material is deposited in the opening and on an upper surface of the first photoresist mask to form a first conductive layer, the first conductive layer is patterned, and the first photoresist mask is removed to form a second conductive layer
The first conductive bump is patterned.
In some other embodiments, in the step (3), a second photoresist mask is formed on the third circuit substrate, a first opening is formed in the second photoresist mask, a conductive material is deposited in the first opening to form the third conductive bump, then a portion of the second photoresist mask is thinned to form a third photoresist mask, a second opening is formed in the third photoresist mask, then a second conductive layer is formed in the second opening and a portion of an upper surface of the third photoresist mask, then the second conductive layer is patterned, then the third photoresist mask is removed to form the third conductive bump
The second conductive bump is of a type.
In some other embodiments, in the step (4), the flexible substrate is one of a polyimide substrate, a polyethylene terephthalate substrate, a polyethersulfone substrate, a thermoplastic polyurethane substrate, a polycarbonate substrate, an epoxy resin substrate, and a phenol resin substrate, and the first temporary carrier substrate is one of a stainless steel substrate, a copper substrate, an iron substrate, and a ceramic substrate.
In some other embodiments, in the step (5), the plurality of spaced apart first through holes extend along a straight line, wherein a depth of the first through hole in the middle region of the first semiconductor die is 50-90 microns, and a depth of the first through hole in the edge region of the first semiconductor die is 100-180 microns.
In some other embodiments, in step (6), the plurality of spaced apart second perforations extend along a straight line, wherein the second perforations located in the middle region of the second semiconductor die have a depth of 30-60 microns and the second perforations located in the edge region of the second semiconductor die have a depth of 80-150 microns.
In some other embodiments, in the step (7), the metal material is one of copper, aluminum and silver, and the first metal pillar and the second metal pillar each have a portion protruding from the flexible substrate.
In some other embodiments, in the step (8), an adhesion preventing layer is coated on a peripheral region of the second temporary carrier substrate, and then a temporary adhesion layer is coated on a middle region of the second temporary carrier substrate, the flexible substrate corresponding to the first encapsulation assembly is adhered to the temporary adhesion layer, and the flexible substrate corresponding to the second encapsulation assembly is disposed on the adhesion preventing layer.
In some other embodiments, the invention also discloses a high stack package structure formed by the method.
As described above, the high stack package structure and the forming method thereof of the present invention have the following advantages: in the formation process of the high stack package structure of the present invention, the first conductive bump exposed from the side surface of the first plastic package layer is formed in the first package component, and the second conductive bump exposed from the side surface of the third plastic package layer and the third conductive bump exposed from the top surface of the third plastic package layer are formed in the third package component, so as to facilitate the electrical connection of the first, second and third package components. The first packaging assembly is arranged in the middle area of the flexible substrate, the two second packaging assemblies are arranged in the two opposite side areas of the flexible substrate respectively, the first through holes and the second through holes are formed through an etching treatment process respectively, the stability of the packaging structure can be improved on the one hand by optimizing the specific sizes of the first through holes and the second through holes, and on the other hand, the function of a semiconductor tube core is not influenced. Through deposit metal material in first perforation and second perforation in order to form first metal post and second metal post respectively, the joint steadiness between encapsulation subassembly and the flexible substrate can be strengthened to this first metal post and second metal post's existence, can effectively prevent high stacked package structure breakage.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. A method for forming a high stack package structure is characterized in that: the method comprises the following steps:
(1) providing a first circuit substrate, forming first conductive bumps on two side edge areas of the first circuit substrate, attaching a first semiconductor die on the first circuit substrate, then forming a first plastic package layer on the first circuit substrate, wherein the first plastic package layer wraps the first conductive bumps and the first semiconductor die, a part of the first conductive bumps are exposed from the side surface of the first plastic package layer, and then planting balls on the back surface of the first circuit substrate to form a first packaging assembly;
(2) providing a second circuit substrate, mounting a second semiconductor die on the second circuit substrate, forming a second plastic package layer on the second circuit substrate, wrapping the second semiconductor die by the first plastic package layer, and planting balls on the back surface of the second circuit substrate to form a second package assembly;
(3) providing a third circuit substrate, forming second conductive bumps on the edge areas of two sides of the third circuit substrate, forming a third conductive bump on the third circuit substrate, mounting a third semiconductor die on the third circuit substrate, then forming a third plastic package layer on the third circuit substrate, wherein the third plastic package layer wraps the second conductive bump, the third conductive bump and the third semiconductor die, a part of the second conductive bump is exposed from the side surface of the third plastic package layer, a part of the third conductive bump is exposed from the top surface of the third plastic package layer, and then planting balls on the back surface of the third circuit substrate to form a third package assembly;
(4) providing a flexible substrate, arranging the first packaging assembly in the middle area of the flexible substrate in a mode that the top surface of the first plastic packaging layer faces the flexible substrate, respectively arranging two second packaging assemblies in two opposite side areas of the flexible substrate in a mode that the top surface of the second plastic packaging layer faces the flexible substrate, and then arranging a first temporary bearing substrate on the first packaging assembly and the second packaging assembly;
(5) etching the middle region of the flexible substrate, the first molding compound layer and the first semiconductor die from the back side of the flexible substrate to form a plurality of first through holes arranged at intervals in the first semiconductor die, wherein the depth of the first through holes in the middle region of the first semiconductor die is shallow, and the depth of the first through holes in the edge region of the first semiconductor die is deep;
(6) etching the two opposite side edge regions of the flexible substrate, the second molding layer and the second semiconductor die from the back surface of the flexible substrate to form a plurality of second through holes arranged at intervals in the second semiconductor die, wherein the depth of the second through holes in the middle region of the second semiconductor die is shallow, and the depth of the second through holes in the edge region of the second semiconductor die is deep;
(7) then depositing a metal material in the first through hole and the second through hole to form a first metal pillar and a second metal pillar respectively;
(8) disposing a second temporary carrier substrate on the bottom surface of the flexible substrate, removing the first temporary carrier substrate, disposing the third package assembly on the first package assembly such that the solder balls of the first package assembly directly contact the third conductive bumps of the third package assembly, and bending the opposite side regions of the flexible substrate upward such that each of the second package assemblies is attached to the sidewalls of the first package assembly and the third package assembly and is electrically connected to the first and third package assemblies;
(9) providing a circuit substrate, electrically connecting the third package assembly to the circuit substrate, and then removing the second temporary carrier substrate.
2. The method of claim 1, wherein: in the step (1), a first photoresist mask is formed on the first circuit substrate, an opening is reserved in the first photoresist mask, a conductive material is deposited in the opening and on the upper surface of the first photoresist mask to form a first conductive layer, patterning is performed on the first conductive layer, and the first photoresist mask is removed to form a first conductive layer
The first conductive bump is patterned.
3. The method of claim 1, wherein: in the step (3), a second photoresist mask is formed on the third circuit substrate, a first opening is formed in the second photoresist mask, a conductive material is deposited in the first opening to form the third conductive bump, then a portion of the second photoresist mask is thinned to form a third photoresist mask, a second opening is formed in the third photoresist mask, then a second conductive layer is formed in the second opening and a portion of an upper surface of the third photoresist mask, then the second conductive layer is patterned, and then the third photoresist mask is removed to form the third conductive bump
The second conductive bump is of a type.
4. The method of claim 1, wherein: in the step (4), the flexible substrate is one of a polyimide substrate, a polyethylene terephthalate substrate, a polyphenylene ether sulfone substrate, a thermoplastic polyurethane substrate, a polycarbonate substrate, an epoxy resin substrate, and a phenol resin substrate, and the first temporary carrier substrate is one of a stainless steel substrate, a copper substrate, an iron substrate, and a ceramic substrate.
5. The method of claim 1, wherein: in the step (5), the plurality of spaced first through holes extend along a straight line, wherein the depth of the first through hole located in the middle region of the first semiconductor die is 50-90 microns, and the depth of the first through hole located in the edge region of the first semiconductor die is 100-180 microns.
6. The method of claim 1, wherein: in step (6), the plurality of spaced apart second through holes extend along a straight line, wherein the second through holes located in the middle region of the second semiconductor die have a depth of 30-60 microns and the second through holes located in the edge region of the second semiconductor die have a depth of 80-150 microns.
7. The method of claim 1, wherein: in the step (7), the metal material is one of copper, aluminum and silver, and the first metal pillar and the second metal pillar each have a portion protruding from the flexible substrate.
8. The method of claim 1, wherein: in the step (8), an adhesion preventing layer is coated on a peripheral region of the second temporary carrier substrate, and then a temporary adhesion layer is coated on a middle region of the second temporary carrier substrate, the flexible substrate corresponding to the first encapsulation member is adhered to the temporary adhesion layer, and the flexible substrate corresponding to the second encapsulation member is disposed on the adhesion preventing layer.
9. A high stack package structure formed by the method of any of claims 1-8.
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