US20070025150A9 - Flash memory device capable of preventing program disturbance according to partial programming - Google Patents
Flash memory device capable of preventing program disturbance according to partial programming Download PDFInfo
- Publication number
- US20070025150A9 US20070025150A9 US10/819,385 US81938504A US2007025150A9 US 20070025150 A9 US20070025150 A9 US 20070025150A9 US 81938504 A US81938504 A US 81938504A US 2007025150 A9 US2007025150 A9 US 2007025150A9
- Authority
- US
- United States
- Prior art keywords
- circuit
- word lines
- memory
- voltage
- driving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
Definitions
- the present invention generally relates to semiconductor memory devices and more specifically to flash memory devices.
- a NAND type flash memory device is one example of a nonvolatile semiconductor memory device capable of providing a high capacity and high integration density without a refresh of stored data. Data is preserved even at power-off.
- the flash memory device is widely employed in electronic devices having a possibility that a power supply is interrupted suddenly (e.g., a portable terminal, a portable computer, etc.)
- FIG. 1 is a block diagram illustrating a conventional NAND type flash memory device.
- the NAND type flash memory device 10 includes a memory cell array 20 , a row selection circuit (marked as “X-SEL” in the drawing) 40 , and a sense and latch circuit 60 (alternatively called a page buffer circuit).
- a memory cell array 20 includes a plurality of cell strings (or NAND strings) 21 each string connected to one of bit lines BL 0 -BLm.
- the string selection transistor SST in each column includes a drain connected to a corresponding bit line and a gate connected to a string selection line SSL.
- the ground selection transistor GST includes a source connected to a common source line CSL and a gate connected to a ground selection line GSL.
- Flash EEPROM cells MC 15 -MC 0 are connected in serial between the source of the string selection transistor SST and the drain of the ground selection transistor GST.
- the cells in each cell string include floating gate transistors and the control gates of the transistors are connected to corresponding word lines WL 15 -WL 0 , respectively.
- the string selection line SSL, the word lines WL 0 -WL 15 , and the ground selection line GSL are electrically connected to a row selection circuit 40 (X-SEL).
- the row selection circuit 40 selects one of the word lines according to row address information, and provides word line voltages to the selected word line and the non-selected word lines as determined by each operation mode.
- the row selection circuit 40 provides a program voltage (e.g., 15V-20V) to a selected word line in a program mode, and a pass voltage (e.g., 10V) to non-selected word lines.
- the row selection circuit 40 provides a ground voltage (GND) to a selected word line and a read voltage (e.g., 4.5V) to non-selected word lines in a read mode.
- GDD ground voltage
- the program voltage, the pass voltage and the read voltage are higher than a power supply voltage.
- the bit lines BL 0 -BLm disposed through the memory cell array 20 are electrically connected to the sense and latch circuit 60 .
- the sense and latch circuit 60 senses data from the flash EEPROM cells of the word line selected through the bit lines BL 0 -BLm in the read mode, and provides a power supply voltage (or a program-inhibited voltage) or a ground voltage (or a program voltage) to the bit lines BL 0 -BLm according to data to be programmed in a program mode.
- the cells not to be programmed may be soft-programmed by a program voltage due to characteristics of the cell structure as widely known. This is called a program disturbance.
- the program disturbance of the program-inhibited cell can be prevented by raising a channel voltage of the cell string to which the program-inhibited cell belongs, and this is called a self-boosting scheme.
- the channel voltage of the cell string follows a pass voltage provided to each of the non-selected word lines. As the pass voltage increases, soft-programming of the program-inhibited cell can be further suppressed. To the contrary, if the pass voltage increases, memory cells connected to each of the non-selected word lines may be soft-programmed by a pass voltage, and this is call “a pass disturbance”. Therefore, the pass voltage should be determined considering the above conditions.
- memory cells of one word line may be programmed at the same time.
- the memory cells in one word line are divided into some parts, and respective parts of the memory cells may be programmed individually. This is called “a partial program scheme”.
- the memory cells in an identical word line are less affected by the program disturbance, while the memory cells in an identical word line are much affected by the program disturbance in the latter case.
- the memory cells in the region with a loaded data and the memory cells in the region without loaded data are all connected to an identical word line, such that the program voltage is provided to the identical word line of the memory cells regardless of positions where the data loaded. Therefore, the possibility that the program-inhibited memory cell(s) is (are) soft-programmed increases as the number of the partial program (NOP) is rising.
- This method of partial programming is often used to manage data in a small unit compared to a page size when the page size is large. For example, when using a device having a 2112 (2K+64)-sized page, four-times partial programs should be ensured for a user to perform a program by a unit of 528 (512+16) bytes. 16 bytes of the 528 bytes are stored in the spare field memory region (referring to FIG. 2 ), and 512 bytes are stored in the main field memory region.
- the NAND type flash memory device becomes more susceptible to program disturbance.
- Embodiments of the present invention include a NAND type flash memory device capable of preventing program disturbance due to partial programming.
- a NAND type flash memory device includes arrays of memory cells disposed along rows and columns. The columns are divided into at least two column regions and each of the columns is divided into at least two electrically isolated word lines each arranged in the column regions.
- the NAND type flash memory device also includes a register for latching data being programmed in the array, a gate circuit for transmitting programmed data to the register in response to column address information, a determining device for judging which region the data loaded on the register operation belongs to according the column address information during a programming, and a selecting device for choosing one of the rows in response to row address information and for driving one or all of word lines in the selected row to a program voltage according to a result of judging.
- the selecting device drives all the word lines in the selected column to the program voltage.
- the selecting device drives one of the word lines in the selected row to a program voltage, and the word line driven with the program voltage corresponds to a column region of the loaded data.
- the selecting device includes a first selection circuit for driving one of the word lines in the selected row to the program voltage, wherein the word line driven with the program voltage belongs to one of the column regions and a second selecting circuit for driving one of the word lines in the selected row with the program voltage, wherein the word line driven with the program voltage belongs to the other region of the column regions.
- the determining device includes a detecting circuit for detecting a column region where the data loaded on the register in response to a column address to select the column regions and generate selection signals as a result of the detecting and a switching circuit for selectively transmitting the program voltage to the first and second selection circuits in response to the selection signals.
- a flash memory device includes an array divided into a first memory block and a second memory block, a first row decoder circuit for selecting one of word lines in the first memory block and driving the selected word line with a program voltage and the non-selected word lines with a pass voltage, a second row decoder circuit for selecting one of the word line in the second memory block and driving the selected word line with the program voltage and the non-selected word lines with the pass voltage, a page buffer circuit for latching data to be programmed to the array, a gate circuit for transmitting the data to be programmed to the page buffer circuit in response to a column address, a determining circuit for judging to which memory block the data loaded on the page buffer circuit is programmed in response to the column address for selecting the first and second memory blocks and generating selection signals as a result of judging, a driving signal generator circuit for outputting driving signals to be provided to word lines each corresponding to the first and second memory blocks, and a switching circuit for switching the driving signals with all or one of the first and second de
- the first and second memory blocks each include a plurality of NAND strings, and each of the NAND strings includes memory cells connected to corresponding word lines respectively.
- one of the driving signals has the program voltage and the rest of the driving signals have the pass voltage during a program operation.
- the determining circuit includes first and second flip-flops, a first set circuit, a first high voltage switch, a second set circuit and a second high voltage switch.
- the first and second flip-flops each reset by a reset signal.
- the first set circuit sets the first flip-flop in response to an address signal for identifying the first memory block during the program operation.
- the first high voltage switch receives an output signal of the first flip-flop to generate a first selection signal. In this case, the first selection signal has a high voltage during activation.
- the second set circuit sets the second flip-flop in response to an address signal for indicating the second memory block during the program operation.
- the second high voltage switch receives an output signal of the second flip-flop to generate a second selection signal. In this case, the second selection signal has a high voltage during activation.
- the reset signal is activated when an input command of a sequential data is introduced.
- the switching circuit operates in response to the first and second selection signals and includes switches each corresponding to the driving signals.
- Each of the switches includes a first depletion MOS transistor for transmitting a corresponding driving signal to the first row decoder circuit in response to the first selection signal, and a second depletion MOS transistor for transmitting a corresponding driving signal to the second row decoder circuit in response to the second selection signal.
- the array further includes a spare array.
- the spare array is divided into spare memory blocks each corresponding to the first and second memory blocks, and each the spare memory blocks is disposed with corresponding memory blocks.
- the memory block and the spare memory block disposed in the same region are controlled by an identical row decoder circuit.
- FIG. 1 is a block diagram illustrating a conventional NAND type flash memory device.
- FIG. 2 illustrates a conventional method of partial programming.
- FIG. 3 is a block diagram illustrating a NAND type flash memory device according to one embodiment of the present invention.
- FIG. 4 is a block diagram illustrating a NAND type flash memory device according to another embodiment of the present invention.
- FIG. 5 is a circuit diagram illustrating a block decoder and a word line switch block of FIG. 3 according to one embodiment of the present invention.
- FIG. 6 is a circuit diagram illustrating a determining circuit of FIG. 3 according to one embodiment of the present invention.
- FIG. 7 is a circuit diagram illustrating a switching circuit of FIG. 3 according to one embodiment of the present invention.
- FIG. 8 is a timing diagram illustrating a partial program operation of the NAND type flash memory device according to the present invention.
- FIG. 3 is a block diagram illustrating a NAND type flash memory device according to one embodiment of the present invention.
- the NAND type flash memory device 100 includes arrays of memory cells arranged along rows and columns. According to the present invention, columns in the array are divided into two column regions and each row is divided into electrically isolated word lines that are disposed in the column regions, respectively.
- one column region is referred to as a first memory block 110 R composing a first mat (or a first memory cell array), and another column region is a second memory block 110 L composing a second mat (or a second memory cell array).
- the first and second memory blocks 110 R and 110 L each include a plurality of cell strings, and each of the cell strings is organized in the same way as illustrated in FIG. 1 .
- a row selection circuit is disposed between the first and second memory blocks 110 R and 110 L, and the row selection circuit comprises first and second word line switch blocks 120 R and 120 L and a block decoder 130 .
- the row selection circuit may be shared by the memory blocks 110 R and 110 L.
- the row selection circuit may comprise two row decoder circuits 120 R, 130 R and 120 L, 130 L each corresponding to the first and second memory blocks 110 R and 110 L.
- Each of the decoder circuits may include a block decoder 130 R/ 130 L and a word line switch block 120 R/ 120 L.
- spare field memory region may be further included in each of the memory blocks 110 R and 110 L in addition to a main field memory region (with reference to FIG. 2 ).
- a string selection line SSL, word lines WL 15 -WL 0 and a ground selection line GSL, which are disposed in a row direction of the second memory block 110 L are electrically connected to a second word line switch block 120 L.
- the block decoder 130 activates or inactivates the block word line BLKWL according to row address information for indicating a memory block.
- the driving signal generator circuit 140 outputs the driving signals SS, S 0 -S 15 and GS in response to the row address information for selecting one of the word lines disposed in each memory block.
- the selection signals SS and GS each have a power supply voltage VCC
- one of the driving signals S 0 -S 15 has the ground voltage
- the remaining driving signals have a reading voltage.
- the selection signal SS has the power supply voltage
- the selection signal GS has the ground voltage.
- one of the driving signals S 0 -S 15 has a program voltage
- the rest have a pass voltage.
- bit lines BL 0 -BLm arranged along each column direction of the first and second memory blocks 110 R and 110 L are electrically connected to the corresponding sense and latch circuits 170 R and 170 L.
- Each of the sense and latch circuits 170 R and 170 L senses data from the flash EEPROM cells of the word line selected through bit lines BL 0 -BLm in a read operation mode.
- Each of the sense and latch circuits 170 R and 170 L latches the data to be programmed that is transferred through the gate circuit 190 R or 190 L in a program operation mode, and provides the power supply voltage or the ground voltage to the bit lines BL 0 -BLm according to the latched data.
- the switching circuit 160 receives the driving signals S 0 -S 15 from the driving signal generator circuit 140 , and outputs first driving signals S 0 R-S 15 R and/or second driving signals S 0 L-S 15 L in response to selection signals VM 1 and VM 2 from the determining circuit 150 . Output signals of the switching circuit 160 have the same voltages as the voltages of the input signals.
- the determining circuit 150 outputs the selection signals VM 1 and VM 2 in response to the column address information for indicating a memory block. In this case, the selection signals VM 1 and VM 2 are activated exclusively or simultaneously. For instance, the selection signals VM 1 and VM 2 are simultaneously activated during a read/erase operation and simultaneously or exclusively activated during a program operation. This operation will be more fully explained herein.
- FIG. 5 illustrates embodiments of the block decoder and the word line switch block shown in FIG. 3 .
- the first word line switch block 120 R includes pass transistors SW 27 -SW 20 each corresponding to the driving signals SS, S 15 R-S 0 R and GS. Gates of the pass transistors SW 27 -Sw 20 are connected to a block word line BLKWL in common.
- the driving signals SS, S 15 R-S 0 R and GS are transferred to a string selection line SSL, word lines WL 15 -WL 0 and a ground selection line GSL through pass transistors SW 27 -SW 20 , respectively.
- one of the driving signals S 15 R-S 0 R has a ground voltage and the rest have a read voltage.
- one of the driving signals S 15 R-S 0 R has a program voltage and the rest have a pass voltage.
- the pass transistors SW 20 -SW 27 in the first word line switch block 120 R each comprises a high voltage NMOS transistor.
- a second word line switch block 120 L is comprised of pass transistors SW 27 -SW 20 each corresponding to the driving signals SS, S 15 L-S 0 L and GS. Gates of the pass transistors SW 27 -SW 20 are connected to a block word line BLKWL in common.
- the driving signals SS, S 15 L-S 0 L and GS are transferred to the string selection line SSL, the word lines WL 15 -WL 0 and the ground selection line GSL through the pass transistors SW 27 -SW 20 , respectively.
- one of the driving signals S 15 L-S 0 L has a ground voltage and the rest have a read voltage.
- one of the driving signals S 15 L-S 0 L has a program voltage and the rest have a pass voltage.
- the pass transistors SW 20 -SW 27 in the second word line switch block 120 L each comprises a high voltage NMOS transistor.
- the block decoder 130 includes NAND gates G 1 , G 2 and G 3 and NMOS transistors M 1 , M 2 , M 3 and M 4 , connected as illustrated in the drawing.
- the NMOS transistors M 2 and M 4 are controlled by an output signal of the NAND gate G 3
- the NMOS transistors M 1 and M 3 are controlled by control signals ERSen and VPRE, respectively.
- the control signal ERSen has a low level during a program/read operation and a high level during an erase operation.
- the NMOS transistor M 2 is used for discharging a block word line BLKWL, and turned on when a control signal BLKWL is in a low level.
- the output of NMOS transistor M 4 is shared by memory blocks 110 R and 110 L, and is connected between string selection lines SSL of the memory blocks and an SSLGND node.
- the SSLGND node has a ground voltage during a program/read operation, and a power supply voltage during an erase operation.
- the control signals XDECdis and BLKWLdis are maintained at a high level for an interval while the data is programmed in a memory cell.
- FIG. 6 is a circuit diagram illustrating the determining circuit 150 of FIG. 3 according to an embodiment of the present invention.
- the determining circuit 150 of the present invention includes inverters INV 1 and INV 2 , AND gates G 4 and G 5 , NOR gates G 6 and G 7 , S-R flip-flops FF 1 and FF 2 and high voltage switches 151 and 152 , each connected as illustrated in the drawing.
- the high voltage switches 151 and 152 each comprise a switch pump circuit, such as the switch pump circuit disclosed in the U.S. Pat. No. 5,861,772 entitled “CHARGE PUMP CIRCUIT OF NONVOLATILE SEMICONDUCTOR MEMORY”.
- each of the high voltage switches 151 and 152 converts a voltage level of input signal to a high voltage (e.g., a program voltage).
- the determining circuit 150 receives a program flag signal nPGM, an address signal CAi, a reset signal RST and a clock signal CLK.
- the determining circuit 150 judges which sense and latch block 170 L or 170 R the data to be programmed is loaded on, and activates selection signals VM 1 and VM 2 simultaneously or exclusively according to the judging.
- the program flag signals nPGM is activated to a low level during a program operation and inactivated to a high level during an erase/read operation.
- the address signal CAi is for selecting memory blocks 110 R and 110 L. For example, when the address signal CAi is “0”, the memory block 110 R is selected. When the address signal CAi is “1”, the memory block 110 L is selected.
- a clock signal CLK is used for loading data to be programmed, and a reset signal RST is a pulse signal that is activated when a sequential data input command is introduced.
- the reset signal RST is activated as an input command of a sequential data is introduced.
- a program flag signal nPGM is maintained at a low level.
- the outputs of the flip-flops FF 1 and FF 2 get a low level as the reset signal RST is activated. That is, the selection signals VM 1 and VM 2 are initialized as a low level, respectively.
- the data to be programmed are sequentially loaded on the sense and latch block(s) as the column address is incremented.
- an output signal S of the NOR gate G 6 transitions from a high level to a low level in synchronization with a low-high transition of the clock signal CLK. That is, the output of the flip-flop FF 1 is activated from a low level to a high level. In this case, the output of the flip-flop FF 2 is maintained at a low level, continuously.
- the address signal CAi is maintained as “0” continuously until all of the data is loaded, the data to be programmed is loaded only on the sense and latch block 170 R. In this case, only the selection signal VM 1 is activated to high.
- the output signal S of the NOR gate G 7 transitions from a high level to a low level in synchronization with a low-high transition of the clock signal CLK. That is, outputs of the flip-flop FF 2 are activated from a low level to a high level.
- the selection signals VM 1 and VM 2 are all activated to high.
- the activated selection signals VM 1 and VM 2 have high voltage through corresponding high voltage switches 151 and 152 .
- the determining circuit 150 activates a selection signal VM 1 when the data to be programmed is loaded only on the sense and latch block 170 R of the memory block 110 R.
- the determining circuit 150 activates a selection signal VM 2 when the data to be programmed is loaded only on the sense and latch block 170 L of the memory block 110 L.
- the determining circuit 150 activates the selection signals VM 1 and VM 2 when the data to be programmed is loaded on all of the sense and latch blocks 170 R and 170 L of the memory blocks 110 R and 110 L.
- FIG. 7 is a circuit diagram showing a switching circuit 160 of FIG. 3 according to an embodiment of the present invention.
- the switching circuit 160 receives driving signals S 0 -S 15 outputted from the driving signal generator circuit 140 , and generates first driving signals S 0 R-S 15 R or second driving signals S 0 L-S 15 L in response to selection signals VM 1 and VM 2 from the determining circuit 150 .
- the switching circuit 160 comprises depletion type MOS pass transistors 161 , 162 , 163 , . . . and 166 .
- the depletion type MOS transistors 162 , 164 , . . . and 166 correspond to the driving signals S 0 -S 15 , respectively, and the transistors are controlled by the selection signal VM 2 in common.
- the determining circuit 150 activates a selection signal VM 1 , and the output signals S 0 -S 15 of the driving signal generator circuit 140 generated as selection signals S 0 R-S 15 R are applied to the switch block 120 R.
- the determining circuit 150 activates the selection signal VM 2 , and output signals S 0 -S 15 of the driving signal generator circuit 140 generated as driving signals S 0 L-S 15 L are applied to the switch block 120 L.
- the determining circuit 150 activates the selection signals VM 1 and VM 2 simultaneously, and the output signals S 0 -S 15 of the driving signal generator circuit 140 are outputted as first and second driving signals S 0 R-S 15 R and S 0 L-S 15 L that are applied to first and second switch blocks 120 R and 120 L.
- FIG. 8 is a timing diagram for illustrating a program operation of a NAND type flash memory device.
- the program operation of the memory device according to the present invention will be fully explained herein with reference to the drawings.
- the signals shown in the first six lines of FIG. 8 are also identified in the circuit of FIG. 6 .
- a sequential data input command is introduced and an initial column address and a row (or a page) address are sequentially inputted.
- the initial column address is loaded on an internal address counter (not shown), and the internal address counter increases internal column addresses by one bit whenever data is inputted by a predetermined unit (a byte or a word unit).
- the data to be programmed is loaded on the sense and latch block(s) 170 L or 170 R as a page buffer circuit through a gate circuit as the column addresses increase.
- a program command for starting a program is inputted.
- the NAND type flash memory device 100 performs program operation according an internal algorithm known in the art after the program command is inputted, and notifies that the memory device is in a busy state to outside through a R/nB pin during the program operation.
- the reset signal RST is activated to a pulse type.
- flip-flops FF 1 and FF 2 of the determining circuits 150 are initialized.
- the output signals VM 1 and VM 2 of the determining circuit 150 are set to a low level.
- a starting (or initial) column address CAi where the data is going to be loaded is inputted, and the initial address counter (not shown) is set to an initial column address.
- a column address for selecting memory blocks of the initial column addresses e.g., an uppermost address signal
- the data to be programmed will be loaded on the sense and latch block 170 R of the memory block 110 R.
- the data to be programmed is loaded on the sense and latch block 170 R through a column gate circuit 190 R in synchronization with a clock signal CLK. Since the column address for selecting memory blocks is “0”, an output signal of the NOR gate G 6 in the determining circuit 150 transitions from a high level to a low level during a low-high transition of the clock signal. This makes the selection signal VM 1 transition from a low level to a high level. In this case, the activated selection signal VM 1 has a high voltage through a high voltage switch 151 .
- the selection signal VM 1 will be activated. This transmits the driving signals S 0 -S 15 inputted in the switching circuit 160 only to a word line switch block 120 R.
- a program voltage and a pass voltage will be applied to the word lines of the memory block 110 R.
- the selection signal VM 2 is not activated, a program voltage and a pass voltage are not applied to word lines of the memory block 110 L. That is, in case of a partial program, the program voltage and the pass voltage are applied only to the word lines of a memory block corresponding to the sense and latch block with a loaded data to be programmed. Therefore, a program disturbance can be prevented (or relieved) according to a partial program scheme because the program voltage and the pass voltage are not applied to the word lines in the memory block corresponding to the sense and latch block without the loaded data to be programmed.
- the data to be programmed is loaded on the sense and latch block 170 L of the memory block 110 L through a gate circuit 190 L.
- the output signal of the NOR gate G 7 in the determining circuit 150 transitions from a high level to a low level in synchronization with a clock signal CLK. This activates the selection signal VM 2 to high. This activation transmits the driving signal S 0 -S 15 inputted in the switching circuit 160 to a word line switch block 120 L.
- the memory blocks of the present invention can include a corresponding spare field memory region.
- the spare field memory region will also be divided into two regions.
- the divided spare field memory regions each correspond to the corresponding memory blocks.
- the memory cell array may be organized as illustrated in FIG. 2 . That is, the memory block 110 R includes one of the divided spare field memory regions and the memory block 110 L includes the other spare field memory region.
- the word lines of the memory block and the corresponding spare field memory region are controlled by the identical row selection circuit.
- a program voltage and a pass voltage are not applied to word lines of a memory block corresponding to a sense and latch block without a loaded data to be programmed, such that a program voltage disturbance cannot be prevented (or relieved) according to a partial program scheme.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
Abstract
Description
- This application claims priority under 35 USC § 119 to Korean Patent Application No. 2003-24812, filed on Apr. 18, 2003, the contents of which are herein incorporated by reference in their entirety.
- The present invention generally relates to semiconductor memory devices and more specifically to flash memory devices.
- There is an increasing need for a semiconductor memory device capable of electrically erasing and programming without a refresh of a stored data. In addition, there is continual pressure to increase storage capacity and integration density of the memory device. A NAND type flash memory device is one example of a nonvolatile semiconductor memory device capable of providing a high capacity and high integration density without a refresh of stored data. Data is preserved even at power-off. The flash memory device is widely employed in electronic devices having a possibility that a power supply is interrupted suddenly (e.g., a portable terminal, a portable computer, etc.)
-
FIG. 1 is a block diagram illustrating a conventional NAND type flash memory device. Referring toFIG. 1 , the NAND type flash memory device 10 includes amemory cell array 20, a row selection circuit (marked as “X-SEL” in the drawing) 40, and a sense and latch circuit 60 (alternatively called a page buffer circuit). Amemory cell array 20 includes a plurality of cell strings (or NAND strings) 21 each string connected to one of bit lines BL0-BLm. Thecell string 21 in each column comprises a string selection transistor SST as a first selection transistor, a ground selection transistor GST as a second selection transistor, and a plurality of flash EEPROM cells MCn (n=0-15) connected in serial between the selection transistors SST and GST. The string selection transistor SST in each column includes a drain connected to a corresponding bit line and a gate connected to a string selection line SSL. The ground selection transistor GST includes a source connected to a common source line CSL and a gate connected to a ground selection line GSL. Flash EEPROM cells MC15-MC0 are connected in serial between the source of the string selection transistor SST and the drain of the ground selection transistor GST. The cells in each cell string include floating gate transistors and the control gates of the transistors are connected to corresponding word lines WL15-WL0, respectively. - The string selection line SSL, the word lines WL0-WL15, and the ground selection line GSL are electrically connected to a row selection circuit 40 (X-SEL). The
row selection circuit 40 selects one of the word lines according to row address information, and provides word line voltages to the selected word line and the non-selected word lines as determined by each operation mode. For example, therow selection circuit 40 provides a program voltage (e.g., 15V-20V) to a selected word line in a program mode, and a pass voltage (e.g., 10V) to non-selected word lines. Therow selection circuit 40 provides a ground voltage (GND) to a selected word line and a read voltage (e.g., 4.5V) to non-selected word lines in a read mode. The program voltage, the pass voltage and the read voltage are higher than a power supply voltage. The bit lines BL0-BLm disposed through thememory cell array 20 are electrically connected to the sense andlatch circuit 60. The sense andlatch circuit 60 senses data from the flash EEPROM cells of the word line selected through the bit lines BL0-BLm in the read mode, and provides a power supply voltage (or a program-inhibited voltage) or a ground voltage (or a program voltage) to the bit lines BL0-BLm according to data to be programmed in a program mode. - In a NAND type flash memory device, the cells not to be programmed (referred to as a program-inhibited cell, hereinafter) may be soft-programmed by a program voltage due to characteristics of the cell structure as widely known. This is called a program disturbance. The program disturbance of the program-inhibited cell can be prevented by raising a channel voltage of the cell string to which the program-inhibited cell belongs, and this is called a self-boosting scheme. The channel voltage of the cell string follows a pass voltage provided to each of the non-selected word lines. As the pass voltage increases, soft-programming of the program-inhibited cell can be further suppressed. To the contrary, if the pass voltage increases, memory cells connected to each of the non-selected word lines may be soft-programmed by a pass voltage, and this is call “a pass disturbance”. Therefore, the pass voltage should be determined considering the above conditions.
- Methods of restricting programming using the self-boosting scheme fully explained above are disclosed in U.S. Pat. No. 5,677,873 entitled “METHOD OF PROGRAMMING FLASH EEPROM INTEGRATED CIRCUIT MEMORY DEVICES TO PREVENT INADVERTENT PROGRAMMING OF NONDESIGNATED NAND MEMORY CELLS THEREIN”, and in U.S. Pat. No. 5,991,202 entitled “METHOD FOR REDUCING PROGRAM DISTURBANCE DURING SELF-BOOSTING IN A NAND FLASH MMEORY”, and incorporated herein by reference.
- In case of the NAND type flash memory device, memory cells of one word line may be programmed at the same time. Alternatively, the memory cells in one word line are divided into some parts, and respective parts of the memory cells may be programmed individually. This is called “a partial program scheme”. In the former case, the memory cells in an identical word line are less affected by the program disturbance, while the memory cells in an identical word line are much affected by the program disturbance in the latter case. Assume that, for example, only the data to be programmed in the memory region of the bit lines BL0-Bli (a part marked with diagonal hash marks in
FIG. 2 ) is loaded on the sense andlatch circuit 60, as illustrated inFIG. 2 . The memory cells in the region with a loaded data and the memory cells in the region without loaded data (in which bit lines BLi+1-BLm are arranged) are all connected to an identical word line, such that the program voltage is provided to the identical word line of the memory cells regardless of positions where the data loaded. Therefore, the possibility that the program-inhibited memory cell(s) is (are) soft-programmed increases as the number of the partial program (NOP) is rising. - This method of partial programming is often used to manage data in a small unit compared to a page size when the page size is large. For example, when using a device having a 2112 (2K+64)-sized page, four-times partial programs should be ensured for a user to perform a program by a unit of 528 (512+16) bytes. 16 bytes of the 528 bytes are stored in the spare field memory region (referring to
FIG. 2 ), and 512 bytes are stored in the main field memory region. - Accordingly, if the number of times of partial program increases, the NAND type flash memory device becomes more susceptible to program disturbance.
- Embodiments of the present invention include a NAND type flash memory device capable of preventing program disturbance due to partial programming.
- In some embodiments of the present invention, a NAND type flash memory device includes arrays of memory cells disposed along rows and columns. The columns are divided into at least two column regions and each of the columns is divided into at least two electrically isolated word lines each arranged in the column regions. The NAND type flash memory device also includes a register for latching data being programmed in the array, a gate circuit for transmitting programmed data to the register in response to column address information, a determining device for judging which region the data loaded on the register operation belongs to according the column address information during a programming, and a selecting device for choosing one of the rows in response to row address information and for driving one or all of word lines in the selected row to a program voltage according to a result of judging.
- In this embodiment, when all of the data loaded on the register belongs to the column regions, the selecting device drives all the word lines in the selected column to the program voltage. Alternatively, when the data loaded on the register belongs to any one of the column regions, the selecting device drives one of the word lines in the selected row to a program voltage, and the word line driven with the program voltage corresponds to a column region of the loaded data.
- In some embodiments, the selecting device includes a first selection circuit for driving one of the word lines in the selected row to the program voltage, wherein the word line driven with the program voltage belongs to one of the column regions and a second selecting circuit for driving one of the word lines in the selected row with the program voltage, wherein the word line driven with the program voltage belongs to the other region of the column regions. The determining device includes a detecting circuit for detecting a column region where the data loaded on the register in response to a column address to select the column regions and generate selection signals as a result of the detecting and a switching circuit for selectively transmitting the program voltage to the first and second selection circuits in response to the selection signals.
- In other embodiments, a flash memory device includes an array divided into a first memory block and a second memory block, a first row decoder circuit for selecting one of word lines in the first memory block and driving the selected word line with a program voltage and the non-selected word lines with a pass voltage, a second row decoder circuit for selecting one of the word line in the second memory block and driving the selected word line with the program voltage and the non-selected word lines with the pass voltage, a page buffer circuit for latching data to be programmed to the array, a gate circuit for transmitting the data to be programmed to the page buffer circuit in response to a column address, a determining circuit for judging to which memory block the data loaded on the page buffer circuit is programmed in response to the column address for selecting the first and second memory blocks and generating selection signals as a result of judging, a driving signal generator circuit for outputting driving signals to be provided to word lines each corresponding to the first and second memory blocks, and a switching circuit for switching the driving signals with all or one of the first and second decoder circuits in response to the selection signals from the determining circuit. In this case, the first and second memory blocks each include a plurality of NAND strings, and each of the NAND strings includes memory cells connected to corresponding word lines respectively. In addition, one of the driving signals has the program voltage and the rest of the driving signals have the pass voltage during a program operation.
- In some embodiments, the determining circuit includes first and second flip-flops, a first set circuit, a first high voltage switch, a second set circuit and a second high voltage switch. The first and second flip-flops each reset by a reset signal. The first set circuit sets the first flip-flop in response to an address signal for identifying the first memory block during the program operation. The first high voltage switch receives an output signal of the first flip-flop to generate a first selection signal. In this case, the first selection signal has a high voltage during activation. The second set circuit sets the second flip-flop in response to an address signal for indicating the second memory block during the program operation. The second high voltage switch receives an output signal of the second flip-flop to generate a second selection signal. In this case, the second selection signal has a high voltage during activation.
- The reset signal is activated when an input command of a sequential data is introduced. The switching circuit operates in response to the first and second selection signals and includes switches each corresponding to the driving signals. Each of the switches includes a first depletion MOS transistor for transmitting a corresponding driving signal to the first row decoder circuit in response to the first selection signal, and a second depletion MOS transistor for transmitting a corresponding driving signal to the second row decoder circuit in response to the second selection signal.
- In further embodiments of the present invention, the array further includes a spare array. The spare array is divided into spare memory blocks each corresponding to the first and second memory blocks, and each the spare memory blocks is disposed with corresponding memory blocks. The memory block and the spare memory block disposed in the same region are controlled by an identical row decoder circuit.
-
FIG. 1 is a block diagram illustrating a conventional NAND type flash memory device. -
FIG. 2 illustrates a conventional method of partial programming. -
FIG. 3 is a block diagram illustrating a NAND type flash memory device according to one embodiment of the present invention. -
FIG. 4 is a block diagram illustrating a NAND type flash memory device according to another embodiment of the present invention. -
FIG. 5 is a circuit diagram illustrating a block decoder and a word line switch block ofFIG. 3 according to one embodiment of the present invention. -
FIG. 6 is a circuit diagram illustrating a determining circuit ofFIG. 3 according to one embodiment of the present invention. -
FIG. 7 is a circuit diagram illustrating a switching circuit ofFIG. 3 according to one embodiment of the present invention. -
FIG. 8 is a timing diagram illustrating a partial program operation of the NAND type flash memory device according to the present invention. - The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown.
-
FIG. 3 is a block diagram illustrating a NAND type flash memory device according to one embodiment of the present invention. Referring toFIG. 3 , the NAND typeflash memory device 100 includes arrays of memory cells arranged along rows and columns. According to the present invention, columns in the array are divided into two column regions and each row is divided into electrically isolated word lines that are disposed in the column regions, respectively. For brevity, one column region is referred to as afirst memory block 110R composing a first mat (or a first memory cell array), and another column region is asecond memory block 110L composing a second mat (or a second memory cell array). The first and second memory blocks 110R and 110L each include a plurality of cell strings, and each of the cell strings is organized in the same way as illustrated inFIG. 1 . A row selection circuit is disposed between the first and second memory blocks 110R and 110L, and the row selection circuit comprises first and second word line switch blocks 120R and 120L and ablock decoder 130. The row selection circuit may be shared by the memory blocks 110R and 110L. - Alternatively, as illustrated in
FIG. 4 , the row selection circuit may comprise tworow decoder circuits block decoder 130R/130L and a wordline switch block 120R/120L. Although not illustrated in the drawings, it is clear that spare field memory region may be further included in each of the memory blocks 110R and 110L in addition to a main field memory region (with reference toFIG. 2 ). - Referring to
FIG. 3 again, a string selection line SSL, word lines WL15-WL0 and the ground selection line GSL, which are disposed in a row direction of thefirst memory block 110R, are electrically connected to the first wordline switch block 120R. According to signals on a block word line BLKWL, the first wordline switch block 120R transmits the driving signals SiR (i=0-15) from aswitching circuit 160 and driving signals SS and GS from a drivingsignal generator circuit 140 to corresponding signal lines SSL, WL0-WL15 and GSL, respectively. A string selection line SSL, word lines WL15-WL0 and a ground selection line GSL, which are disposed in a row direction of thesecond memory block 110L are electrically connected to a second wordline switch block 120L. According to signals on the block word line BLKWL, the second wordline switch block 120L transmits driving signals SiL (i=0-15) from the switchingcircuit 160 and the driving signals SS and GS from the drivingsignal generator circuit 140 to the corresponding signal lines SSL, WL0-WL15 and GSL, respectively. Theblock decoder 130 activates or inactivates the block word line BLKWL according to row address information for indicating a memory block. - The driving
signal generator circuit 140 outputs the driving signals SS, S0-S15 and GS in response to the row address information for selecting one of the word lines disposed in each memory block. During a read operation, the selection signals SS and GS each have a power supply voltage VCC, one of the driving signals S0-S15 has the ground voltage, and the remaining driving signals have a reading voltage. During a program operation, the selection signal SS has the power supply voltage, and the selection signal GS has the ground voltage. In this case, one of the driving signals S0-S15 has a program voltage, and the rest have a pass voltage. The drivingsignal generator circuit 140 is provided with a program voltage, a pass voltage and a read voltage from a highvoltage generator circuit 180 as determined by the different operation modes to apply a high voltage to each of the driving signal Si (i=1-15) lines. - Referring to the embodiments of both
FIG. 3 andFIG. 4 , bit lines BL0-BLm arranged along each column direction of the first and second memory blocks 110R and 110L are electrically connected to the corresponding sense and latchcircuits circuits circuits gate circuit switching circuit 160 receives the driving signals S0-S15 from the drivingsignal generator circuit 140, and outputs first driving signals S0R-S15R and/or second driving signals S0L-S15L in response to selection signals VM1 and VM2 from the determiningcircuit 150. Output signals of theswitching circuit 160 have the same voltages as the voltages of the input signals. The determiningcircuit 150 outputs the selection signals VM1 and VM2 in response to the column address information for indicating a memory block. In this case, the selection signals VM1 and VM2 are activated exclusively or simultaneously. For instance, the selection signals VM1 and VM2 are simultaneously activated during a read/erase operation and simultaneously or exclusively activated during a program operation. This operation will be more fully explained herein. -
FIG. 5 illustrates embodiments of the block decoder and the word line switch block shown inFIG. 3 . The first wordline switch block 120R includes pass transistors SW27-SW20 each corresponding to the driving signals SS, S15R-S0R and GS. Gates of the pass transistors SW27-Sw20 are connected to a block word line BLKWL in common. The driving signals SS, S15R-S0R and GS are transferred to a string selection line SSL, word lines WL15-WL0 and a ground selection line GSL through pass transistors SW27-SW20, respectively. When a read operation is performed, one of the driving signals S15R-S0R has a ground voltage and the rest have a read voltage. When a program operation is performed, one of the driving signals S15R-S0R has a program voltage and the rest have a pass voltage. The pass transistors SW20-SW27 in the first wordline switch block 120R each comprises a high voltage NMOS transistor. - A second word
line switch block 120L is comprised of pass transistors SW27-SW20 each corresponding to the driving signals SS, S15L-S0L and GS. Gates of the pass transistors SW27-SW20 are connected to a block word line BLKWL in common. The driving signals SS, S15L-S0L and GS are transferred to the string selection line SSL, the word lines WL15-WL0 and the ground selection line GSL through the pass transistors SW27-SW20, respectively. When a read operation is performed, one of the driving signals S15L-S0L has a ground voltage and the rest have a read voltage. When a program operation is performed, one of the driving signals S15L-S0L has a program voltage and the rest have a pass voltage. The pass transistors SW20-SW27 in the second wordline switch block 120L each comprises a high voltage NMOS transistor. - Still referring to
FIG. 5 , theblock decoder 130 includes NAND gates G1, G2 and G3 and NMOS transistors M1, M2, M3 and M4, connected as illustrated in the drawing. The NMOS transistors M2 and M4 are controlled by an output signal of the NAND gate G3, and the NMOS transistors M1 and M3 are controlled by control signals ERSen and VPRE, respectively. The control signal ERSen has a low level during a program/read operation and a high level during an erase operation. The NMOS transistor M2 is used for discharging a block word line BLKWL, and turned on when a control signal BLKWL is in a low level. The output of NMOS transistor M4 is shared bymemory blocks -
FIG. 6 is a circuit diagram illustrating the determiningcircuit 150 ofFIG. 3 according to an embodiment of the present invention. Referring toFIG. 6 , the determiningcircuit 150 of the present invention includes inverters INV1 and INV2, AND gates G4 and G5, NOR gates G6 and G7, S-R flip-flops FF1 and FF2 andhigh voltage switches high voltage switches high voltage switches - The determining
circuit 150 receives a program flag signal nPGM, an address signal CAi, a reset signal RST and a clock signal CLK. The determiningcircuit 150 judges which sense and latch block 170L or 170R the data to be programmed is loaded on, and activates selection signals VM1 and VM2 simultaneously or exclusively according to the judging. InFIG. 5 , the program flag signals nPGM is activated to a low level during a program operation and inactivated to a high level during an erase/read operation. The address signal CAi is for selectingmemory blocks memory block 110R is selected. When the address signal CAi is “1”, thememory block 110L is selected. A clock signal CLK is used for loading data to be programmed, and a reset signal RST is a pulse signal that is activated when a sequential data input command is introduced. - In a circuit operation, the reset signal RST is activated as an input command of a sequential data is introduced. In this case, a program flag signal nPGM is maintained at a low level. The outputs of the flip-flops FF1 and FF2 get a low level as the reset signal RST is activated. That is, the selection signals VM1 and VM2 are initialized as a low level, respectively. Afterwords, the data to be programmed are sequentially loaded on the sense and latch block(s) as the column address is incremented. In case that the column address signal CAi is maintained as “0” for a data loading interval, an output signal S of the NOR gate G6 transitions from a high level to a low level in synchronization with a low-high transition of the clock signal CLK. That is, the output of the flip-flop FF1 is activated from a low level to a high level. In this case, the output of the flip-flop FF2 is maintained at a low level, continuously. When the address signal CAi is maintained as “0” continuously until all of the data is loaded, the data to be programmed is loaded only on the sense and latch block 170R. In this case, only the selection signal VM1 is activated to high. If the address signal CAi changes to “1” while the data is being loaded, the output signal S of the NOR gate G7 transitions from a high level to a low level in synchronization with a low-high transition of the clock signal CLK. That is, outputs of the flip-flop FF2 are activated from a low level to a high level. In this case, the selection signals VM1 and VM2 are all activated to high. The activated selection signals VM1 and VM2 have high voltage through corresponding
high voltage switches - The determining
circuit 150 activates a selection signal VM1 when the data to be programmed is loaded only on the sense and latch block 170R of thememory block 110R. The determiningcircuit 150 activates a selection signal VM2 when the data to be programmed is loaded only on the sense andlatch block 170L of thememory block 110L. The determiningcircuit 150 activates the selection signals VM1 and VM2 when the data to be programmed is loaded on all of the sense and latchblocks -
FIG. 7 is a circuit diagram showing aswitching circuit 160 ofFIG. 3 according to an embodiment of the present invention. Referring toFIG. 7 , The switchingcircuit 160 receives driving signals S0-S15 outputted from the drivingsignal generator circuit 140, and generates first driving signals S0R-S15R or second driving signals S0L-S15L in response to selection signals VM1 and VM2 from the determiningcircuit 150. Theswitching circuit 160 comprises depletion typeMOS pass transistors type MOS transistors type MOS transistors - If the data to be programmed is loaded only on the sense and latch block 170R of the
first memory block 110R, the determiningcircuit 150 activates a selection signal VM1, and the output signals S0-S15 of the drivingsignal generator circuit 140 generated as selection signals S0R-S15R are applied to theswitch block 120R. When the data to be programmed is loaded only on the sense andlatch block 170L of thesecond memory block 110L, the determiningcircuit 150 activates the selection signal VM2, and output signals S0-S15 of the drivingsignal generator circuit 140 generated as driving signals S0L-S15L are applied to theswitch block 120L. If the data to be programmed is loaded on all of the sense and latchblocks second blocks circuit 150 activates the selection signals VM1 and VM2 simultaneously, and the output signals S0-S15 of the drivingsignal generator circuit 140 are outputted as first and second driving signals S0R-S15R and S0L-S15L that are applied to first and second switch blocks 120R and 120L. -
FIG. 8 is a timing diagram for illustrating a program operation of a NAND type flash memory device. The program operation of the memory device according to the present invention will be fully explained herein with reference to the drawings. The signals shown in the first six lines ofFIG. 8 are also identified in the circuit ofFIG. 6 . - As widely known, according to a program procedure of the NAND type flash memory device, a sequential data input command is introduced and an initial column address and a row (or a page) address are sequentially inputted. The initial column address is loaded on an internal address counter (not shown), and the internal address counter increases internal column addresses by one bit whenever data is inputted by a predetermined unit (a byte or a word unit). The data to be programmed is loaded on the sense and latch block(s) 170L or 170R as a page buffer circuit through a gate circuit as the column addresses increase. When all of the data is loaded, a program command for starting a program is inputted. The NAND type
flash memory device 100 performs program operation according an internal algorithm known in the art after the program command is inputted, and notifies that the memory device is in a busy state to outside through a R/nB pin during the program operation. - When the sequential program data command is inputted, the reset signal RST is activated to a pulse type. When the reset signal RST transitions from a low level to a high level, flip-flops FF1 and FF2 of the determining
circuits 150 are initialized. As the flip-flops FF1 and FF2 are initialized (referring toFIG. 8 ), the output signals VM1 and VM2 of the determiningcircuit 150 are set to a low level. Then, a starting (or initial) column address CAi where the data is going to be loaded is inputted, and the initial address counter (not shown) is set to an initial column address. Assume a column address for selecting memory blocks of the initial column addresses (e.g., an uppermost address signal) as “0”. According to this assumption, the data to be programmed will be loaded on the sense and latch block 170R of thememory block 110R. - After a column address is inputted, the data to be programmed is loaded on the sense and latch block 170R through a
column gate circuit 190R in synchronization with a clock signal CLK. Since the column address for selecting memory blocks is “0”, an output signal of the NOR gate G6 in the determiningcircuit 150 transitions from a high level to a low level during a low-high transition of the clock signal. This makes the selection signal VM1 transition from a low level to a high level. In this case, the activated selection signal VM1 has a high voltage through ahigh voltage switch 151. - If the column address is maintained as “0” continuously until all of the data to be programmed is loaded, only the selection signal VM1 will be activated. This transmits the driving signals S0-S15 inputted in the
switching circuit 160 only to a wordline switch block 120R. When the data loading is ended and a program command is introduced, a program voltage and a pass voltage will be applied to the word lines of thememory block 110R. Conversely, since the selection signal VM2 is not activated, a program voltage and a pass voltage are not applied to word lines of thememory block 110L. That is, in case of a partial program, the program voltage and the pass voltage are applied only to the word lines of a memory block corresponding to the sense and latch block with a loaded data to be programmed. Therefore, a program disturbance can be prevented (or relieved) according to a partial program scheme because the program voltage and the pass voltage are not applied to the word lines in the memory block corresponding to the sense and latch block without the loaded data to be programmed. - Meanwhile, if a value of the column address for selecting the memory blocks varies from “0” to “1” before all the data to be programmed is loaded, the data to be programmed is loaded on the sense and
latch block 170L of thememory block 110L through agate circuit 190L. As the column address varies from “0” to “1”, the output signal of the NOR gate G7 in the determiningcircuit 150 transitions from a high level to a low level in synchronization with a clock signal CLK. This activates the selection signal VM2 to high. This activation transmits the driving signal S0-S15 inputted in theswitching circuit 160 to a wordline switch block 120L. When the data loading is ended and a program command is introduced, a program voltage and a pass voltage will be applied to the word lines of the memory blocks 110R and 110L through aswitching circuit 160. Therefore, the data loaded on the sense and latchblocks - Although not shown in the drawings, it is clear to those skilled in the art that the memory blocks of the present invention can include a corresponding spare field memory region. In the case that one row is divided into two word lines, the spare field memory region will also be divided into two regions. The divided spare field memory regions each correspond to the corresponding memory blocks. Thus, in case of the NAND flash memory device according to the present invention, the memory cell array may be organized as illustrated in
FIG. 2 . That is, thememory block 110R includes one of the divided spare field memory regions and thememory block 110L includes the other spare field memory region. In the same way as illustrated above, the word lines of the memory block and the corresponding spare field memory region are controlled by the identical row selection circuit. - According to the present invention, a program voltage and a pass voltage are not applied to word lines of a memory block corresponding to a sense and latch block without a loaded data to be programmed, such that a program voltage disturbance cannot be prevented (or relieved) according to a partial program scheme.
- These embodiments were described on the bases of the structure in which one array is divided into only two memory blocks. However, it is well known to those skilled in the art that the present invention can be employed in the structures in which one array is divided into 4, 8 or more memory blocks.
- Changes can be made to the invention in light of the above detailed description. In general, in the following claims, the terms used should not be construed to limit the invention to the specific embodiments disclosed in the specification and the claims, but should be construed to include all methods and devices that are in accordance with the claims. Accordingly, the invention is not limited by the disclosure, but instead its scope is to be determined by the following claims.
Claims (18)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/819,385 US7184307B2 (en) | 2001-08-28 | 2004-04-05 | Flash memory device capable of preventing program disturbance according to partial programming |
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US31553601P | 2001-08-28 | 2001-08-28 | |
KR10-2001-0082417A KR100432884B1 (en) | 2001-08-28 | 2001-12-21 | Non-volatile semiconductor memory device with shared row selecting circuit |
KR2001-82417 | 2001-12-21 | ||
US10/222,573 US6731540B2 (en) | 2001-08-28 | 2002-08-15 | Non-volatile semiconductor memory device having shared row selection circuit |
KR2003-24812 | 2003-04-18 | ||
KR1020030024812A KR100543452B1 (en) | 2003-04-18 | 2003-04-18 | Flash memory device capable of preventing program disturbance according to partial programming |
US10/819,385 US7184307B2 (en) | 2001-08-28 | 2004-04-05 | Flash memory device capable of preventing program disturbance according to partial programming |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/222,573 Continuation-In-Part US6731540B2 (en) | 2001-08-28 | 2002-08-15 | Non-volatile semiconductor memory device having shared row selection circuit |
Publications (3)
Publication Number | Publication Date |
---|---|
US20040208059A1 US20040208059A1 (en) | 2004-10-21 |
US20070025150A9 true US20070025150A9 (en) | 2007-02-01 |
US7184307B2 US7184307B2 (en) | 2007-02-27 |
Family
ID=37726978
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/819,385 Expired - Lifetime US7184307B2 (en) | 2001-08-28 | 2004-04-05 | Flash memory device capable of preventing program disturbance according to partial programming |
Country Status (1)
Country | Link |
---|---|
US (1) | US7184307B2 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070064467A1 (en) * | 2005-07-05 | 2007-03-22 | Stmicroelectronics Sa | Read-only memory |
TWI486955B (en) * | 2011-03-23 | 2015-06-01 | Macronix Int Co Ltd | Flash memory device and programming method thereof |
WO2016043868A1 (en) * | 2014-09-16 | 2016-03-24 | Empire Technology Development Llc | Data storage based on rank modulation in single-level flash memory |
US20160217866A1 (en) * | 2014-04-01 | 2016-07-28 | SK Hynix Inc. | Semiconductor device being capable of improving the breakdown characteristics |
US9514822B2 (en) * | 2015-01-30 | 2016-12-06 | SK Hynix Inc. | Flash memory device |
US9916197B2 (en) | 2012-03-08 | 2018-03-13 | California Institute Of Technology | Rank-modulation rewriting codes for flash memories |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100684873B1 (en) * | 2004-11-22 | 2007-02-20 | 삼성전자주식회사 | Nonvolatile memory device and word line voltage control method thereof |
KR100669342B1 (en) * | 2004-12-21 | 2007-01-16 | 삼성전자주식회사 | Program method of nand flash memory device |
KR100725993B1 (en) * | 2005-12-28 | 2007-06-08 | 삼성전자주식회사 | Row decoder for preventing leakage current and semiconductor memory device having the same |
KR100694977B1 (en) * | 2006-03-27 | 2007-03-14 | 주식회사 하이닉스반도체 | High voltage switch circuit including a boosting circuit for increasing switching operation speed of the high voltage switch circuit and flash memory device with the same |
KR100708907B1 (en) | 2006-04-26 | 2007-04-18 | 한양대학교 산학협력단 | Nand flash memory device having booster line and its programming method |
KR100769772B1 (en) * | 2006-09-29 | 2007-10-23 | 주식회사 하이닉스반도체 | Flash memory device and method of erasing using thesame |
KR100770754B1 (en) * | 2006-10-12 | 2007-10-29 | 삼성전자주식회사 | Non-volatile memory device and method of programming the same |
JP4996277B2 (en) * | 2007-02-09 | 2012-08-08 | 株式会社東芝 | Semiconductor memory system |
US8351262B2 (en) * | 2007-04-23 | 2013-01-08 | Samsung Electronics Co., Ltd. | Flash memory device and program method thereof |
KR101521993B1 (en) * | 2009-04-03 | 2015-05-22 | 삼성전자주식회사 | Nonvolatile memory device independent from breakdown voltage |
KR101636015B1 (en) * | 2010-02-11 | 2016-07-05 | 삼성전자주식회사 | Non-volatile data storage device, programming method thereof and memory system including the same |
KR20120121166A (en) * | 2011-04-26 | 2012-11-05 | 에스케이하이닉스 주식회사 | Semiconductor device and operating method thereof |
US9378830B2 (en) | 2013-07-16 | 2016-06-28 | Seagate Technology Llc | Partial reprogramming of solid-state non-volatile memory cells |
US9576649B2 (en) | 2015-03-31 | 2017-02-21 | Seagate Technology Llc | Charge loss compensation through augmentation of accumulated charge in a memory cell |
KR102491624B1 (en) * | 2015-07-27 | 2023-01-25 | 삼성전자주식회사 | Method for operating data storage device and method for operating system having same |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5677873A (en) * | 1995-09-19 | 1997-10-14 | Samsung Electronics Co., Ltd. | Methods of programming flash EEPROM integrated circuit memory devices to prevent inadvertent programming of nondesignated NAND memory cells therein |
US5815435A (en) * | 1995-10-10 | 1998-09-29 | Information Storage Devices, Inc. | Storage cell for analog recording and playback |
US5991202A (en) * | 1998-09-24 | 1999-11-23 | Advanced Micro Devices, Inc. | Method for reducing program disturb during self-boosting in a NAND flash memory |
US6081450A (en) * | 1996-11-14 | 2000-06-27 | Sharp Kabushiki Kaisha | Non-volatile semiconductor memory device in which read, write and erase operations can be simultaneously performed in different memory cell array blocks |
US6542406B2 (en) * | 2000-07-13 | 2003-04-01 | Samsung Electronics Co. Ltd. | Row decoder of a NOR-type flash memory device |
US6731540B2 (en) * | 2001-08-28 | 2004-05-04 | Samsung Electronics Co., Ltd. | Non-volatile semiconductor memory device having shared row selection circuit |
-
2004
- 2004-04-05 US US10/819,385 patent/US7184307B2/en not_active Expired - Lifetime
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5677873A (en) * | 1995-09-19 | 1997-10-14 | Samsung Electronics Co., Ltd. | Methods of programming flash EEPROM integrated circuit memory devices to prevent inadvertent programming of nondesignated NAND memory cells therein |
US5815435A (en) * | 1995-10-10 | 1998-09-29 | Information Storage Devices, Inc. | Storage cell for analog recording and playback |
US6081450A (en) * | 1996-11-14 | 2000-06-27 | Sharp Kabushiki Kaisha | Non-volatile semiconductor memory device in which read, write and erase operations can be simultaneously performed in different memory cell array blocks |
US5991202A (en) * | 1998-09-24 | 1999-11-23 | Advanced Micro Devices, Inc. | Method for reducing program disturb during self-boosting in a NAND flash memory |
US6542406B2 (en) * | 2000-07-13 | 2003-04-01 | Samsung Electronics Co. Ltd. | Row decoder of a NOR-type flash memory device |
US6731540B2 (en) * | 2001-08-28 | 2004-05-04 | Samsung Electronics Co., Ltd. | Non-volatile semiconductor memory device having shared row selection circuit |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070064467A1 (en) * | 2005-07-05 | 2007-03-22 | Stmicroelectronics Sa | Read-only memory |
US7447074B2 (en) * | 2005-07-05 | 2008-11-04 | Stmicroelectronics Sa | Read-only memory |
TWI486955B (en) * | 2011-03-23 | 2015-06-01 | Macronix Int Co Ltd | Flash memory device and programming method thereof |
US9916197B2 (en) | 2012-03-08 | 2018-03-13 | California Institute Of Technology | Rank-modulation rewriting codes for flash memories |
US20160217866A1 (en) * | 2014-04-01 | 2016-07-28 | SK Hynix Inc. | Semiconductor device being capable of improving the breakdown characteristics |
WO2016043868A1 (en) * | 2014-09-16 | 2016-03-24 | Empire Technology Development Llc | Data storage based on rank modulation in single-level flash memory |
CN107077418A (en) * | 2014-09-16 | 2017-08-18 | 英派尔科技开发有限公司 | Data storage based on the hierarchical modulation in single stage flash memory |
US9772935B2 (en) | 2014-09-16 | 2017-09-26 | Empire Technology Development Llc | Data storage based on rank modulation in single-level flash memory |
US9983991B2 (en) | 2014-09-16 | 2018-05-29 | Empire Technology Development Llc | Data storage based on rank modulation in single-level flash memory |
US9514822B2 (en) * | 2015-01-30 | 2016-12-06 | SK Hynix Inc. | Flash memory device |
Also Published As
Publication number | Publication date |
---|---|
US7184307B2 (en) | 2007-02-27 |
US20040208059A1 (en) | 2004-10-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6977846B2 (en) | Non-volatile semiconductor memory device in which one page is set for a plurality of memory cell arrays | |
US7184307B2 (en) | Flash memory device capable of preventing program disturbance according to partial programming | |
US7095657B2 (en) | Nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array | |
KR100463197B1 (en) | Nand-type flash memory device with multi-page program, multi-page read, and multi-block erase operations | |
KR100454116B1 (en) | Bit line setup and discharge circuit for programming non-volatile memory | |
US5768188A (en) | Multi-state non-volatile semiconductor memory and method for driving the same | |
KR100742278B1 (en) | Nand flash memory device with improved operating operation and dual program fucntion | |
KR960005359B1 (en) | Nonvolatile semiconductor memory device | |
KR100648289B1 (en) | Flash memory device capable of improving program speed and program method thereof | |
US7154800B2 (en) | No-precharge FAMOS cell and latch circuit in a memory device | |
US8605512B2 (en) | Nonvolatile semiconductor memory device and method of operating a nonvolatile memory device | |
US6307783B1 (en) | Descending staircase read technique for a multilevel cell NAND flash memory device | |
US6614683B1 (en) | Ascending staircase read technique for a multilevel cell NAND flash memory device | |
JP3662725B2 (en) | Nonvolatile semiconductor memory device capable of simultaneously performing single bit cell and large bit cell operations | |
US11227658B2 (en) | Flash memory and method for controlling the same | |
JP3414587B2 (en) | Nonvolatile semiconductor memory device | |
KR100543452B1 (en) | Flash memory device capable of preventing program disturbance according to partial programming | |
US20200402578A1 (en) | Flash memory and method for operating the same | |
US7692967B2 (en) | Method of programming a nonvolatile memory device using hybrid local boosting | |
KR20060016553A (en) | Page buffer and method of reading a flash memory cell using the same | |
US20120140572A1 (en) | Semiconductor memory device and method of operating the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LEE, JUNE;REEL/FRAME:014784/0565 Effective date: 20040325 |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
AS | Assignment |
Owner name: MOSAID TECHNOLOGIES INCORPORATED, CANADA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SAMSUNG ELECTRONICS CO., LTD.;REEL/FRAME:025423/0170 Effective date: 20101026 |
|
AS | Assignment |
Owner name: ROYAL BANK OF CANADA, CANADA Free format text: U.S. INTELLECTUAL PROPERTY SECURITY AGREEMENT (FOR NON-U.S. GRANTORS) - SHORT FORM;ASSIGNORS:658276 N.B. LTD.;658868 N.B. INC.;MOSAID TECHNOLOGIES INCORPORATED;REEL/FRAME:027512/0196 Effective date: 20111223 |
|
AS | Assignment |
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., Free format text: CHANGE OF NAME;ASSIGNOR:MOSAID TECHNOLOGIES INCORPORATED;REEL/FRAME:032439/0638 Effective date: 20140101 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: CONVERSANT IP N.B. 868 INC., CANADA Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344 Effective date: 20140611 Owner name: CONVERSANT IP N.B. 276 INC., CANADA Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344 Effective date: 20140611 Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:ROYAL BANK OF CANADA;REEL/FRAME:033484/0344 Effective date: 20140611 |
|
AS | Assignment |
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CANADA Free format text: CHANGE OF ADDRESS;ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:033678/0096 Effective date: 20140820 Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., Free format text: CHANGE OF ADDRESS;ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:033678/0096 Effective date: 20140820 |
|
AS | Assignment |
Owner name: CPPIB CREDIT INVESTMENTS INC., AS LENDER, CANADA Free format text: U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:033706/0367 Effective date: 20140611 Owner name: ROYAL BANK OF CANADA, AS LENDER, CANADA Free format text: U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:033706/0367 Effective date: 20140611 |
|
AS | Assignment |
Owner name: CPPIB CREDIT INVESTMENTS, INC., CANADA Free format text: AMENDED AND RESTATED U.S. PATENT SECURITY AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:046900/0136 Effective date: 20180731 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |
|
AS | Assignment |
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CANADA Free format text: RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:ROYAL BANK OF CANADA, AS LENDER;REEL/FRAME:047645/0424 Effective date: 20180731 Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., Free format text: RELEASE OF U.S. PATENT AGREEMENT (FOR NON-U.S. GRANTORS);ASSIGNOR:ROYAL BANK OF CANADA, AS LENDER;REEL/FRAME:047645/0424 Effective date: 20180731 |
|
AS | Assignment |
Owner name: CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC., CANADA Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:CPPIB CREDIT INVESTMENTS INC.;REEL/FRAME:054371/0684 Effective date: 20201028 |
|
AS | Assignment |
Owner name: MOSAID TECHNOLOGIES INCORPORATED, CANADA Free format text: CHANGE OF NAME;ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY INC.;REEL/FRAME:058297/0646 Effective date: 20210401 |
|
AS | Assignment |
Owner name: MOSAID TECHNOLOGIES INCORPORATED, CANADA Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY'S NAME PREVIOUSLY RECORDED ON REEL 058297 FRAME 0646. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME;ASSIGNOR:CONVERSANT INTELLECTUAL PROPERTY MANAGEMENT INC.;REEL/FRAME:064746/0409 Effective date: 20210401 |