KR100708907B1 - Nand flash memory device having booster line and its programming method - Google Patents

Abstract

The present invention relates to a memory device, and more particularly, to a memory device and a method of manufacturing the same, which improves the reliability of the memory device by improving the program disturbance and / or the path disturbance of the non-selected memory cell. will be. According to an embodiment of the present invention, a NAND flash memory device may include: a plurality of floating gates formed over active regions of a semiconductor substrate; An isolation layer formed between the active regions in the semiconductor substrate; A booster line formed in the device isolation layer; And a booster line including a control gate covering the floating gate and the booster line. Using the program method with booster lines, the power consumption is low at the low supply voltage, the chip area is small, and the programming method is simple and high efficiency.

Memory, Flash, Nand, Booster Lines, Program Jammer, Pass Jammer

Description

NAND flash memory device having a booster line and its programming method {NAND flash memory device having booster line and its programming method}

1 is a circuit diagram of a structure of a NAND flash memory device, that is, a cell string connected to bit lines, respectively.

2 is a plan view of a NAND flash memory device using a shallow trench isolation process.

3 is a cross-sectional view of a NAND flash memory device taken along the line AA ′ of FIG. 2.

FIG. 4 is a diagram illustrating a program disturbance characteristic and a path disturbance characteristic when programming the NAND flash memory device illustrated in FIGS. 1 to 3;

5 is a circuit diagram of a NAND flash memory device having a booster line according to an embodiment of the present invention.

FIG. 6 is a plan view of a NAND flash memory device having a booster line shown in FIG. 5. FIG.

FIG. 7 is a cross-sectional view taken along the line BB ′ of FIG. 6.

8 is a graph illustrating an amount of shift of a threshold voltage according to a channel voltage of a non-program memory cell.

9 is a capacitance equivalent circuit diagram of memory cells included in one cell string of a conventional NAND flash memory device.

10 is a capacitance equivalent circuit diagram of a NAND flash memory device having a booster line according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

MSS1, MSS2, MSS51, MSS52: String Select Transistors

MGS1, MGS2, MGS51, MGS52: Ground Select Transistors

M1-0 to M1-15, M2-0 to M2-15, M51-0 to M51-15, M52-0 to M52-15: memory cell transistors

BL1 (161), BL2 (162), BL51 (561), BL52 (562): bit line

SSL 120, SSL 520: String Selection Line Pattern

GSL 140, GSL 540: Ground Select Line Pattern

500a, 500b: Booster Line

The present invention relates to a memory device, and more particularly, to a memory device and a method of manufacturing the same, which improves the reliability of the memory device by improving the program disturbance and / or the path disturbance of the non-selected memory cell. will be.

Flash memory is a memory in which data can be continuously stored in the memory even when there is no power supply, and data can be freely stored / deleted. Flash memory is divided into NOR type and NAND type according to the internal method. The NOR type is a cell connected in parallel, and the NAND type is a cell connected in series.

NAND flash memory is used in an SD card or a memory stick among memory cards, and NOR flash memory is used in an MMC card or a compact flash memory.

1 is a circuit diagram of a structure of a NAND flash memory device, that is, a cell string connected to bit lines, and FIG. 2 is a plan view of a NAND flash memory device using a shallow trench isolation (STI) process. 3 is a cross-sectional view of a NAND flash memory device along the line AA ′ of FIG. 2.

The first cell string 10 has two select transistors MSS1 and MGS1 and a drain-source current path is in series between the source of the string select transistor MSS1 and the ground (source) of the ground select transistor MGS1. The connected memory cell transistors M1-0 to M1-15 are included. The second cell string 20 has two select transistors MSS2 and MGS2 and a drain-source current path in series between the source of the string select transistor MSS2 and the ground (source) of the ground select transistor MGS2. It includes connected memory cell transistors M2-0 to M2-15.

Each of the memory cell transistors M1-0 to M1-15 and M2-0 to M2-15 includes a drain region and a source region separated by a channel. The floating gates 135a, 135b, 135c,... Are formed on the oxide surfaces 310a, 310b, 310c,... Of the channel surface, and the control gate 130 is formed on the insulating films 320a, 320b, 320c,... ) Is formed on. The drains 111 and 112 of the string select transistors MSS1 and MSS2 are connected to the bit lines BL1 161 and BL2 162, respectively, and the sources of the ground select transistors MGS1 and MGS2 are common source lines. Is connected to 150. The common source line 150 receives a power supply voltage Vcc during a program operation. Gates of the string select transistors MSS1 and MSS2 and the ground select transistors MGS1 and MGS2 are connected to the string select line SSL 120 and the ground select line GSL 140, respectively.

The program operation of the NAND flash memory device is as follows.

In general, in the NAND flash memory structure, the memory transistors are erased before programming. In this operation, erasing of the memory cell transistors M1-0 to M1-15 and M2-0 to M2-15 applies an erase voltage (eg, 20V) to the semiconductor substrate, for example a reference of 0V. This is done by applying a voltage (ie, ground voltage VGS) to word lines WL0 130-0 to WL15 130-15. Electrons stored in the floating gates of the memory cell transistors M1-0 to M1-15 and M2-0 to M2-15 are stored by FN-Nordheim tunneling, and memory cell transistors M1-0. M1-15 and M2-0 to M2-15 are changed to depletion mode transistors. In this case, it is assumed that the erased memory cell transistors store logic '1' data.

A process in which the program operation is performed under the assumption that the memory cell transistor M1-0 corresponding to the first word line WL0 130-0 of the first cell string BL1 161 is programmed will be described. The power supply voltage Vcc and the ground voltage Vss are applied to the string select line SSL 120 and the ground select line GSL 140, respectively. Each of the bit lines BL1 161 and BL2 162 is applied with a ground voltage Vss (data '0') or a power supply voltage Vcc (data '1') according to a data state to be programmed. The voltage applied to the bit line that does not contain the memory cell to be programmed is called the inhibit voltage. Here, the ground voltage Vss (for example, 0 V) is applied to the first bit line BL1 161, and the power supply voltage Vcc (for example, 3.3 V) is applied to the second bit line BL2 162. Applied, the power supply voltage becomes a prohibition voltage. The pass voltage Vpass (e.g., 10V) is an unselected word line except for word lines WL1 130-1 to WL15 130-15, that is, selected word line WL0 130-0. Is applied. A reference voltage (for example, ground voltage Vss) is applied to the semiconductor substrate (bulk) 300. After a predetermined time has elapsed, the program voltage Vpgm (for example, 18V) is applied to the selected word line WL0 130-0.

In this program operation, the string select transistor MSS2 in the second cell string 20 connected to the second bit line BL2 162 to which the power supply voltage Vcc is applied is turned off so that the second cell string 20 is turned off. Is plotted. Therefore, when the program voltage Vpgm is applied to the control gate of the memory cell transistor M2-0 corresponding to the selected word line WL0 130-0 in the second cell string 20, the source and drain And the potential of the channel rises by capacitor coupling. That is, the difference between the voltage of the control gate and the source-drain-channel voltage is not increased enough to cause F-N tunneling, and the memory cell transistor M2-0 remains in an erased state.

On the other hand, since the string select transistor MSS1 in the first cell string 10 is connected to the first bit line BL1 161 having the ground voltage Vss, the string select transistor MSS1 is turned on. The source, drain, and channel potentials of the selected memory cell transistors M1-0 in the cell string 10 are equal to the ground voltage Vss. When the program voltage Vpgm is applied to the selected memory cell transistor M1-0 in the first cell string 10, electrons are trapped and accumulated in the floating gate of the selected memory cell transistor M1-0 by FN tunneling. do. The trapping and accumulation of large amounts of electrons on the floating gate causes the threshold voltage of the selected memory cell transistor M1-0 to rise (eg, about 6 to 7V). Thus, the selected memory cell transistor M1-0 is changed to an enhancement mode transistor and programmed to store logic '0' data.

In a program operation as described above, a pass disturbance or a program disturbance in which non-selected memory cell transistors are programmed in addition to the selected memory cell transistor M1-0 may occur. FIG. 4 is a diagram illustrating a program disturbance characteristic and a path disturbance characteristic when programming the NAND flash memory device illustrated in FIGS. 1 to 3.

Referring to '410' of FIG. 4, a program disturbance is that a memory cell transistor having a gate connected to the same word line WL0 130-0 as the selected memory cell transistor M1-0 is programmed. For example, memory cell transistor M2-0 is programmed. This occurs when the pass voltage Vpass applied to the unselected word lines WL1 130-1 to WL15 130-15 is lowered below a predetermined value (eg, 10V). When the pass voltage Vpass is lowered, the voltage boosted by the channel of the unselected memory cell transistor M2-0 is lowered, and the channel potential is lowered below the programmable potential (eg, 7V) by FN tunneling. The unselected memory cell transistor M2-0 is programmed.

Referring to '420' of FIG. 4, the path disturbance is caused by the unselected word lines WL1 130-1 in the cell string to which the selected memory cell transistor M1-0 belongs, in this case, the first cell string 10. The memory cell transistors M1-1 to M1-15 having gates connected to WL15 130-15 are programmed. This occurs when the pass voltage Vpass of the word line coupled with the unselected memory cell transistors is raised above the minimum voltage at which the memory cell transistors can be programmed (eg, 10V).

In FIG. 4, when the pass voltage is 3 V or less, neither program disturb nor pass disturb occurs. In this bias state, since the non-selected memory cells M2-1, ..., M2-15 connected to the non-programmed memory cell M2-0 are turned off, the non-programmed memory cells M2-0 and the non-selected memory cells ( M2-1, ..., M2-15) are electrically isolated. When the program disturbance characteristic is evaluated, the non-selected memory cells M2-1, ..., M2-15 connected to the non-program memory cell M2-0 except for the non-program memory cell M2-0 are programmed. This is because it is assumed. At this time, since the threshold voltage in the programmed state is, for example, 3V or more, when the pass voltage is 3V or less, the unselected memory cells M2-1, ..., M2-15 are turned off. That is, the channel of the non-program memory cell M2-0 is floated. In this state, if a program voltage (for example, 18V) is applied to the selected word line, the channel voltage of the non-program memory cell M2-0 is effectively increased so that the program disturbance characteristic hardly appears.

However, when the pass voltage is less than or equal to 3V, the memory cells M1-0 and the non-selected memory cells M1-1, ..., M1-15 that are programmed are not electrically connected to each other, and thus are applied to the selected bit line BL1. Since the 0V voltage is not connected to the channel voltage of the memory cell M1-0 that is programmed, the channel is floated. In this state, when the program voltage is applied to the selected word line WL0, the channel voltage of the memory cell M1-0 that is programmed is boosted and increased, as the channel voltage of the non-program memory cell M2-0 is boosted and raised. The program will not work. Therefore, the pass voltage cannot be made low.

In order to improve the program disturbance and the path disturbance of the NAND flash memory device, the program disturbance is reduced by increasing the channel voltage of the non-program memory cell. In order to increase the channel voltage of a non-program cell, a method of directly applying a high voltage through a bit line has been used. However, this method requires a charge pump circuit that occupies a large silicon area and has a disadvantage in that power consumption is large. Accordingly, various self-boosting program inhibitor schemes have been developed to reduce program disturb characteristics caused by non-program memory cells without directly applying a high voltage to a bit line.

Although a Vcc-bitline programming scheme is used among self-boosting program prohibition methods, there is a limit in increasing the channel voltage of non-program memory cells. This is because it is difficult to lower the bit line voltage below a certain voltage because the channel voltage is determined by the bit line voltage level. Local self-boosting schemes can be used to locally increase the channel voltage, but random programming is not possible in this case. If the boosted-bitline programming scheme is used, the channel voltage can be increased. However, the large bitline capacitance has the disadvantage of increasing program time, power consumption, and manufacturing cost. In addition, there is a method of improving the program disturbance by increasing the channel voltage by using a source-line programming scheme or using a negative threshold voltage cell architecture. The disadvantage is that the operation is complicated and additional peripheral circuits are required.

Raising the channel voltage of unprogrammed cells using the self-boosting program prohibition method in NAND type flash memory device structure is limited and has a large power consumption, performance degradation, increased chip area and complicated programming methods and manufacturing. Losses, such as an increase in unit cost, occur. In addition, there is a disadvantage in that the threshold voltage distribution is widened by floating gate coupling between adjacent cells when the device density increases, and as the isolation width decreases, the program disturb characteristic becomes worse due to an increase in leakage current. New device structures are needed to improve the problem.

Accordingly, the present invention provides a NAND flash memory device having a high efficiency booster line having a low power consumption, a small chip area, and a simple programming method at a low supply voltage using a program method having a booster line.

The present invention also provides a NAND flash memory device having a booster line capable of obtaining a high channel voltage of a nonprogrammed memory cell without applying a pass voltage to an unselected word line.

In addition, the present invention provides a NAND flash memory device having a booster line which greatly reduces the program disturb characteristic and completely eliminates the path disturb, thereby greatly improving the reliability.

Other objects of the present invention will be readily understood through the following description.

In order to achieve the above object, according to an aspect of the present invention, a plurality of floating gate formed on the active region of the semiconductor substrate; An isolation layer formed between the active regions in the semiconductor substrate; A booster line formed in the device isolation layer; And a booster line including a floating gate and a control gate covering the booster line.

Preferably, the device isolation layer may be an STI formed by a shallow trench isolation process, and the booster line may form a capacitance between the active regions and the control gate.

In order to achieve the above objects, according to another aspect of the invention, a plurality of device isolation film formed in a predetermined region of the semiconductor substrate, parallel to each other; A string select line pattern and a ground select line pattern crossing the active regions between the plurality of device isolation layers and parallel to each other; A plurality of word line patterns disposed between the string select line pattern and the ground select line pattern; And a booster line intersecting the plurality of word line patterns in each of the device isolation layers, the booster line including a booster line formed between the string select line pattern and the ground select line pattern. .

Preferably, the device isolation layer is an STI formed by a shallow trench isolation process, and the booster line may form capacitance between the active regions between the device isolation layer and the word line pattern.

In order to achieve the above objects, according to another aspect of the present invention, a plurality of memory cell transistors arranged in rows and columns and electrically erased and programmed, a plurality of word lines extending in the row direction, the column direction A method of programming a NAND flash memo device having a plurality of bit lines extending to each other and booster lines formed between the bit lines, the method comprising: selecting a word line and a bit line corresponding to a memory cell transistor to be programmed; ; Supplying a program voltage to the selected word line and plotting the unselected word lines; And a booster line including supplying a forbidden voltage to an unselected bit line.

Advantageously, the channel voltage of the memory cell transistor to be programmed may be relatively high by the program voltage through the booster line.

Hereinafter, exemplary embodiments of a NAND flash memory device having a booster line according to the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, when it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. Numbers (eg, first, second, etc.) used in the description of the present specification are merely identification symbols for sequentially distinguishing identical or similar entities.

5 is a circuit diagram of a NAND flash memory device having a booster line according to an exemplary embodiment of the present invention, FIG. 6 is a plan view of a NAND flash memory device having a booster line shown in FIG. 5, and FIG. 6 is a cross-sectional view taken along the line B-B ', and FIG. 8 is a graph showing the amount of shift of the threshold voltage according to the channel voltage of the non-program memory cell. In the following description, it is assumed that one cell string includes 16 memory cells, but the same may be applied to other cases.

The first cell string 510 has two select transistors MSS51 and MGS51 and a drain-source current path in series between the source of the string select transistor MSS51 and the ground (source) of the ground select transistor MGS51. The connected memory cell transistors M51-0 to M51-15 are included. The second cell string 520 has two select transistors MSS52 and MGS52 and a drain-source current path in series between the source of the string select transistor MSS52 and the ground (source) of the ground select transistor MGS52. Connected memory cell transistors M52-0 to M52-15.

Each of the memory cell transistors M51-0 to M51-15 and M52-0 to M52-15 includes a drain region and a source region separated by a channel. The floating gates 535a, 535b, 535c,... Are formed on the oxide surfaces 710a, 710b, 710c,... Of the channel surface, and the control gate 530 is formed of insulating films 720a, 720b, 720c,... ) Is formed on. The drains 511 and 512 of the string select transistors MSS51 and MSS52 are connected to the bit lines BL51 561 and BL52 562, respectively, and the sources of the ground select transistors MGS51 and MGS52 are common source lines. 550 is connected. The common source line 550 is supplied with a power supply voltage Vcc during a program operation. Gates of the string select transistors MSS51 and MSS52 and the ground select transistors MGS51 and MGS52 are connected to the string select line SSL 520 and the ground select line GSL 540, respectively. Assuming that the memory cell transistor to be programmed is M51-0, the memory cell transistor group 580 affected by the booster lines 500a and 500b, which will be described later, is used for each memory cell transistor of the second cell string 520. (M52-0, ..., M52-15).

The bit lines BL51 561, BL52 562,... Are separated by device isolation layers 571, 572,... The device isolation layers 571, 572,... Are STIs formed by a shallow trench isolation (STI) process, and booster lines 500a, 500b,... Are formed in the device isolation layers 571, 572,. . Booster lines 500a and 500b are formed between bit lines BL51 561, BL52 562, ... (ie, there are two booster lines, one on each side of one bit line), and a string select line Referring to the plan view of FIG. 6, the word lines 530-0, 530-1,..., 530-15 between the SSL 520 and the ground select line GSL 540 intersect each other. A1 to A8).

A plurality of device isolation layers 571, 572,... Parallel to each other are formed in a predetermined region (here, STI) of the semiconductor substrate 700. A tunnel oxide film (not shown) is formed on active regions (ie, regions where bit lines BL51 561 and BL52 562 are to be formed) between the plurality of device isolation layers 571, 572,... . A string select line pattern 520 and a ground select line pattern 540 are disposed across the plurality of device isolation layers 571, 572,..., And the tunnel oxide layer. The string select line pattern 520 and the ground select line pattern 540 are arranged in parallel at a predetermined interval, and a plurality of word line patterns 50-0, 530-1,. Is placed.

The string select line pattern 520 includes a string select line, a gate interlayer insulating film (not shown), and a dummy gate electrode (not shown), which are sequentially stacked, and the ground select line pattern 540 is a ground select line, which is sequentially stacked, a gate It is composed of an interlayer insulating film (not shown) and a dummy gate electrode (not shown). Each of the word line patterns 530-0, 530-1, ..., 530-15 is sequentially stacked with channel oxide films 710a, 710b, ..., floating gates 535a, 535b, ..., and gate interlayer insulating films 720a, 720b. , ...) and a word line (i.e., control gate 530). The floating gates 535a, 535b, ... are formed at portions where each active region and each word line pattern cross each other.

Impurity regions are formed in active regions between the string select line pattern 520, the plurality of word line patterns 50-0-530-1,..., 530-15, and the ground select line pattern 540. The impurity regions are regions doped with impurities of a conductive type different from that of the semiconductor substrate 700. Impurity regions formed in the active regions adjacent to the string select line pattern 520 and opposite to the ground select line pattern 540 correspond to drain regions 511 and 512 of each cell string.

In addition, the impurity regions formed in the active regions adjacent to the ground select line pattern 540 and opposite the string select line pattern 520 correspond to source regions of each cell string. A common source line 550 parallel to the ground select line pattern 540 is disposed on each of the source regions and the device isolation layers between the source regions.

A plurality of bit lines BL51 561 and BL52 562 are formed across the plurality of word line patterns 50-0, 530-1,..., 530-15 and the common source line 550. Each bit line BL51 561 or BL52 562 is electrically connected to each drain region.

Here, the program operation of the NAND flash memory device having the booster line according to the embodiment of the present invention is as described above, and the differences are as follows.

Conventionally, the pass voltage Vpass (for example, 10V) is unselected except for the word lines WL1 530-1 to WL15 530-15, that is, the selected word line WL0 50-0. Applied to word lines. However, according to a preferred embodiment of the present invention, it is possible to sufficiently increase the channel voltage of the non-program memory cell without applying the pass voltage by the booster lines 500a and 500b, so that the pass voltage is applied to the unselected word lines. And floats unselected word lines. After a predetermined time has elapsed, the program voltage Vpgm (for example, 18V) is applied to the selected word line WL0 530-0.

Hereinafter, it will be assumed that the first word line WL0 in the first bit line BL1 or BL51 is selected.

Referring to Figure 8, the initial threshold voltage (Vth) (memory '1' state: it can usually be between -3V and -1V because the designer can vary the threshold voltage of the device's erased state) The negative threshold voltage may move to a positive value by shifting the threshold voltage due to the program disturbance characteristic. At this time, since the read voltage of the selected cell is 0V, the cell that was originally '1' is read as '0' and an error appears. Referring to 810, since the shift of the threshold voltage decreases as the channel voltage of the non-program memory cell increases, the program disturbance characteristic may be reduced by increasing the channel voltage.

Therefore, a coupling ratio between the control gate 130 and the floating gate 135b of the non-program memory cell M2-0 corresponding to the unselected bit line BL2 of the selected word line WL0 is determined. Increase the channel voltage.

In addition, when several partial programs are performed on the same word line, the programming method using the booster line proposed in the present invention can execute more partial programs because the margin for read error due to threshold voltage shift is high.

9 is a capacitance equivalent circuit diagram of memory cells included in one cell string of a conventional NAND flash memory device, and FIG. 10 is a capacitance equivalent of a NAND flash memory device having a booster line according to an exemplary embodiment of the present invention. It is a circuit diagram.

Referring to FIG. 9, a gate oxide capacitance C _ONO is formed between the control gate 130 and the floating gate 135b, and a tunnel oxide capacitance C _OX is formed between the floating gate 135b and the channel. do.

10, booster lines 500a and 500b are formed at both sides of the channel of the non-program memory cell M52-0. Therefore, in addition to the gate oxide capacitance C _ONO and the tunnel oxide capacitance C _OX , the upper oxide capacitance C _TOP and the side oxide capacitance C _SW by the booster lines 500a and 500b are additionally formed.

Therefore, in the NAND type flash memory device having a booster line, the coupling ratio is four kinds of gate oxide capacitance (C _ONO ), tunnel oxide capacitance (C _OX ), upper oxide capacitance (C _TOP ), and side oxide capacitance (C _SW ). Since it is determined by the factor, it is possible to overcome the limitation of the coupling ratio, which was previously determined only by the gate oxide capacitance (C _ONO ) and the tunnel oxide capacitance (C _OX ).

Formulating the capacitance models of FIGS. 9 and 10 is the same as Equations 1 and 2 below. Equation 1 is a formula of the capacitance model of FIG. 9, Equation 2 is a formula of the capacitance model of FIG.

는 선택되지 않은 비트라인을 통해서 프리차지된 전압이고,

는 기존의 낸드 플래시 메모리 소자의 '0' 상태의 문턱전압이다.

은 기존의 낸드형 플래시 메모리 소자의 채널 부스트 비율이고,

와

은 각각 부스터 라인을 가지는 낸드형 플래시 메모리 소자의 비프로그램 메모리 셀의 채널 부스트 비율과 부스터 라인을 게이트로 하는 비선택 메모리 셀의 채널 부스트 비율을 나타낸다. C_ch는 채널 커패시턴스로 16개 셀의 반전층과 p 우물층, 그리고 n 확산층과 p 우물층 사이의 캐패시턴스를, C_cs 는 셀 스트링 간의 커패시턴스로 16개 셀의 활성영역과 다른 셀 스트링에 있는 셀 사이의 캐패시턴스를 나타낸다. C_TOTAL은 기존의 낸드형 플래시 메모리 소자의 16개 셀의 총 캐패시턴스를 나타내고 C'_TOTAL은 부스터 라인을 가지는 낸드형 플래시 메모리 소자의 총 캐패시턴스를 나타낸다.here,

Is the voltage precharged through the unselected bit lines,

Is a threshold voltage of a '0' state of a conventional NAND flash memory device.

Is the channel boost ratio of conventional NAND flash memory devices,

Wow

Denotes the channel boost ratio of the non-program memory cell of the NAND flash memory device having the booster line and the channel boost ratio of the non-selected memory cell gated by the booster line. C _ch is the channel capacitance, the capacitance between the inverted layer and the p well layer of 16 cells, and the capacitance between the n diffusion layer and the p well layer, and C _cs is the capacitance between the cell strings and the cells in the cell region different from the active region of 16 cells. Represents the capacitance between. C _TOTAL represents the total capacitance of 16 cells of a conventional NAND flash memory device, and C ' _TOTAL represents the total capacitance of a NAND flash memory device having a booster line.

는

보다 크다. 따라서 기존 플래시 메모리 소자의 비프로그램 메모리 셀의 채널 전압보다 부스터 라인을 가지는 낸드형 플래시 메모리 소자의 비프로그램 메모리 셀의 채널 전압이 높고 이에 따라 비프로그램 메모리 셀의 프로그램 방해 특성을 줄이게 된다. 또한, 부스터 라인을 이용한 프로그래밍 방법은 비선택 워드 라인에 아무런 전압도 주지 않기 때문에 비선택 메모리 셀들에 의한 패스 방해도 없게 된다. Since the effective swing voltage for increasing the channel voltage of the conventional NAND flash memory device is (Vpass-V _th0 -V _chi ), and the NAND flash memory device having a booster line is (Vpgm-V _chi ), The effective voltage amplitude of NAND flash memory devices with booster lines is much larger. In addition, the non-program memory cell of the NAND flash memory device having a booster line has an upper oxide capacitance C _TOP by the booster lines 500a and 500b in addition to the gate oxide capacitance C _ONO and the tunnel oxide capacitance C _OX . Channel Boost Ratio with Additional Side-by-Side Oxide Capacitance (C _SW ) Paralleled

Is

Greater than Therefore, the channel voltage of the non-program memory cell of the NAND flash memory device having the booster line is higher than that of the non-program memory cell of the conventional flash memory device, thereby reducing the program disturbance characteristic of the non-program memory cell. In addition, the programming method using the booster line does not apply any voltage to the unselected word line, thereby eliminating the path interference by the unselected memory cells.

As described above, the NAND flash memory device having the booster line and the program method according to the present invention use the program method having the booster line, which consumes less power at low supply voltage, the chip area is small, the programming method is simple, and the high efficiency. to be.

In addition, a high channel voltage of the non-program memory cell can be obtained without applying a pass voltage to the unselected word line.

It also greatly reduces reliability by reducing program disturbances and completely eliminating pass disturbances.

In addition, when a plurality of partial programs are executed on the same word line, it is possible to implement more partial programs because the margin for read error due to threshold voltage shift is high.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

Claims (8)

A plurality of floating gates formed over the active regions of the semiconductor substrate; An isolation layer formed between the active regions in the semiconductor substrate; A booster line formed in the device isolation layer; And A control gate covering the floating gate and the booster line NAND flash memory device having a booster line comprising a. The method of claim 1, The device isolation layer is a NAND flash memory device having a booster line of STI formed by a shallow trench isolation process. The method of claim 1, And the booster line has a booster line forming a capacitance between the active regions and the control gate. A plurality of device isolation films formed in a predetermined region of the semiconductor substrate and parallel to each other; A string select line pattern and a ground select line pattern crossing the active regions between the plurality of device isolation layers and parallel to each other; A plurality of word line patterns disposed between the string select line pattern and the ground select line pattern; And A booster line intersecting the plurality of word line patterns in each device isolation layer and formed between the string select line pattern and the ground select line pattern NAND flash memory device having a booster line comprising a. The method of claim 4, wherein And the device isolation layer has a booster line, which is an STI formed by a shallow trench isolation process. The method of claim 4, wherein And the booster line has a booster line forming capacitance between active regions between the device isolation layers and the word line pattern. A plurality of memory cell transistors arranged in rows and columns and electrically erased and programmed, a plurality of word lines extending in the row direction, a plurality of bit lines extending in the column direction, and formed between the bit lines A program method of a NAND flash memo device having booster lines, Selecting a word line and a bit line corresponding to the memory cell transistor to be programmed; Supplying a program voltage to the selected word line and plotting the unselected word lines; And A method of programming a NAND flash memory device having a booster line comprising supplying a forbidden voltage to an unselected bit line. The method of claim 7, wherein And a channel line of the memory cell transistor to be programmed has a booster line which is relatively increased by the program voltage through the booster line.

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