US20070004227A1 - Semiconductor processing methods - Google Patents

Semiconductor processing methods Download PDF

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US20070004227A1
US20070004227A1 US11517742 US51774206A US2007004227A1 US 20070004227 A1 US20070004227 A1 US 20070004227A1 US 11517742 US11517742 US 11517742 US 51774206 A US51774206 A US 51774206A US 2007004227 A1 US2007004227 A1 US 2007004227A1
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exposed
portions
layer
material
method
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Weimin Li
John Li
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Weimin Li
Li John Q
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • H01L21/31608Deposition of SiO2
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • H01L21/31633Deposition of carbon doped silicon oxide, e.g. SiOC

Abstract

In one aspect, the invention encompasses a semiconductor processing method. A layer of material is formed over a semiconductive wafer substrate. Some portions of the layer are exposed to energy while other portions are not exposed. The exposure to energy alters physical properties of the exposed portions relative to the unexposed portions. After the portions are exposed, the exposed and unexposed portions of the layer are subjected to common conditions. The common conditions are effective to remove the material and comprise a rate of removal that is influenced by the altered physical properties of the layer. The common conditions remove either the exposed or unexposed portions faster than the other of the exposed and unexposed portions. After the selective removal of the exposed or unexposed portions, and while the other of the exposed and unexposed portions remains over the substrate, the wafer is cut into separated die. In another aspect, the invention encompasses another semiconductor processing method. A layer of (CH3)ySi(OH)4-y is formed over a substrate. Some portions of the layer are exposed to ultraviolet light while other portions are not exposed. The exposure to ultraviolet light converts the exposed portions to (CH3)xSiO2-x. After the exposure to ultraviolet light, the exposed and unexposed portions of the layer are subjected to hydrofluoric acid to selectively remove the (CH3)ySi(OH)4-y of the unexposed portions relative to the (CH3)xSiO2-x of the exposed portions.

Description

    TECHNICAL FIELD
  • The invention pertains to semiconductor processing methods, and particularly pertains to methods of removing some portions of a layer from over a semiconductive substrate, while leaving other portions of the layer remaining over the substrate.
  • BACKGROUND OF THE INVENTION
  • Modern semiconductor processing frequently involves photolithographic methods to pattern materials into very small structures, which are ultimately incorporated into a semiconductor circuit. An exemplary prior art method for forming small structures from a layer of material is as follows. First, the layer of material is provided over a semiconductive substrate. Subsequently, a layer of photoresist is provided over the layer of material. A photolithographic mask is then provided over the layer of photoresist and light is shined through the mask to expose portions of the layer of photoresist while leaving other portions unexposed. The photoresist typically comprises an unsaturated organic material, such as, for example, a material comprising one or more unsaturated carbon-containing rings. The exposed portions are rendered either more or less soluble in a solvent relative to the unexposed portions. If the exposed portions are rendered more soluble, the resist is referred to as a positive photoresist (as a positive image of a pattern from the photolithographic mask is transferred to the photoresist), and if the exposed portions are rendered less soluble, the photoresist is referred to as a negative photoresist (as a negative image of the pattern from the photolithographic mask is transferred to the photoresist). In any event, the photoresist is exposed to a solvent and either the exposed or unexposed portions are removed while leaving the other of the exposed or unexposed portions remaining over the layer of material. Such patterns the photoresist into a patterned mask overlaying the layer of material. The layer of material is then exposed to conditions which transfer a pattern from the patterned mask to the layer of material (i.e., which removes portions of the layer of material not covered by photoresist, while leaving the portions of the layer material that are covered by photoresist). Subsequently, the photoresist is removed and the substrate having the patterned layer of material thereon is subjected to subsequent processing steps to form an integrated circuit over the substrate.
  • Typically, the semiconductive substrate referred to above is in the form of a wafer and a plurality of semiconductor packages (i.e., individual integrated circuits) are simultaneously formed over the wafer. After the formation of the plurality of semiconductor packages is complete, the wafer is subjected to a die-cutting process to separate the individual integrated circuits from one another. In wafer fabrication processes employed to date, photoresist is entirely removed from a wafer prior to subjecting the wafer to a die-cutting process. Among the reasons for removal of the photoresist is that the photoresist is not a material suitable for incorporation into semiconductor circuits. It would be desirable to develop alternative methods for patterning structures during semiconductor circuit fabrication processes.
  • In an area of semiconductor processing considered to be unrelated to the above-described photolithographic processing methods, a recently developed technique for forming insulative materials is Flowfill™ Technology, which has been developed by Trikon Technology of Bristol, U.K. The process can be utilized for forming either silicon dioxide or methylsilicon oxide ((CH3)xSiO2-x), for example. The process for forming silicon dioxide is as follows. First, SiH4 and H2O2 are separately introduced into a chemical vapor deposition (CVD) chamber, such as a parallel plate reaction chamber. The reaction rate between SiH4 and H2O2 can be moderated by the introduction of nitrogen into the reaction chamber. A semiconductive wafer is provided within the chamber, and ideally maintained at a suitably low temperature, such, as 0° C., at an exemplary pressure of 1 Torr to achieve formation of a silanol-type structure of the formula Si(OH)x, which is predominantly Si(OH)4. The Si(OH)4 condenses onto the wafer surface. Although the reaction occurs in the gas phase, the deposited Si(OH)4 is in the form of a viscous liquid which flows to fill small gaps on the wafer surface. In applications where deposition thickness increases, surface tension drives the deposited layer flat, thus forming a planarized layer over the substrate.
  • The liquid Si(OH)4 is typically converted to a silicon dioxide structure by a two-step process. First, planarization of the liquid film is promoted by increasing the temperature to above 100° C., while maintaining the pressure of about 1 Torr, to result in solidification and formation of a polymer layer. Thereafter, the temperature is raised to above 400° C., while maintaining the pressure of greater than 1 Torr, to form SiO2. The processing above 400° C. also provides the advantage of driving undesired water from the resultant SiO2 layer.
  • The formation of methylsilicon oxide is accomplished similarly to that described above for forming silicon dioxide, with the exception that methylsilane ((CH3)xSiH4-z, wherein z is at least 1 and no greater than 4) is combined with the hydrogen peroxide to produce a methylsilanol, instead of combining the silane (SiH4) with the hydrogen peroxide to form silanol.
  • SUMMARY OF THE INVENTION
  • In one aspect, the invention encompasses a semiconductor processing method wherein a layer of material is formed over a semiconductive wafer substrate. Some portions of the layer are exposed to energy while other portions are not exposed. The exposure to energy alters physical properties of the exposed portions relative to the unexposed portions. After the portions are exposed, the exposed and unexposed portions of the layer are subjected to common conditions. The common conditions are effective to remove the material and comprise a rate of removal that is influenced by the altered physical properties of the layer. The common conditions remove either the exposed or unexposed portions faster than the other of the exposed and unexposed portions. After the selective removal of the exposed or unexposed portions, and while the other of the exposed and unexposed portions remains over the substrate, the wafer is cut into separated die.
  • In another aspect, the invention encompasses another semiconductor processing method. A layer of (CH3)ySi(OH)4-y is formed over a substrate, wherein y is greater than 0 and less than 4. Some portions of the layer are exposed to ultraviolet light while other portions are not exposed. The exposure to ultraviolet light converts the exposed portions to (CH3)xSiO2-x, wherein x is greater than 0 and less than 2. After the exposure to ultraviolet light, the exposed and unexposed portions of the layer are subjected to hydrofluoric acid to selectively remove the (CH3)ySi(OH)4-y of the unexposed portions relative to the (CH3)xSiO2-x of the exposed portions.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
  • FIG. 1 is a fragmentary, diagrammatic, cross-sectional view of a semiconductive wafer fragment at a first step of a processing method in accordance with the present invention.
  • FIG. 2 is a view of the FIG. 1 wafer fragment at a step subsequent to that of FIG. 1.
  • FIG. 3 is a view of the FIG. 1 wafer fragment at a step subsequent to that of FIG. 2 in accordance with a first embodiment processing method of the present invention.
  • FIG. 4 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 3.
  • FIG. 5 is a view of the FIG. 1 wafer fragment shown at a step is subsequent to that of FIG. 2, and in accordance with a second embodiment processing sequence of the present invention.
  • FIG. 6 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that of FIG. 5.
  • FIG. 7 is a top view of a semiconductive wafer, such as the wafer incorporating the fragment of FIG. 1, shown prior to subjecting the wafer to a die-cutting process.
  • FIG. 8 is a top view of portions of the FIG. 7 semiconductive wafer shown after the wafer is subjected to a die-cutting process.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).
  • The invention encompasses methods for utilizing energy to form patterned masking materials on a wafer. In particular aspects of the invention, the patterned masking materials are retained on a wafer after a die-cutting process. In other particular aspects of the invention, the patterned masking materials comprise silicon. The invention is described with reference to a preferred embodiment in FIGS. 1-8.
  • Referring to FIG. 1, a semiconductive wafer fragment 10 is illustrated at a preliminary step of a processing sequence encompassed by the present invention. Wafer fragment 10 comprises a semiconductive substrate 12. Substrate 12 can comprise, for example, monocrystalline silicon lightly doped with a p-type conductivity enhancing dopant. To aid in interpretation of the claims that follow, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
  • A first layer of material 14 is formed over substrate 12, and a second layer of material 16 is formed over first layer 14. The material of first layer 14 can be either a conductive material or an insulative material, and is not particularly germane to the present invention. The material of second layer 16 has physical properties which can be altered by exposure to energy. The material of second layer 16 can comprise, for example, methylsilanol ((CH3)ySi(OH)4-y) or silanol (Si(OH)4, either of which can be formed by methods described above in the “Background” section of this disclosure. Both methylsilanol and silanol have physical properties which can be altered by exposure to, for example, electron beam energy, ultraviolet light or plasma. For instance, if portions of either silanol or methylsilanol are exposed to ultraviolet light, such portions will have a higher etch rate in hydrofluoric acid than will portions not exposed to the ultraviolet light. The exposure of methylsilanol to ultraviolet light converts it to the insulative material (CH3)xSiO2-x, and exposure of silanol to ultraviolet light converts it silicon dioxide.
  • Referring to FIG. 2, an energy source 18 is provided over wafer fragment 10, and a patterned photolithographic mask 20 is provided between source 18 and second layer 16. Mask 20 comprises orifices 22 extending therethrough. In operation, energy 24 is emitted from source 18 and toward mask 20. In the illustrated embodiment, the energy is shown as light waves which can comprise, for example, wavelengths corresponding to ultraviolet light. Mask 20 blocks some of the light waves, while other light waves penetrate through orifices 22 to reach layer 16. Layer 16 is thus divided into portions 30 which are exposed to the radiation from source 18 and portions 32 which are shielded by mask 20 and not exposed to radiation 24. The exposure of layer 16 to radiation 24 alters physical properties of the material of layer 16 within exposed regions 30 relative to physical properties of the material in unexposed portions 32.
  • After the exposure to radiation 24, the exposed portions 30 and unexposed portions 32 of layer 16 are exposed to common conditions which are effective to remove the material of layer 16. Further, the common conditions comprise a rate of removal of the material of layer 16 that is influenced by physical properties altered by exposure to radiation 24. Accordingly, exposed portions 30 are removed at a different rate than unexposed portions 32. FIGS. 3 and 4 illustrate an embodiment wherein exposed portions 30 are removed at a slower rate than unexposed portions 32, and FIGS. 5 and 6 illustrate an embodiment wherein the exposed portions are removed at a faster rate than the unexposed portions.
  • Referring first to the embodiment of FIGS. 3 and 4, and specifically referring to FIG. 3, substrate 10 is illustrated after exposure to conditions which remove exposed portions 32 (FIG. 2) more rapidly than unexposed portions 30, to leave only unexposed portions 30 remaining over first material 14. In an exemplary embodiment, the material of layer 16 can comprise either methylsilanol or silanol, the radiation 24 (FIG. 2) can comprise ultraviolet light, and the common conditions can comprise exposure to hydrofluoric acid. The ultraviolet light converts exposed material of layer 16 to either methylsilicon dioxide or silicon dioxide, and thus renders such exposed portions more resistant to hydrofluoric acid removal than unexposed portions comprising either methylsilanol or silanol. In the exemplary embodiment, it is found that the portions of a methylsilanol or silanol layer 16 exposed to ultraviolet light are removed by hydrofluoric acid at a rate that is at least about 5 times slower than portions of layer 16 not exposed to ultraviolet light. The portions not exposed to ultraviolet light can thus be selectively removed relative to the portions that have been exposed to ultraviolet light. For purposes of interpreting this disclosure and the claims that follow, a first material is “selectively removed” relative to another material if the first material is removed at a rate that is at least 3 times faster than a rate at which the other material is removed.
  • Referring to FIG. 4, a pattern is transferred from exposed portions 30 to underlying layer 14. Specifically, portions of layer 14 are removed by an etch. The conditions of the etch will vary depending on the material of layer 14, and can comprise conventional methods which will be recognized by persons of ordinary skill in the art for utilization with various materials of layer 14.
  • Referring to 5 and 6, processing similar to that of FIGS. 3 and 4 is illustrated with the exception that it is exposed portions 30 (FIG. 2) that have a faster rate of removal than unexposed portions 32 when layer 16 is subjected to conditions for removing the material of layer 16.
  • An advantage of the present invention relative to prior art methods described above in the “Background” section of this disclosure is that the photolithographically patterned layer 16 does not comprise photoresist. Accordingly, layer 16 can have attributes desired in structures formed over substrate 12. For instance, in the above-described exemplary embodiment of FIGS. 3 and 4, the remaining portions 30 of layer 16 comprise an insulative material (either silicon dioxide or methylsilicon oxide). Such insulative material can be utilized for separating conductive components of a semiconductor circuit from one another. In some applications, the methylsilicon oxide can be more preferred than the silicon dioxide, as methylsilicon oxide has a lower dielectric constant than silicon oxide. Accordingly, methylsilicon oxide can reduce parasitic capacitance between adjacent conductive components relative to silicon dioxide. The advantages of utilizing methylsilicon oxide can be generally realized from silicon oxides having the generic formula R—Si—O, wherein R is an organic group. R can comprise, for example, a hydrocarbon group.
  • FIGS. 7 and 8 illustrate subsequent processing which can occur after the processing of either FIGS. 3 and 4, or the processing of FIGS. 5 and 6. Specifically, FIG. 7 is a view of an entirety of a semiconductive wafer 50 which has been processed. The semiconductive wafer has a plurality of semiconductor structures (e.g., circuitry) formed thereover (not shown) and is subdivided into circuit packages 52 (only some of which are labeled). Imaginary dashed lines 53 are provided to show boundaries between adjacent semiconductor circuit packages 52. For reasons discussed above, structures comprised by packages 52 can comprise portions of photolithographically patterned layer 16 incorporated therein.
  • Referring to FIG. 8, wafer fragment 50 (FIG. 7) is illustrated after being subjected to a die-cutting process, wherein the wafer has been cut into separated die corresponding to packages 52.
  • In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

Claims (12)

  1. 1. A semiconductor processing method, comprising:
    forming a layer of material over a semiconductive wafer substrate;
    exposing some portions of the layer to energy while leaving other portions unexposed, the exposing altering physical properties of the exposed portions of material relative to the unexposed portions of material;
    after the exposing, subjecting the exposed and unexposed portions of the layer to common conditions, the common conditions being effective to remove the material and comprising a rate of removal that is influenced by the altered physical properties of the layer, the common conditions removing either the exposed or unexposed portions faster than the other of the exposed and unexposed portions; and
    after the selective removal of the exposed or unexposed portions, and while the other of the exposed and unexposed portions remains over the substrate, cutting the wafer into separated die.
  2. 2. The method of claim 1 wherein the material comprises silicon.
  3. 3. The method of claim 1 wherein the material comprises carbon, silicon and oxygen.
  4. 4. The method of claim 1 wherein the material comprises silicon bound to a hydrocarbon group and bound to oxygen.
  5. 5. The method of claim 1 wherein the material comprises (CH3)ySi(OH)4-y, with y being greater than 0 and less than 4.
  6. 6. The method of claim 1 wherein the material comprises Si(OH)4.
  7. 7. The method of claim 1 wherein the energy is in the form of ultraviolet light.
  8. 8. The method of claim 1 wherein the energy is in the form of an electron beam.
  9. 9. The method of claim 1 wherein the energy is in the form of a plasma.
  10. 10-29. (canceled)
  11. 30. The method of claim 1 wherein the forming a layer comprises depositing a layer of material comprising (CH3)ySi(OH)4-y, as initially deposited, with y being greater than 0 and less than 4.
  12. 31. The method of claim 1 wherein the forming a layer comprises depositing a layer of material comprising Si(OH)4, as initially deposited.
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Citations (97)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4158717A (en) * 1977-02-14 1979-06-19 Varian Associates, Inc. Silicon nitride film and method of deposition
US4444617A (en) * 1983-01-06 1984-04-24 Rockwell International Corporation Reactive ion etching of molybdenum silicide and N+ polysilicon
US4523214A (en) * 1981-07-03 1985-06-11 Fuji Photo Film Co., Ltd. Solid state image pickup device utilizing microcrystalline and amorphous silicon
US4592129A (en) * 1985-04-01 1986-06-03 Motorola, Inc. Method of making an integral, multiple layer antireflection coating by hydrogen ion implantation
US4600671A (en) * 1983-09-12 1986-07-15 Canon Kabushiki Kaisha Photoconductive member having light receiving layer of A-(Si-Ge) and N
US4648904A (en) * 1986-02-14 1987-03-10 Scm Corporation Aqueous systems containing silanes for rendering masonry surfaces water repellant
US4695859A (en) * 1986-10-20 1987-09-22 Energy Conversion Devices, Inc. Thin film light emitting diode, photonic circuit employing said diode imager employing said circuits
US4755478A (en) * 1987-08-13 1988-07-05 International Business Machines Corporation Method of forming metal-strapped polysilicon gate electrode for FET device
US4764247A (en) * 1987-03-18 1988-08-16 Syn Labs, Inc. Silicon containing resists
US4805683A (en) * 1988-03-04 1989-02-21 International Business Machines Corporation Method for producing a plurality of layers of metallurgy
US4833096A (en) * 1988-01-19 1989-05-23 Atmel Corporation EEPROM fabrication process
US4910160A (en) * 1989-06-06 1990-03-20 National Semiconductor Corporation High voltage complementary NPN/PNP process
US4940509A (en) * 1988-03-25 1990-07-10 Texas Instruments, Incorporated Isotropic etchant for capped silicide processes
US4992306A (en) * 1990-02-01 1991-02-12 Air Products Abd Chemicals, Inc. Deposition of silicon dioxide and silicon oxynitride films using azidosilane sources
US5034348A (en) * 1990-08-16 1991-07-23 International Business Machines Corp. Process for forming refractory metal silicide layers of different thicknesses in an integrated circuit
US5036383A (en) * 1989-04-27 1991-07-30 Kabushiki Kaisha Toshiba Semiconductor device having an improved bonding pad
US5140390A (en) * 1990-02-16 1992-08-18 Hughes Aircraft Company High speed silicon-on-insulator device
US5219613A (en) * 1990-06-13 1993-06-15 Wacker-Chemitronic Gesellschaft Fur Elektronik-Grundstoffe Mbh Process for producing storage-stable surfaces of polished silicon wafers
US5234869A (en) * 1990-06-28 1993-08-10 Kabushiki Kaisha Toshiba Method of manufacturing silicon nitride film
US5276347A (en) * 1991-12-18 1994-01-04 Sgs-Thomson Microelectronics, Inc. Gate overlapping LDD structure
US5285017A (en) * 1991-12-31 1994-02-08 Intel Corporation Embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias
US5286661A (en) * 1992-08-26 1994-02-15 Motorola, Inc. Method of forming a bipolar transistor having an emitter overhang
US5302366A (en) * 1991-03-28 1994-04-12 Phillips Petroleum Company Production of silicon product containing both carbon and nitrogen
US5312768A (en) * 1993-03-09 1994-05-17 Micron Technology, Inc. Integrated process for fabricating raised, source/drain, short-channel transistors
US5314724A (en) * 1991-01-08 1994-05-24 Fujitsu Limited Process for forming silicon oxide film
US5340621A (en) * 1992-03-30 1994-08-23 Nippon Sheet Glass Co., Ltd. Plasma CVD method
US5405489A (en) * 1991-10-30 1995-04-11 Samsung Electronics Co., Ltd. Method for fabricating an interlayer-dielectric film of a semiconductor device by using a plasma treatment prior to reflow
US5413963A (en) * 1994-08-12 1995-05-09 United Microelectronics Corporation Method for depositing an insulating interlayer in a semiconductor metallurgy system
US5429987A (en) * 1993-01-25 1995-07-04 Sharp Microelectronics Technology, Inc. Method for profile control of selective metallization
US5439838A (en) * 1994-09-14 1995-08-08 United Microelectronics Corporation Method of thinning for EEPROM tunneling oxide device
US5441797A (en) * 1993-04-27 1995-08-15 International Business Machines Corporation Antireflective polyimide dielectric for photolithography
US5482894A (en) * 1994-08-23 1996-01-09 Texas Instruments Incorporated Method of fabricating a self-aligned contact using organic dielectric materials
US5498555A (en) * 1994-11-07 1996-03-12 United Microelectronics Corporation Method of making LDD with polysilicon and dielectric spacers
US5536857A (en) * 1994-07-05 1996-07-16 Ford Motor Company Single source volatile precursor for SiO2.TiO2 powders and films
US5541445A (en) * 1991-08-14 1996-07-30 Mitel Corporation High performance passivation for semiconductor devices
US5543654A (en) * 1992-01-28 1996-08-06 Thunderbird Technologies, Inc. Contoured-tub fermi-threshold field effect transistor and method of forming same
US5591566A (en) * 1991-12-30 1997-01-07 Sony Corporation Method of forming a resist pattern by using a silicon carbide anti-reflective layer
US5591494A (en) * 1993-09-24 1997-01-07 Applied Materials, Inc. Deposition of silicon nitrides by plasma-enhanced chemical vapor deposition
US5593741A (en) * 1992-11-30 1997-01-14 Nec Corporation Method and apparatus for forming silicon oxide film by chemical vapor deposition
US5600165A (en) * 1994-07-27 1997-02-04 Sony Corporation Semiconductor device with antireflection film
US5639687A (en) * 1993-07-06 1997-06-17 Motorola Inc. Method for forming an integrated circuit pattern on a semiconductor substrate using silicon-rich silicon nitride
US5641607A (en) * 1991-12-30 1997-06-24 Sony Corporation Anti-reflective layer used to form a semiconductor device
US5652187A (en) * 1991-10-30 1997-07-29 Samsung Electronics Co., Ltd. Method for fabricating doped interlayer-dielectric film of semiconductor device using a plasma treatment
US5656330A (en) * 1994-03-22 1997-08-12 Futaba Denshi Kogyo K.K. Resistive element having a resistivity which is thermally stable against heat treatment, and method and apparatus for producing same
US5656337A (en) * 1993-08-31 1997-08-12 Samsung Electronics Co., Ltd. Method of forming a dielectric layer
US5661093A (en) * 1996-09-12 1997-08-26 Applied Materials, Inc. Method for the stabilization of halogen-doped films through the use of multiple sealing layers
US5709741A (en) * 1995-02-28 1998-01-20 Dow Corning Toray Silicone Co., Ltd. Water repellent for application to glass and water-repellent glass
US5710067A (en) * 1995-06-07 1998-01-20 Advanced Micro Devices, Inc. Silicon oxime film
US5711987A (en) * 1996-10-04 1998-01-27 Dow Corning Corporation Electronic coatings
US5731242A (en) * 1993-10-15 1998-03-24 Intel Corporation Self-aligned contact process in semiconductor fabrication
US5741721A (en) * 1994-02-01 1998-04-21 Quality Microcircuits Corporation Method of forming capacitors and interconnect lines
US5744399A (en) * 1995-11-13 1998-04-28 Lsi Logic Corporation Process for forming low dielectric constant layers using fullerenes
US5747388A (en) * 1992-09-18 1998-05-05 Siemens Aktiengesellschaft Antireflection layer and process for lithographically structuring a layer
US5750442A (en) * 1995-09-25 1998-05-12 Micron Technology, Inc. Germanium as an antireflective coating and method of use
US5753320A (en) * 1985-09-26 1998-05-19 Canon Kabushiki Kaisha Process for forming deposited film
US5759755A (en) * 1993-08-08 1998-06-02 Samsung Electronics, Co., Ltd. Semiconductor substrate containing anti-reflective layer
US5759746A (en) * 1996-05-24 1998-06-02 Kabushiki Kaisha Toshiba Fabrication process using a thin resist
US5783493A (en) * 1997-01-27 1998-07-21 Taiwan Semiconductor Manufacturing Company Ltd. Method for reducing precipitate defects using a plasma treatment post BPSG etchback
US5786039A (en) * 1995-05-15 1998-07-28 France Telecom Process for electrical insulation in microelectronics, applicable in narrow cavities, by deposition of oxide in the viscous state and corresponding device
US5789819A (en) * 1994-05-20 1998-08-04 Texas Instruments Incorporated Low dielectric constant material for electronics applications
US5792688A (en) * 1996-11-06 1998-08-11 Vanguard International Semiconductor Corporation Method to increase the surface area of a storage node electrode, of an STC structure, for DRAM devices, via formation of polysilicon columns
US5796151A (en) * 1996-12-19 1998-08-18 Texas Instruments Incorporated Semiconductor stack having a dielectric sidewall for prevention of oxidation of tungsten in tungsten capped poly-silicon gate electrodes
US5858880A (en) * 1994-05-14 1999-01-12 Trikon Equipment Limited Method of treating a semi-conductor wafer
US5872035A (en) * 1996-06-29 1999-02-16 Hyundai Electronics Industries Co., Ltd. Method of forming a floating gate in a flash memory device
US5872385A (en) * 1994-05-02 1999-02-16 Motorola Inc. Conductive interconnect structure and method of formation
US5874367A (en) * 1992-07-04 1999-02-23 Trikon Technologies Limited Method of treating a semi-conductor wafer
US5883014A (en) * 1997-06-03 1999-03-16 United Microelectronics Corp. Method for treating via sidewalls with hydrogen plasma
US5883011A (en) * 1997-06-18 1999-03-16 Vlsi Technology, Inc. Method of removing an inorganic antireflective coating from a semiconductor substrate
US5933721A (en) * 1997-04-21 1999-08-03 Advanced Micro Devices, Inc. Method for fabricating differential threshold voltage transistor pair
US6017614A (en) * 1997-07-14 2000-01-25 Vanguard International Semiconductor Corporation Plasma-enhanced chemical vapor deposited SIO2 /SI3 N4 multilayer passivation layer for semiconductor applications
US6017779A (en) * 1994-06-15 2000-01-25 Seiko Epson Corporation Fabrication method for a thin film semiconductor device, the thin film semiconductor device itself, liquid crystal display, and electronic device
US6020243A (en) * 1997-07-24 2000-02-01 Texas Instruments Incorporated Zirconium and/or hafnium silicon-oxynitride gate dielectric
US6022404A (en) * 1995-01-12 2000-02-08 Degussa Aktiengesellschaft Surface-modified, pyrogenically produced mixed oxides, method of their production and use
US6040619A (en) * 1995-06-07 2000-03-21 Advanced Micro Devices Semiconductor device including antireflective etch stop layer
US6057217A (en) * 1996-07-25 2000-05-02 Nec Corporation Process for production of semiconductor device with foreign element introduced into silicon dioxide film
US6060765A (en) * 1998-01-05 2000-05-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and a method of manufacturing the same
US6060766A (en) * 1997-08-25 2000-05-09 Advanced Micro Devices, Inc. Protection of hydrogen sensitive regions in semiconductor devices from the positive charge associated with plasma deposited barriers or layers
US6071799A (en) * 1997-06-30 2000-06-06 Hyundai Electronics Industries Co., Ltd. Method of forming a contact of a semiconductor device
US6072227A (en) * 1998-02-11 2000-06-06 Applied Materials, Inc. Low power method of depositing a low k dielectric with organo silane
US6080529A (en) * 1997-12-12 2000-06-27 Applied Materials, Inc. Method of etching patterned layers useful as masking during subsequent etching or for damascene structures
US6083852A (en) * 1997-05-07 2000-07-04 Applied Materials, Inc. Method for applying films using reduced deposition rates
US6087064A (en) * 1998-09-03 2000-07-11 International Business Machines Corporation Silsesquioxane polymers, method of synthesis, photoresist composition, and multilayer lithographic method
US6087267A (en) * 1986-03-04 2000-07-11 Motorola, Inc. Process for forming an integrated circuit
US6184151B1 (en) * 1997-08-21 2001-02-06 International Business Machines Corporation Method for forming cornered images on a substrate and photomask formed thereby
US6184158B1 (en) * 1996-12-23 2001-02-06 Lam Research Corporation Inductively coupled plasma CVD
US6187694B1 (en) * 1997-11-10 2001-02-13 Intel Corporation Method of fabricating a feature in an integrated circuit using two edge definition layers and a spacer
US6200835B1 (en) * 1994-10-07 2001-03-13 Micron Technology, Inc. Methods of forming conductive polysilicon lines and bottom gated thin film transistors, and conductive polysilicon lines and thin film transistors
US6204168B1 (en) * 1998-02-02 2001-03-20 Applied Materials, Inc. Damascene structure fabricated using a layer of silicon-based photoresist material
US6208004B1 (en) * 1998-08-19 2001-03-27 Philips Semiconductor, Inc. Semiconductor device with high-temperature-stable gate electrode for sub-micron applications and fabrication thereof
US6209484B1 (en) * 1996-06-28 2001-04-03 Applied Materials, Inc. Method and apparatus for depositing an etch stop layer
US6218292B1 (en) * 1997-12-18 2001-04-17 Advanced Micro Devices, Inc. Dual layer bottom anti-reflective coating
US6225217B1 (en) * 1997-06-27 2001-05-01 Nec Corporation Method of manufacturing semiconductor device having multilayer wiring
US6238976B1 (en) * 1997-07-08 2001-05-29 Micron Technology, Inc. Method for forming high density flash memory
US6268282B1 (en) * 1998-09-03 2001-07-31 Micron Technology, Inc. Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks
US6274292B1 (en) * 1998-02-25 2001-08-14 Micron Technology, Inc. Semiconductor processing methods
US6281100B1 (en) * 1998-09-03 2001-08-28 Micron Technology, Inc. Semiconductor processing methods
US6373114B1 (en) * 1998-10-23 2002-04-16 Micron Technology, Inc. Barrier in gate stack for improved gate dielectric integrity

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2553314A (en) 1944-07-01 1951-05-15 Gen Electric Method of rendering materials water repellent
US4474975A (en) 1983-05-09 1984-10-02 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Process for producing tris (N-methylamino) methylsilane
US4702936A (en) 1984-09-20 1987-10-27 Applied Materials Japan, Inc. Gas-phase growth process
JPS63157443A (en) 1986-12-22 1988-06-30 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
US5855880A (en) 1987-06-04 1999-01-05 Washington University Avirulent microbes and uses therefor
JPS63316476A (en) 1987-06-18 1988-12-23 Seiko Instr & Electronics Ltd Semiconductor device and manufacture thereof
US4863755A (en) 1987-10-16 1989-09-05 The Regents Of The University Of California Plasma enhanced chemical vapor deposition of thin films of silicon nitride from cyclic organosilicon nitrogen precursors
US5270267A (en) 1989-05-31 1993-12-14 Mitel Corporation Curing and passivation of spin on glasses by a plasma process wherein an external polarization field is applied to the substrate
US5061509A (en) 1989-08-25 1991-10-29 Kabushiki Kaisha Toshiba Method of manufacturing polyimide thin film and method of manufacturing liquid crystal orientation film of polyimide
JP2814009B2 (en) 1990-06-05 1998-10-22 三菱電機株式会社 A method of manufacturing a semiconductor device
US5356515A (en) 1990-10-19 1994-10-18 Tokyo Electron Limited Dry etching method
US5470772A (en) 1991-11-06 1995-11-28 Intel Corporation Silicidation method for contactless EPROM related devices
US5677111A (en) 1991-12-20 1997-10-14 Sony Corporation Process for production of micropattern utilizing antireflection film
US5670297A (en) 1991-12-30 1997-09-23 Sony Corporation Process for the formation of a metal pattern
JPH05263255A (en) 1992-03-19 1993-10-12 Hitachi Electron Eng Co Ltd Plasma cvd device
EP0572704B1 (en) 1992-06-05 2000-04-19 Alcan- Tech Co., Inc. Method for manufacturing a semiconductor device including method of reforming an insulating film formed by low temperature CVD
US5677015A (en) 1994-03-17 1997-10-14 Sony Corporation High dielectric constant material containing tantalum, process for forming high dielectric constant film containing tantalum, and semiconductor device using the same
KR100366910B1 (en) 1994-04-05 2003-03-04 소니 가부시끼 가이샤 A method of manufacturing a semiconductor device
US5461003A (en) 1994-05-27 1995-10-24 Texas Instruments Incorporated Multilevel interconnect structure with air gaps formed between metal leads
US5554567A (en) 1994-09-01 1996-09-10 Taiwan Semiconductor Manufacturing Company Ltd. Method for improving adhesion to a spin-on-glass
US5962581A (en) * 1995-04-28 1999-10-05 Kabushiki Kaisha Toshiba Silicone polymer composition, method of forming a pattern and method of forming an insulating film
JP3061255B2 (en) 1995-08-18 2000-07-10 キヤノン販売株式会社 Film formation method
US5948482A (en) 1995-09-19 1999-09-07 University Of New Mexico Ambient pressure process for preparing aerogel thin films reliquified sols useful in preparing aerogel thin films
US5968324A (en) 1995-12-05 1999-10-19 Applied Materials, Inc. Method and apparatus for depositing antireflective coating
EP0793271A3 (en) 1996-02-22 1998-12-02 Matsushita Electric Industrial Co., Ltd. Semiconductor device having a metal silicide film and method of fabricating the same
US5838052A (en) 1996-03-07 1998-11-17 Micron Technology, Inc. Reducing reflectivity on a semiconductor wafer by annealing titanium and aluminum
US5923999A (en) 1996-10-29 1999-07-13 International Business Machines Corporation Method of controlling dopant diffusion and metal contamination in thin polycide gate conductor of mosfet device
US5807660A (en) 1997-02-03 1998-09-15 Taiwan Semiconductor Manufacturing Company Ltd. Avoid photoresist lifting by post-oxide-dep plasma treatment
JPH1116904A (en) 1997-06-26 1999-01-22 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
US5968611A (en) 1997-11-26 1999-10-19 The Research Foundation Of State University Of New York Silicon nitrogen-based films and method of making the same
US6118163A (en) 1998-02-04 2000-09-12 Advanced Micro Devices, Inc. Transistor with integrated poly/metal gate electrode
EP0942330A1 (en) * 1998-03-11 1999-09-15 Applied Materials, Inc. Process for depositing and developing a plasma polymerized organosilicon photoresist film
US6001741A (en) 1998-04-15 1999-12-14 Lucent Technologies Inc. Method for making field effect devices and capacitors with improved thin film dielectrics and resulting devices
US6159871A (en) 1998-05-29 2000-12-12 Dow Corning Corporation Method for producing hydrogenated silicon oxycarbide films having low dielectric constant
US5960289A (en) 1998-06-22 1999-09-28 Motorola, Inc. Method for making a dual-thickness gate oxide layer using a nitride/oxide composite region
US6156674A (en) 1998-11-25 2000-12-05 Micron Technology, Inc. Semiconductor processing methods of forming insulative materials
US6156485A (en) 1999-01-19 2000-12-05 Taiwan Semiconductor Manufacturing Company Ltd. Film scheme to solve high aspect ratio metal etch masking layer selectivity and improve photo I-line PR resolution capability in quarter-micron technology
US6028015A (en) 1999-03-29 2000-02-22 Lsi Logic Corporation Process for treating damaged surfaces of low dielectric constant organo silicon oxide insulation material to inhibit moisture absorption

Patent Citations (100)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4158717A (en) * 1977-02-14 1979-06-19 Varian Associates, Inc. Silicon nitride film and method of deposition
US4523214A (en) * 1981-07-03 1985-06-11 Fuji Photo Film Co., Ltd. Solid state image pickup device utilizing microcrystalline and amorphous silicon
US4444617A (en) * 1983-01-06 1984-04-24 Rockwell International Corporation Reactive ion etching of molybdenum silicide and N+ polysilicon
US4600671A (en) * 1983-09-12 1986-07-15 Canon Kabushiki Kaisha Photoconductive member having light receiving layer of A-(Si-Ge) and N
US4592129A (en) * 1985-04-01 1986-06-03 Motorola, Inc. Method of making an integral, multiple layer antireflection coating by hydrogen ion implantation
US5753320A (en) * 1985-09-26 1998-05-19 Canon Kabushiki Kaisha Process for forming deposited film
US4648904A (en) * 1986-02-14 1987-03-10 Scm Corporation Aqueous systems containing silanes for rendering masonry surfaces water repellant
US4648904B1 (en) * 1986-02-14 1988-12-06
US6087267A (en) * 1986-03-04 2000-07-11 Motorola, Inc. Process for forming an integrated circuit
US4695859A (en) * 1986-10-20 1987-09-22 Energy Conversion Devices, Inc. Thin film light emitting diode, photonic circuit employing said diode imager employing said circuits
US4764247A (en) * 1987-03-18 1988-08-16 Syn Labs, Inc. Silicon containing resists
US4755478A (en) * 1987-08-13 1988-07-05 International Business Machines Corporation Method of forming metal-strapped polysilicon gate electrode for FET device
US4833096A (en) * 1988-01-19 1989-05-23 Atmel Corporation EEPROM fabrication process
US4805683A (en) * 1988-03-04 1989-02-21 International Business Machines Corporation Method for producing a plurality of layers of metallurgy
US4940509A (en) * 1988-03-25 1990-07-10 Texas Instruments, Incorporated Isotropic etchant for capped silicide processes
US5036383A (en) * 1989-04-27 1991-07-30 Kabushiki Kaisha Toshiba Semiconductor device having an improved bonding pad
US4910160A (en) * 1989-06-06 1990-03-20 National Semiconductor Corporation High voltage complementary NPN/PNP process
US4992306A (en) * 1990-02-01 1991-02-12 Air Products Abd Chemicals, Inc. Deposition of silicon dioxide and silicon oxynitride films using azidosilane sources
US5140390A (en) * 1990-02-16 1992-08-18 Hughes Aircraft Company High speed silicon-on-insulator device
US5219613A (en) * 1990-06-13 1993-06-15 Wacker-Chemitronic Gesellschaft Fur Elektronik-Grundstoffe Mbh Process for producing storage-stable surfaces of polished silicon wafers
US5234869A (en) * 1990-06-28 1993-08-10 Kabushiki Kaisha Toshiba Method of manufacturing silicon nitride film
US5034348A (en) * 1990-08-16 1991-07-23 International Business Machines Corp. Process for forming refractory metal silicide layers of different thicknesses in an integrated circuit
US5314724A (en) * 1991-01-08 1994-05-24 Fujitsu Limited Process for forming silicon oxide film
US5302366A (en) * 1991-03-28 1994-04-12 Phillips Petroleum Company Production of silicon product containing both carbon and nitrogen
US5541445A (en) * 1991-08-14 1996-07-30 Mitel Corporation High performance passivation for semiconductor devices
US5652187A (en) * 1991-10-30 1997-07-29 Samsung Electronics Co., Ltd. Method for fabricating doped interlayer-dielectric film of semiconductor device using a plasma treatment
US5405489A (en) * 1991-10-30 1995-04-11 Samsung Electronics Co., Ltd. Method for fabricating an interlayer-dielectric film of a semiconductor device by using a plasma treatment prior to reflow
US5276347A (en) * 1991-12-18 1994-01-04 Sgs-Thomson Microelectronics, Inc. Gate overlapping LDD structure
US5641607A (en) * 1991-12-30 1997-06-24 Sony Corporation Anti-reflective layer used to form a semiconductor device
US5591566A (en) * 1991-12-30 1997-01-07 Sony Corporation Method of forming a resist pattern by using a silicon carbide anti-reflective layer
US5648202A (en) * 1991-12-30 1997-07-15 Sony Corporation Method of forming a photoresist pattern using an anti-reflective
US5285017A (en) * 1991-12-31 1994-02-08 Intel Corporation Embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias
US5543654A (en) * 1992-01-28 1996-08-06 Thunderbird Technologies, Inc. Contoured-tub fermi-threshold field effect transistor and method of forming same
US5340621A (en) * 1992-03-30 1994-08-23 Nippon Sheet Glass Co., Ltd. Plasma CVD method
US5874367A (en) * 1992-07-04 1999-02-23 Trikon Technologies Limited Method of treating a semi-conductor wafer
US5286661A (en) * 1992-08-26 1994-02-15 Motorola, Inc. Method of forming a bipolar transistor having an emitter overhang
US5747388A (en) * 1992-09-18 1998-05-05 Siemens Aktiengesellschaft Antireflection layer and process for lithographically structuring a layer
US5593741A (en) * 1992-11-30 1997-01-14 Nec Corporation Method and apparatus for forming silicon oxide film by chemical vapor deposition
US5429987A (en) * 1993-01-25 1995-07-04 Sharp Microelectronics Technology, Inc. Method for profile control of selective metallization
US5312768A (en) * 1993-03-09 1994-05-17 Micron Technology, Inc. Integrated process for fabricating raised, source/drain, short-channel transistors
US5441797A (en) * 1993-04-27 1995-08-15 International Business Machines Corporation Antireflective polyimide dielectric for photolithography
US5639687A (en) * 1993-07-06 1997-06-17 Motorola Inc. Method for forming an integrated circuit pattern on a semiconductor substrate using silicon-rich silicon nitride
US5759755A (en) * 1993-08-08 1998-06-02 Samsung Electronics, Co., Ltd. Semiconductor substrate containing anti-reflective layer
US5656337A (en) * 1993-08-31 1997-08-12 Samsung Electronics Co., Ltd. Method of forming a dielectric layer
US5591494A (en) * 1993-09-24 1997-01-07 Applied Materials, Inc. Deposition of silicon nitrides by plasma-enhanced chemical vapor deposition
US5731242A (en) * 1993-10-15 1998-03-24 Intel Corporation Self-aligned contact process in semiconductor fabrication
US5741721A (en) * 1994-02-01 1998-04-21 Quality Microcircuits Corporation Method of forming capacitors and interconnect lines
US5656330A (en) * 1994-03-22 1997-08-12 Futaba Denshi Kogyo K.K. Resistive element having a resistivity which is thermally stable against heat treatment, and method and apparatus for producing same
US5872385A (en) * 1994-05-02 1999-02-16 Motorola Inc. Conductive interconnect structure and method of formation
US5858880A (en) * 1994-05-14 1999-01-12 Trikon Equipment Limited Method of treating a semi-conductor wafer
US5789819A (en) * 1994-05-20 1998-08-04 Texas Instruments Incorporated Low dielectric constant material for electronics applications
US6017779A (en) * 1994-06-15 2000-01-25 Seiko Epson Corporation Fabrication method for a thin film semiconductor device, the thin film semiconductor device itself, liquid crystal display, and electronic device
US5536857A (en) * 1994-07-05 1996-07-16 Ford Motor Company Single source volatile precursor for SiO2.TiO2 powders and films
US5600165A (en) * 1994-07-27 1997-02-04 Sony Corporation Semiconductor device with antireflection film
US5413963A (en) * 1994-08-12 1995-05-09 United Microelectronics Corporation Method for depositing an insulating interlayer in a semiconductor metallurgy system
US5482894A (en) * 1994-08-23 1996-01-09 Texas Instruments Incorporated Method of fabricating a self-aligned contact using organic dielectric materials
US5439838A (en) * 1994-09-14 1995-08-08 United Microelectronics Corporation Method of thinning for EEPROM tunneling oxide device
US6200835B1 (en) * 1994-10-07 2001-03-13 Micron Technology, Inc. Methods of forming conductive polysilicon lines and bottom gated thin film transistors, and conductive polysilicon lines and thin film transistors
US5498555A (en) * 1994-11-07 1996-03-12 United Microelectronics Corporation Method of making LDD with polysilicon and dielectric spacers
US6022404A (en) * 1995-01-12 2000-02-08 Degussa Aktiengesellschaft Surface-modified, pyrogenically produced mixed oxides, method of their production and use
US5709741A (en) * 1995-02-28 1998-01-20 Dow Corning Toray Silicone Co., Ltd. Water repellent for application to glass and water-repellent glass
US5786039A (en) * 1995-05-15 1998-07-28 France Telecom Process for electrical insulation in microelectronics, applicable in narrow cavities, by deposition of oxide in the viscous state and corresponding device
US6040619A (en) * 1995-06-07 2000-03-21 Advanced Micro Devices Semiconductor device including antireflective etch stop layer
US5710067A (en) * 1995-06-07 1998-01-20 Advanced Micro Devices, Inc. Silicon oxime film
US5750442A (en) * 1995-09-25 1998-05-12 Micron Technology, Inc. Germanium as an antireflective coating and method of use
US5744399A (en) * 1995-11-13 1998-04-28 Lsi Logic Corporation Process for forming low dielectric constant layers using fullerenes
US5759746A (en) * 1996-05-24 1998-06-02 Kabushiki Kaisha Toshiba Fabrication process using a thin resist
US6209484B1 (en) * 1996-06-28 2001-04-03 Applied Materials, Inc. Method and apparatus for depositing an etch stop layer
US5872035A (en) * 1996-06-29 1999-02-16 Hyundai Electronics Industries Co., Ltd. Method of forming a floating gate in a flash memory device
US6057217A (en) * 1996-07-25 2000-05-02 Nec Corporation Process for production of semiconductor device with foreign element introduced into silicon dioxide film
US5661093A (en) * 1996-09-12 1997-08-26 Applied Materials, Inc. Method for the stabilization of halogen-doped films through the use of multiple sealing layers
US5711987A (en) * 1996-10-04 1998-01-27 Dow Corning Corporation Electronic coatings
US5792688A (en) * 1996-11-06 1998-08-11 Vanguard International Semiconductor Corporation Method to increase the surface area of a storage node electrode, of an STC structure, for DRAM devices, via formation of polysilicon columns
US5796151A (en) * 1996-12-19 1998-08-18 Texas Instruments Incorporated Semiconductor stack having a dielectric sidewall for prevention of oxidation of tungsten in tungsten capped poly-silicon gate electrodes
US6184158B1 (en) * 1996-12-23 2001-02-06 Lam Research Corporation Inductively coupled plasma CVD
US5783493A (en) * 1997-01-27 1998-07-21 Taiwan Semiconductor Manufacturing Company Ltd. Method for reducing precipitate defects using a plasma treatment post BPSG etchback
US5933721A (en) * 1997-04-21 1999-08-03 Advanced Micro Devices, Inc. Method for fabricating differential threshold voltage transistor pair
US6083852A (en) * 1997-05-07 2000-07-04 Applied Materials, Inc. Method for applying films using reduced deposition rates
US5883014A (en) * 1997-06-03 1999-03-16 United Microelectronics Corp. Method for treating via sidewalls with hydrogen plasma
US5883011A (en) * 1997-06-18 1999-03-16 Vlsi Technology, Inc. Method of removing an inorganic antireflective coating from a semiconductor substrate
US6225217B1 (en) * 1997-06-27 2001-05-01 Nec Corporation Method of manufacturing semiconductor device having multilayer wiring
US6071799A (en) * 1997-06-30 2000-06-06 Hyundai Electronics Industries Co., Ltd. Method of forming a contact of a semiconductor device
US6238976B1 (en) * 1997-07-08 2001-05-29 Micron Technology, Inc. Method for forming high density flash memory
US6017614A (en) * 1997-07-14 2000-01-25 Vanguard International Semiconductor Corporation Plasma-enhanced chemical vapor deposited SIO2 /SI3 N4 multilayer passivation layer for semiconductor applications
US6020243A (en) * 1997-07-24 2000-02-01 Texas Instruments Incorporated Zirconium and/or hafnium silicon-oxynitride gate dielectric
US6184151B1 (en) * 1997-08-21 2001-02-06 International Business Machines Corporation Method for forming cornered images on a substrate and photomask formed thereby
US6060766A (en) * 1997-08-25 2000-05-09 Advanced Micro Devices, Inc. Protection of hydrogen sensitive regions in semiconductor devices from the positive charge associated with plasma deposited barriers or layers
US6187694B1 (en) * 1997-11-10 2001-02-13 Intel Corporation Method of fabricating a feature in an integrated circuit using two edge definition layers and a spacer
US6080529A (en) * 1997-12-12 2000-06-27 Applied Materials, Inc. Method of etching patterned layers useful as masking during subsequent etching or for damascene structures
US6218292B1 (en) * 1997-12-18 2001-04-17 Advanced Micro Devices, Inc. Dual layer bottom anti-reflective coating
US6060765A (en) * 1998-01-05 2000-05-09 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and a method of manufacturing the same
US6204168B1 (en) * 1998-02-02 2001-03-20 Applied Materials, Inc. Damascene structure fabricated using a layer of silicon-based photoresist material
US6072227A (en) * 1998-02-11 2000-06-06 Applied Materials, Inc. Low power method of depositing a low k dielectric with organo silane
US6274292B1 (en) * 1998-02-25 2001-08-14 Micron Technology, Inc. Semiconductor processing methods
US6208004B1 (en) * 1998-08-19 2001-03-27 Philips Semiconductor, Inc. Semiconductor device with high-temperature-stable gate electrode for sub-micron applications and fabrication thereof
US6727173B2 (en) * 1998-09-03 2004-04-27 Micron Technology, Inc. Semiconductor processing methods of forming an utilizing antireflective material layers, and methods of forming transistor gate stacks
US6268282B1 (en) * 1998-09-03 2001-07-31 Micron Technology, Inc. Semiconductor processing methods of forming and utilizing antireflective material layers, and methods of forming transistor gate stacks
US6281100B1 (en) * 1998-09-03 2001-08-28 Micron Technology, Inc. Semiconductor processing methods
US6087064A (en) * 1998-09-03 2000-07-11 International Business Machines Corporation Silsesquioxane polymers, method of synthesis, photoresist composition, and multilayer lithographic method
US6373114B1 (en) * 1998-10-23 2002-04-16 Micron Technology, Inc. Barrier in gate stack for improved gate dielectric integrity

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