US20060152459A1 - Scan driver for selectively performing progressive scanning and interlaced scanning and a display using the same - Google Patents
Scan driver for selectively performing progressive scanning and interlaced scanning and a display using the same Download PDFInfo
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- US20060152459A1 US20060152459A1 US11/284,973 US28497305A US2006152459A1 US 20060152459 A1 US20060152459 A1 US 20060152459A1 US 28497305 A US28497305 A US 28497305A US 2006152459 A1 US2006152459 A1 US 2006152459A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0224—Details of interlacing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0272—Details of drivers for data electrodes, the drivers communicating data to the pixels by means of a current
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
- G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
- G09G3/325—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
Definitions
- the present invention relates to a scan driver for a flat panel display (FPD), and more particularly, to a scan driver that may selectively perform progressive scanning and interlaced scanning.
- FPD flat panel display
- a scan driver is an indispensable circuit for a FPD.
- the scan driver is used to is drive a plurality of pixels that are arranged in rows and columns. In order to drive the pixels, the scan driver enables a selected row of pixels to emit light or enables data to be input to selected pixels.
- formation of one image frame requires a vertical synchronous signal, which defines an image frame display period, and a horizontal synchronous signal, which drives each of a plurality of pixel lines forming the image frame. While the horizontal synchronous signal is activated, image data is input to pixels arranged in a line to which the horizontal synchronous signal is transmitted.
- pixels start to emit light when image data is input; however, in an active matrix (AM) display, after storing input image data, all pixels arranged in one line emit light during a predetermined time duration.
- PM passive matrix
- AM active matrix
- a scan signal In a liquid crystal display (LCD), an organic electroluminescent (EL) display, and a plasma display panel (PDP), the horizontal synchronous signal is typically referred to as a scan signal. Therefore, a signal that selects and activates lines will hereinafter be referred to as a scan signal.
- LCD liquid crystal display
- EL organic electroluminescent
- PDP plasma display panel
- a circuit that transmits the scan signal to a panel in which pixels are arranged is a scan driver. More specifically, the scan driver transmits the scan signal to respective lines of the panel. The selection and activation of lines via transmission of the scan signal may be performed according to a progressive scan method or an interlaced scan method.
- a scan signal is sequentially transmitted to the panel lines. That is, the scan signal is sequentially transmitted to each of a first line through a final line.
- a frame is displayed through two processes. Specifically, in a first process, a scan signal is sequentially transmitted to odd-numbered lines during an odd field period corresponding to half of a frame period. In a second process, a scan signal is sequentially transmitted to even-numbered lines during an even field period corresponding to the remaining half of the frame period.
- a conventional FPD utilizes either progressive scanning or interlaced scanning to display image data because the FPD does not include a scan driver that can selectively perform progressive scanning and interlaced scanning.
- the present invention therefore, provides a scan driver that can selectively perform progressive scanning and interlaced scanning.
- the present invention also provides an organic EL display that can selectively perform progressive scanning and interlaced scanning.
- the present invention also provides a scan driver that selectively performs progressive scanning and interlaced scanning using a mode selection unit.
- the present invention discloses a scan driver that selectively performs progressive scanning and interlaced scanning and that includes a shift register for receiving a start pulse and a clock signal and outputting data at intervals of a cycle of the clock signal, an odd line selection unit for receiving an output signal of an odd-numbered flip-flop of the shift register and an odd line control signal and performing a logical operation on the received signals to generate an odd scan signal, and an even line selection unit for receiving an output signal of an even-numbered flip-flop of the shift register and an even line control signal and performing a logical operation on the received signals to generate an even scan signal.
- the present invention also discloses a display including a pixel array having a plurality of pixels, a scan driver for transmitting a scan signal and an emission control signal to the pixel array and selectively performing progressive scanning and interlaced scanning, and a data driver for transmitting data to a pixel selected by the scan signal of the scan driver.
- the scan driver includes a shift register for receiving a start pulse and a clock signal and outputting data at intervals of a cycle of the clock signal, an odd line selection unit for receiving an output signal of an odd-numbered flip-flop of the shift register and an odd line control signal and performing a logical operation on the received signals to generate an odd scan signal, and an even line selection unit for receiving an output signal of an even-numbered flip-flop of the shift register and an even line control signal and performing a logical operation on the received signals to generate an even scan signal.
- the present invention also discloses a scan driver that selectively performs progressive scanning and interlaced scanning and that includes a shift register for receiving a start pulse and a clock signal and outputting data at intervals of half of a cycle of the clock signal, a mode selection unit for receiving an output signal of a flip-flop of the shift register and performing a logical operation on the output signal of the flip-flop in response to a mode selection signal, an odd line selection unit for selecting an output signal of an odd-numbered flip-flop or an output signal of the mode selection unit in response to an odd line control signal, and an even line selection unit for selecting an output signal of an even-numbered flip-flop or the output signal of the mode selection unit in response to an even line control signal.
- the present invention also discloses a scan driver that selectively performs progressive scanning and interlaced scanning and that includes a shift register including a plurality of flip-flops connected in series, wherein odd-numbered flip-flops sample an input signal and output the sampled signal on a rising edge of a clock signal and even-numbered flip-flops sample an input signal and output the sampled signal on a falling edge of the clock signal, a mode selection unit for performing a logical OR operation on output signals of adjacent flip-flops or masking the output signals of the flip-flops in response to a mode selection signal, an odd line selection unit for selecting an output signal of an odd-numbered flip-flop or an output signal of the mode selection unit in response to an odd line control signal, and an even line selection unit for selecting an output signal of an even-numbered flip-flop or the output signal of the mode selection unit in response to an even line control signal.
- a shift register including a plurality of flip-flops connected in series, wherein odd-numbered flip-flops sample an input signal and output the sampled
- FIG. 1 is a circuit diagram of a scan driver that performs progressive scanning and interlaced scanning according to an exemplary embodiment of the present invention.
- FIG. 2 is a circuit diagram of a flip-flop according to an exemplary embodiment of the present invention.
- FIG. 3 is a timing diagram showing the progressive scanning of the scan driver of FIG. 1 .
- FIG. 4A and FIG. 4B are timing diagrams showing interlaced scanning of the scan driver of FIG. 1 .
- FIG. 5A is a block diagram of an organic EL display including a scan driver according to another exemplary embodiment of the present invention.
- FIG. 5B is a circuit diagram of a pixel driving circuit of the organic EL display of FIG. 5A .
- FIG. 6A and FIG. 6B are timing diagrams showing the progressive scanning and interlaced scanning of the organic EL display of FIG. 5A .
- FIG. 7 is a circuit diagram of a scan driver according to still another exemplary embodiment of the present invention.
- FIG. 8 is a circuit diagram of a flip-flop of FIG. 7 .
- FIG. 9A and FIG. 9B are a circuit diagram and a truth table, respectively, of a mode selection circuit of FIG. 7 .
- FIG. 10 is a circuit diagram of a line selection circuit of FIG. 7 .
- FIG. 11A and FIG. 11B are timing diagrams showing the progressive scanning and interlaced scanning of the scan driver of FIG. 7 .
- FIG. 1 is a circuit diagram of a scan driver that selectively performs progressive scanning and interlaced scanning according to an exemplary embodiment of the present invention.
- the scan driver includes a shift register 100 , an odd line selection unit 120 , and an even line selection unit 140 .
- the shift register 100 includes flip-flops corresponding to the number of scan lines of a panel. Accordingly, when a panel includes m scan lines, the shift register 100 includes at least m flip-flops. A clock signal CLK and an inverted clock signal /CLK are input to each flip-flop. Each flip-flop transmits stored data to the next flip-flop per a clock cycle in synchronization with the input clock signal CLK.
- an output signal SR 1 of data stored in a flip-flop FF 1 through a start pulse VSP is delayed by one clock cycle and output as an output signal SR 2 of a flip-flop FF 2 . That is, output signals SR 1 , SR 2 , SR 3 , . . . , and SRm of flip-flops FF 1 , FF 2 , FF 3 , . . . , and FFm are delayed by one clock cycle and output as delayed signals.
- the odd line selection unit 120 includes a plurality of NAND gates.
- An odd line control signal ODD is input to the NAND gates of the odd line selection unit 120 .
- output signals SR 1 , SR 3 , . . . , and SRm- 1 of odd-numbered flip-flops are input to the NAND gates of the odd line selection unit 120 .
- a first NAND gate 121 receives the odd line control signal ODD and the output signal SR 1 of the flip-flop FF 1 and performs a logical operation on the received signals to generate a first scan signal SCAN[ 1 ].
- a third NAND gate 123 receives the odd line control signal ODD and the output signal SR 3 of the flip-flop FF 3 and performs a logical operation on the received signals to generate a third scan signal SCAN[ 3 ].
- the first NAND gate 121 to an (m ⁇ 1)th NAND gate 125 of the odd line selection unit 120 perform the same operation on the same principle as described above. Accordingly, as the odd line selection unit 120 operates to generate odd scan signals.
- the even line selection unit 140 also includes a plurality of NAND gates.
- An even line control signal EVEN is input to the NAND gates of the even line selection unit 140 .
- output signals SR 2 , SR 4 , . . . , and SRm of even-numbered flip-flops are input to the NAND gates of the even line selection unit 140 .
- a second NAND gate 142 receives the even line control signal EVEN and the output signal SR 2 of the flip-flop FF 2 and performs a logical operation on the received signals to generate a second scan signal SCAN[ 2 ].
- a fourth NAND gate 144 receives the even line control signal EVEN and the output signal SR 4 of the flip-flop FF 4 and performs a logical operation on the received signals to generate a fourth scan signal SCAN[ 4 ].
- the second NAND gate 142 to an mth NAND gate 146 of the even line selection unit 140 perform the same operation on the same principle as described above.
- the odd line control signal ODD is at a high level, and the odd-numbered NAND gates invert input signals.
- the first scan signal SCAN[ 1 ] is an inverted signal of the output signal SR 1 of the flip-flop FF 1
- the third scan signal SCAN[ 3 ] is an inverted signal of the output signal SR 3 of the flip-flop FF 3
- an (m ⁇ 1)th scan signal SCAN[m ⁇ 1] is an inverted signal of the output signal SRm ⁇ 1 of the flip-flop FFm ⁇ 1.
- the even line control signal EVEN is at a high level, and the even-numbered NAND gates invert input signals.
- the second scan signal SCAN[ 2 ] is an inverted signal of the output signal SR 2 of the flip-flop FF 2
- the fourth scan signal SCAN[ 4 ] is an inverted signal of the output signal SR 4 of the flip-flop FF 4
- an mth scan signal SCAN[m] is an inverted signal of the output signal SRm of the flip-flop FFm.
- the scan driver performs progressive scanning when both the odd line control signal ODD and the even line control signal EVEN are at a high level.
- the odd line control signal ODD is at a high level during an odd field period corresponding to half of a frame period. Accordingly, the odd-numbered NAND gates invert input signals during the odd field period.
- odd line control signal ODD is at a low level during an even field period corresponding to the other half of the frame period. Accordingly, the odd-numbered NAND gates perform a masking operation during the even field period, thereby outputting high-level signals irrespective of output signal levels of the odd-number flip-flops.
- the even line control signal EVEN is at a low level during the odd field period when the scan driver performs interlaced scanning. Accordingly, the even-numbered NAND gates output high-level signals during the odd field period. On the other hand, the even line control signal EVEN is at a high level during the even field period. Accordingly, the even-numbered NAND gates invert input signals during the even field period.
- the odd line selection unit 120 and the even line selection unit 140 are activated. But when the scan driver performs interlaced scanning, only the odd line selection unit 120 is activated during the odd field period, and only the even line selection unit 140 is activated during the even field is period.
- FIG. 2 is a circuit diagram of one of the flip-flops of FIG. 1 .
- the flip-flop includes a first latch 200 and a second latch 210 .
- the first latch 200 includes a first sampler 202 and a first holder 204 .
- the first sampler 202 samples an input signal in a low-level period of a clock signal CLK
- the first holder 204 holds an output signal of the first sampler 202 in a high-level period of the clock signal CLK.
- a signal which is input to the first sampler 202 during a low-level period of the clock signal CLK, is held in the first holder 204 for a high-level period of the clock signal CLK. Since the input signal has a lower frequency than the frequency of the clock signal CLK, the first latch 200 samples the input signal during a low-level period of the clock signal CLK and holds the sampled input signal during a high-level period thereof.
- the second latch 210 includes a second sampler 212 and a second holder 214 .
- the second sampler 212 samples an input signal in a high-level period of the clock signal CLK, and the second holder 214 holds an output signal of the second sampler 212 in a low-level period of the clock signal CLK.
- the first sampler 202 receives an input signal, inverts the input signal, and outputs the inverted signal to the first holder 204 . Since the first holder 204 operates at a high level, it does not hold the inverted signal during a low-level period of the clock signal CLK. Once the clock signal CLK makes a low-to-high transition, the first sampler 202 stops receiving the input signal, and the first holder 204 holds the inverted signal. Simultaneously, the second sampler 212 receives an input signal. An output signal of the first holder 204 , which is input to the second sampler 212 , is output via an inverter of the first holder 204 . But while the clock signal CLK is at a high level, the second holder 214 does not hold received data, and while the clock signal CLK is at a low level again, the second holder 214 holds the received data.
- the flip-flop of FIG. 2 stores data, which is input directly before a rising edge of the clock signal CLK, and outputs the data during one cycle of the clock signal CLK until a new sampling operation starts.
- FIG. 3 is a timing diagram showing progressive scanning of the scan driver of FIG. 1 .
- a start pulse VSP is input to the flip-flop FF 1 with the same frequency as a frame frequency and during a low-level period of a clock signal CLK.
- the flip-flop FF 1 samples the start pulse VSP before a rising edge of the clock signal CLK and outputs the sampled data.
- an output signal SR 1 of the flip-flop FF 1 is at a high level during a first cycle.
- the output signal SR 1 is input to the first NAND gate 121 and the flip-flop FF 2 . Since the odd line control signal ODD is at a high level, the first NAND gate 121 inverts the output signal SR 1 and outputs the inverted signal. Thus, a first scan signal SCAN[ 1 ] is at a low level during the first cycle.
- the output signal SR 1 is also input to the flip-flop FF 2 , delayed by one cycle, and then output as a delayed signal. That is, data, which is sampled directly before a rising edge of a second cycle of the clock signal CLK, is output on the rising edge of the second cycle thereof. Accordingly, the flip-flop FF 2 outputs an output signal SR 2 , which is delayed by one cycle as compared to the output signal SR 1 .
- the output signal SR 2 of the flip-flop FF 2 is input to the second NAND gate 142 and the flip-flop FF 3 . Since the even line control signal EVEN is at a high level, the second NAND gate 142 inverts the output signal SR 2 and outputs the inverted signal. Thus, a second scan signal SCAN[ 2 ] is at a low level during the second cycle.
- the flip-flop FF 3 receives the output signal SR 2 and outputs an output signal SR 3 , which is delayed by one cycle as compared to the output signal SR 2 .
- the third NAND gate 123 receives and inverts the output signal SR 3 and outputs a third scan signal SCAN[ 3 ], which is at a low level during a third cycle.
- all scan signals may be sequentially generated during one frame period as described above.
- FIG. 4A and FIG. 4B are timing diagrams showing interlaced scanning of the scan driver of FIG. 1 .
- Odd scan signals SCAN[ 1 , 3 , . . . ,m ⁇ 1] are activated during the odd field period
- even scan signals SCAN[ 2 , 4 , . . . , m] are activated during the even field period.
- the odd line control signal ODD is at a high level during the odd field period to generate the odd scan signals SCAN[ 1 , 3 , . . . ,m ⁇ 1].
- the even line control signal EVEN is at a high level during the even field period to generate the even scan signals SCAN[ 2 , 4 , . . . ,m].
- the output signals of the odd-numbered flip-flops are masked, and the output signals of the even-numbered flip-flops are inverted and output from the NAND gates of the even line selection unit 140 .
- the odd line control signal ODD remains at a low level during the even field period to mask the output signals of the odd-numbered flip-flops
- the even line control signal EVEN remains at a high level during the even field period to invert the output signals of the even-numbered flip-flops.
- a start pulse VSP is input to the flip-flop FF 1 with a frequency that is double the frame frequency.
- a clock frequency of FIG. 4A is about twice the clock frequency of FIG. 3 , which illustrates progressive scanning.
- the start pulse VSP has a high-level period corresponding to at least two clock cycles.
- the output signal of each flip-flop has a high-level period corresponding to two clock cycles.
- the output signal SR 1 output from the flip-flop FF 1 , the output signal SR 2 output from the flip-flop FF 2 , the output signal SR 3 output from the flip-flop FF 3 , . . . , and the output signal SRm output from the flip-flop FF 3 are generated through the same process as shown in FIG. 3 . Accordingly, the output signals SR 1 , SR 2 , SR 3 , . . . , SRm ⁇ 1, and SRm of the flip-flops have a high-level period that is delayed by one cycle. Also, since each output signal has a high-level period corresponding to two clock cycles, output signals of two sequential flip-flops have high-level periods that overlap for one clock cycle.
- n cycles of the clock signal CLK m output signals of the flip-flops are at a high level at intervals of one cycle. Also, during the remaining n+1 cycles of the clock signal CLK, the m output signals of the flip-flops are at a high level at intervals of one cycle.
- the odd line control signal ODD is at a high level. But considering a timing margin, such as a time delay due to a transmission line, during a logical operation on the output signal SR 1 of the flip-flop FF 1 , the odd line control signal ODD may be elevated to a high level half of a clock cycle earlier than the first cycle of the clock signal CLK.
- the NAND gates of the odd line selection unit 120 invert the output signals SR 1 , SR 3 , . . . , and SRm ⁇ 1 of the odd-numbered flip-flops and output the inverted signals.
- the even line control signal EVEN is at a low level during the odd field period. But considering a timing margin, the even line control signal EVEN may fall to a low level half of a clock cycle later than the first clock cycle of the clock signal CLK.
- the NAND gates of the even line selection unit 140 mask the output signals of the even numbered flip-flops. Accordingly, the even-numbered scan signals SCAN[ 2 , 4 , . . . ,m] become a high level.
- the odd line control signal ODD is at a low level
- the even line control signal EVEN is at a high level.
- the output signals of the odd-numbered flip-flops are masked, and the odd line scan signals SCAN[ 1 , 3 , . . . ,m ⁇ 1] remain at a high level.
- the even line selection unit 140 inverts the output signals SR 2 , SR 4 , . . . , and SRm of the even-numbered flip-flops and outputs the inverted signals. Accordingly, the even line scan signals SCAN[ 2 , 4 , . . . ,m] are at a low level during two clock cycles.
- the even field period may have one more clock cycle than the odd field period so that the output signal SRm of the final flip-flop is inverted and an intact signal can be transmitted to the mth scan line.
- FIG. 4B shows that the number of clock signals included in an odd field period may equal the number of clock signals included in an even field period. That is, the odd field period of one frame period may have n+1 clock cycles, and the even field period of the frame period may also have n+1 clock cycles.
- the output signal SRm of the mth flip-flop FFm has a high-level period during the odd field period and the even field period.
- the output signal SRm of the mth flip-flop FFm has a high-level period during two clock cycles included in the odd field period.
- FIG. 5A is a block diagram of an organic electroluminescent (EL) display including a scan driver according to another exemplary embodiment of the present invention
- FIG. 5B is a circuit diagram of a pixel driving circuit of the organic EL display shown in FIG. 5A .
- EL organic electroluminescent
- the organic EL display includes a scan driver 301 , a data driver 303 , and a pixel array 305 .
- the scan driver 301 selectively performs progressive scanning and interlaced scanning as shown in FIG. 1 .
- the scan driver 301 also applies scan signals via m scan lines and applies emission control signals via m emission control lines.
- the data driver 303 applies data to a line of the pixel array 305 , which is selected by an emission control signal and a scan signal.
- the applied data may be a voltage or current.
- the organic EL display may be a voltage-write type, and when the applied data is a current, the organic EL display may be a current-write type.
- FIG. 5A Although a current-write organic EL display is shown in FIG. 5A , it would be apparent to those skilled in the art that a voltage-write display can be used instead.
- the pixel array 305 includes a plurality of pixels 310 .
- a first scan signal SCAN[ 1 ] and a first emission control signal EMI[ 1 ] are applied to pixels 310 arranged in a first row
- a second scan signal SCAN[ 2 ] and a second emission control signal EMI[ 2 ] are applied to pixels 310 arranged in a second row. That is, at least one scan signal and at least one emission control signal are applied to pixels 310 arranged in one row that forms one horizontal line.
- FIG. 5B is a circuit diagram of a current-write pixel driving circuit of the organic EL display shown in FIG. 5A .
- the pixel driving circuit includes four transistors M 1 , M 2 , M 3 , and M 4 , a program capacitor Cst, and an organic light emitting diode OLED.
- a driving transistor M 1 supplies substantially the same current as the data current, which is sunk via a data line data[n], to an emission control transistor M 4 during an emission operation of a pixel.
- a gate of the driving transistor M 1 is electrically connected with a terminal of the program capacitor Cst and a switching transistor M 2 .
- the driving transistor M 1 is also electrically connected with a power supply voltage ELVdd and transistors M 3 and M 4 .
- the switching transistor M 2 is turned on in response to a scan signal SCAN[m], thereby forming a path between the data line data[n] and the program capacitor Cst. Also, the switching transistor M 2 applies a predetermined bias voltage to the gate of the driving transistor M 1 , thus forming a voltage Vgs of the driving transistor M 1 corresponding to the data current.
- the transistor M 3 is turned on in response to the scan signal SCAN[m] and supplies a current from the driving transistor M 1 to the data line data[n] during a data current program operation.
- the transistor M 4 is turned on in response to an emission control signal EMI[m] and supplies a current from the driving transistor M 1 to the organic light emitting diode OLED during an emission operation.
- the current-write pixel driving circuit stores a voltage Vgs corresponding to the data current in the program capacitor Cst and turns on the emission control transistor M 4 so that substantially the same current as the data current may be supplied to the organic light emitting diode OLED.
- the emission control transistor M 4 is turned off thereby interrupting the emission operation of the organic light emitting diode OLED.
- the transistors M 2 and M 3 are turned on in response to the low level scan signal SCAN[m]. While the transistors M 2 and M 3 are being turned on, when a data current Idata is sunk via the data line data[n], the power supply voltage ELVdd, the driving transistor M 1 , and the transistor M 3 form a current path. Also, when the data current Idata is sunk, the switching transistor M 2 operates in a triode region. That is, direct current is not substantially supplied to the program capacitor Cst and the gate of the driving transistor M 1 , but only a bias voltage for turning on the driving transistor M 1 is applied to the gate of the driving transistor M 1 .
- the driving transistor M 1 may operate in a saturation region in order to supply the data current Idata from the power supply voltage ELVdd to the data line data[n].
- K denotes a proportional constant
- Vgs denotes a voltage difference between the gate and source of the driving transistor M 1
- Vth denotes a threshold voltage of the driving transistor M 1 .
- the emission control transistor M 4 is turned on.
- the driving transistor M 1 operates in the saturation region, and the data current Idata corresponding to the voltage Vgs stored in the program capacitor Cst is supplied to the transistor M 4 .
- a current substantially equal to the data current Idata is supplied to the organic light emitting diode OLED through the emission control transistor M 4 , thus the organic light emitting diode OLED emits light with luminance corresponding to the data current Idata.
- the current-write pixel driving circuit may have various configurations.
- FIG. 6A and FIG. 6B are timing diagrams showing progressive scanning and interlaced scanning of the organic EL display shown in FIG. 5A .
- FIG. 6A is a timing diagram showing progressive scanning of the organic EL display shown in FIG. 5A .
- the organic EL display applies emission control signals EMI[ 1 , 2 , . . . ,m] to the pixel array 305 , thereby enabling the data driver 303 to perform a current-write operation.
- an emission control signal EMI[ 1 , 2 , . . . ,m] is time-synchronized with a scan signal SCAN[ 1 , 2 , . . . ,m]
- a pixel may consecutively perform a data current program operation and an emission operation. Therefore, the scan signal SCAN[ 1 , 2 , . . . ,m] and the emission control signal EMI[ 1 , 2 , . . .
- a low-level period of the scan signal SCAN[ 1 , 2 , . . . ,m] is shorter than a high-level period of the emission control signal EMI[ 1 , 2 , . . . ,m].
- the odd line control signal ODD and the even line control signal EVEN may be pulse trains.
- the odd line control signal ODD when the odd line control signal ODD is at a low level, the output signals SR 1 , SR 3 , . . . , and SRm ⁇ 1 of the odd-numbered flip-flops are masked, and the odd scan signals SCAN[ 1 , 3 , . . . ,m ⁇ 1] are at a high level.
- the even line control signal EVEN is at a low level
- the output signals SR 2 , SR 4 , . . . , and SRm of the even-numbered flip-flops are masked, and the even scan signals SCAN[ 2 , 4 , . . . ,m] are at a high level.
- the odd line control signal ODD when the odd line control signal ODD is a pulse train, its low-level period is reflected in the odd scan signals SCAN[ 1 , 3 , . . . ,m ⁇ 1].
- the odd scan signal SCAN[ 1 , 3 , . . . ,m ⁇ 1] becomes a high level. Accordingly, the odd scan signals SCAN[ 1 , 3 , . . . ,m ⁇ 1] of FIG. 6A have shorter low-level time intervals than the odd scan signals of FIG. 3 .
- the high-level period of the odd emission control signals EMI[ 1 , 3 , . . . ,m ⁇ 1] is longer than the low-level period of the odd scan signals.
- the odd emission control signals EMI[ 1 , 3 , . . . ,m ⁇ 1 have the substantially same waveform as the output signal of the odd-numbered flip-flops.
- the odd emission control signals EMI[ 1 , 3 , . . . ,m ⁇ 1] may be formed using the output signals of the odd-numbered flip-flops, or they may be formed using an additional waveform generating circuit according to another embodiment.
- the above-described waveform generation process is likewise applied to generate the even scan signals SCAN[ 2 , 4 , . . . ,m]. Accordingly, the first emission control signal EMI[ 1 ] and the first scan signal SCAN[ 1 ], the second emission control signal EMI[ 2 ] and the second scan signal SCAN[ 2 ], . . . , and the mth emission control signal EMI[m] and the m-th scan signal SCAN[m] are sequentially generated in response to the odd line control signal ODD and the even line control signal EVEN.
- a pixel 310 to which it is applied does not emit light. Also, when the scan signal SCAN[ 1 , 2 , . . . ,m], which has a time interval with the emission control signal EMI[ 1 , 2 , . . . ,m], is input to the pixel 310 , the pixel 310 starts to perform a data current program operation. Once the scan signal SCAN[ 1 , 2 , . . .
- the pixel 310 elevates to a high level, the pixel 310 finishes the program operation, and the programmed pixel 310 may then start to emit light from a falling edge of the emission control signal EMI[ 1 , 2 , . . . ,m], which occurs a short time after the rising edge of the scan signal SCAN[ 1 , 2 , . . . ,m].
- EMI emission control signal
- FIG. 6B is a timing diagram showing interlaced scanning of the organic EL display shown in FIG. 5A .
- the timing diagram of FIG. 6B may be obtained by adding emission control signals EMI[ 1 , 2 , . . . ,m] to the timing diagram of FIG. 4B . Further, so that a low-level period of the scan signal SCAN[ 1 , 2 , . . . ,m] may be shorter than a high-level period of the emission control signal EMI[ 1 , 2 , . . . ,m], the odd line control signal ODD and the even line control signal EVEN have different waveforms from those shown in FIG. 4B .
- the odd line control signal ODD activates the odd scan signals SCAN[ 1 , 3 , . . . ,m ⁇ 1]. But since the odd line control signal ODD has a low-level period during each cycle of the clock signal CLK, output signals of odd-numbered flip-flops are masked during the low-level period. Accordingly, as described above with reference to FIG. 6A , a high-level period of the emission control signals is longer than a low-level period of the scan signals.
- an emission control signal has the substantially same waveform as the output signal of a flip-flop
- the output signals of the flip-flops can be used as the emission control signals.
- an additional circuit may be added to generate the emission control signals.
- the even line control signal EVEN activates even scan signals SCAN[ 2 , 4 , . . . ,m]. Since the even line control signal EVEN has a low-level period during each cycle of the clock signal CLK, the output signal of the even-numbered flip-flop is masked and output as a high-level signal during the low-level period.
- progressive scanning or interlaced scanning may be carried out using the odd line control signal ODD and the even line control signal EVEN.
- the scan driver may selectively perform progressive scanning and interlaced scanning in response to the odd line control signal ODD and the even line control signal EVEN. Consequently, a display including the scan driver, such as an organic EL display, an LCD, or a PDP, can selectively perform progressive scanning and interlaced scanning.
- FIG. 7 is a circuit diagram of a scan driver according to still another exemplary embodiment of the present invention.
- the scan driver includes a shift register 400 , a mode selection unit 420 , an odd line selection unit 440 , and an even line selection unit 460 .
- the shift register 400 includes a plurality of flip-flops, and there are more flip-flops than scan lines of a panel. Thus, when the panel includes m scan lines, the shift register 400 includes at least m+1 flip-flops. At least one of clock signal CLK and an inverted clock signal /CLK is input to each flip-flop.
- a first flip-flop FF 1 receives a start pulse VSP, and the clock signal CLK is input is to a clock input pin CK.
- the first flip-flop FF 1 samples data of the start pulse VSP and outputs the sampled data on a rising edge of the clock signal CLK.
- a second flip-flop FF 2 receives an output signal SR 1 of the first flip-flop FF 1 , and the inverted signal /CLK of the clock signal CLK is input to a clock input pin CK of the second flip-flop FF 2 .
- the second flip-flop FF 2 samples the output signal SR 1 and outputs the sampled signal on a falling edge of the clock signal CLK.
- odd-numbered flip-flops FF 1 , FF 3 , . . . , FFm ⁇ 1, and FFm+1 sample an input signal and output the sampled signal on a rising edge of the clock signal CLK and store data, which is input directly before a falling edge of the clock signal CLK, in a low-level period of the clock signal CLK.
- even-numbered flip-flops FF 2 , FF 4 , . . . , and FFm sample an input signal and output the sampled signal on a falling edge of the clock signal CLK and store data, which is input directly before a rising edge of the clock signal CLK, in a high-level period of the clock signal CLK.
- the mode selection unit 420 includes a plurality of mode selection circuits that are arranged in parallel. Each mode selection circuit receives output signals of two serial flip--flops and performs a logical operation on the received output signals in response to a mode selection signal MODE. Each mode selection circuit includes a NOR gate to receive the output signals of the two serial flip-flops and a NAND gate to receive the NOR gate's output signal and the mode selection signal MODE.
- the odd line selection unit 440 provides odd line scan signals SCAN[ 1 , 3 , . . . ,m ⁇ 1] to odd-numbered scan lines according to an operation determined by the mode selection unit 420 .
- the odd line selection unit 440 includes a plurality of line selection circuits that select the output signal of the flip-flop or an output signal of the mode selection circuit according to control of the odd line control signal ODD.
- the even line selection unit 460 provides even line scan signals SCAN[ 2 , 4 , . . . ,m] to even-numbered scan lines according to an operation determined by the mode selection unit 420 .
- the even line selection unit 460 includes a plurality of line selection circuits that select the output signal of the flip-flop or the output signal of the mode selection circuit according to control of the even line control signal EVEN.
- FIG. 8 is a circuit diagram of one of the flip-flops of FIG. 7 .
- the flip-flop includes a sampler 501 and a holder 503 .
- the sampler 501 samples an input signal SRk, or the start pulse VSP in the case of the first flip-flop FF 1 , during a high-level period of an input clock signal CLK, and the holder 503 outputs the input signal SRk during a high-level period of the clock signal CLK and holds the input signal SRk during a low-level period thereof.
- the sampler 501 may include an inverter that operates in response to the clock signal CLK. Thus, the sampler 501 samples the input signal SRk during a high-level period of the clock signal CLK. While the clock signal CLK remains at a high level, the input signal SRk is input to the flip-flop and output. Once the clock signal CLK falls to a low level, the sampler 501 interrupts the input of the input signal SRk, which is simultaneously held in the holder 503 . The holder 503 starts to hold the input signal SRk on a falling edge of the clock signal CLK.
- the flip-flop receives the input signal SRk and outputs the received input signal SRk during a high-level period of the clock signal CLK and holds the input signal SRk, which is input directly before a falling edge of the clock signal CLK, and outputs the held input signal SRk during a low-level period thereof.
- FIG. 9A and FIG. 9B are a circuit diagram and a truth table, respectively, of a mode selection circuit of FIG. 7 .
- the mode selection circuit includes a NOR gate 601 and a NAND gate 603 .
- the NOR gate 601 receives an output signal SRk of a kth flip-flop and an output signal SRk+1 of a (k+1)th flip-flop.
- the NAND gate 603 receives the output signal of the NOR gate 601 and the mode selection signal MODE and performs a NAND operation on the two input signals and then inputs the operation result out[k] to the line selection circuit.
- FIG. 9B shows a logic state of the mode selection signal MODE and a state of the operation result out[k] that is obtained from the NAND operation.
- the NAND gate 603 When the mode selection signal MODE is at a low level, the NAND gate 603 outputs a high-level signal irrespective of the output of the NOR gate 601 .
- the mode selection unit when the mode selection signal MODE is at a high level, the NAND gate 603 inverts the output of the NOR gate 601 . Accordingly, when the input signals SRk and SRk+1 are at a low level, the result out[k] is also a low level. In all other cases, the result out[k] is a high level. Hence, during progressive scanning (i.e. when the mode selection signal MODE is at a high level), the mode selection unit performs a logical OR operation on the output signals SRk and SRk+1.
- the mode selection circuit outputs a low-level signal only when the mode selection signal MODE is at a high level and the input signals SRk and SRk+1 are at a low level.
- FIG. 10 is a circuit diagram of a line selection circuit of FIG. 7 .
- the line selection circuit includes three NAND gates 701 , 705 , and 707 and an inverter 703 .
- the line selection circuit selects either the output signal SRk of the flip-flop or the output signal out[k] of the mode selection circuit in response to the odd line control signal ODD or the even line control signal EVEN. For example, when a high level odd line control signal ODD is input to the line selection circuit, the first NAND gate 701 inverts the output signal SRk of the flip-flop.
- the inverter 703 outputs a low-level signal to the second NAND gate 705
- the second NAND gate 705 outputs a high-level signal irrespective of the level of the output signal out[k] of the mode selection circuit. Since the high-level output signal of the second NAND gate 705 is input to the third NAND gate 707 , the third NAND gate 707 inverts the output signal of the first NAND gate 701 . Thus, an output signal SCAN[k] of the third NAND gate 707 becomes the output signal SRk of the flip-flop.
- the first NAND gate 701 when a low level odd line control signal ODD is input to the line selection circuit, the first NAND gate 701 outputs a high-level signal irrespective of the level of the output signal SRk of the flip-flop. Also, since the inverter 703 outputs a high-level signal to the second NAND gate 705 , the second NAND gate 705 inverts the output signal out[k] of the mode selection circuit and outputs the result to the third NAND gate 707 . Since the third NAND gate 707 receives the high-level output signal of the first NAND gate 701 , it inverts the output signal of the second NAND gate 705 . Accordingly, the output signal SCAN[k] of the third NAND gate 707 becomes the output signal out[k] of the mode selection circuit.
- the line selection circuit of FIG. 10 selects and outputs the output signal SRk of the flip-flop when the odd line control signal ODD or the even line control signal EVEN are at a high level, and selects and outputs the output signal out[k] of the mode selection circuit when the odd line control signal ODD or the even line control signal EVEN are at a low level.
- FIG. 11A and FIG. 11B are timing diagrams showing progressive scanning and interlaced scanning, respectively, of the scan driver of FIG. 7 .
- the scan driver sequentially activates m scan signals during one frame period.
- a start pulse VSP which has the same frequency as a vertical synchronous signal that defines an image frame display period, is input to an input terminal of the first flip-flop FF 1 .
- the first flip-flop FF 1 samples the input signal on a rising edge of the clock signal CLK.
- an output signal SR 1 of the first flip-flop FF 1 makes a high-to-low transition on a rising edge of a final cycle of the previous frame.
- the output signal SR 1 of the first flip-flop FF 1 makes a low-to-high transition. Accordingly, the output signal SR 1 remains at a low level from a high-level period of the final cycle of the previous frame to a low-level period of a first cycle of the present frame of the clock signal CLK.
- the output signal SR 1 of the first flip-flop FF 1 is input to the second flip-flop FF 2 , and an inverted clock signal /CLK is input to a clock input terminal CK of the second flip-flop FF 2 .
- the second flip-flop FF 2 samples the output signal SR 1 of the first flip-flop FF 1 on a falling edge of the clock signal CLK.
- an output signal SR 2 of the second flip-flop FF 2 makes a high-to-low transition on a falling edge of the first cycle of the clock signal CLK and then makes a low-to-high transition on a falling edge of a second cycle thereof.
- an output signal SR 3 of the third flip-flop FF 3 makes a high-to-low transition on a rising edge of a first cycle of the clock signal CLK and makes a low-to-high transition on a rising edge of a second cycle of the clock signal.
- an output signal SRm of the mth flip-flop FFm makes a high-to-low transition on a falling edge of an m/2th cycle of the clock signal CLK and makes a low-to-high transition on a falling edge of a first cycle of the next frame.
- an output signal SRm+1 of the (m+1)th flip-flop makes a high-to-low transition on a rising edge of the m/2th cycle of the clock signal CLK and makes a low-to-high transition on a rising edge of the first cycle of the next frame.
- the mode selection signal MODE is set to a high level.
- the mode selection circuits of the mode selection unit 420 output a low-level signal only when the output signals SRk and SRk+1 of sequential flip-flops are at a low level.
- the odd line control signal ODD and the even line control signal EVEN are set to a low level. Since the odd line control signal ODD is at a low level, the line selection circuit of the odd line selection unit 440 selects an output signal out[ 1 , 3 , . . . ,m+1] of an odd mode selection circuit and outputs the output signal out[ 1 , 3 , . . . ,m+1] to a corresponding scan line.
- the line selection circuit of the even line selection unit 460 selects an output signal out[ 2 , 4 , . . . ,m] of an even mode selection circuit and outputs the output signal out[ 2 , 4 , . . . ,m] to a corresponding scan line.
- the mode selection circuit outputs a low level signal only when the output signals of sequential flip-flops are at a low level. Therefore, a first scan signal SCAN[ 1 ] is at a low level only when both the output signal SR 1 of the first flip-flop FF 1 and the output signal SR 2 of the second flip-flop FF 2 are at a low level. Accordingly, the first scan signal SCAN[ 1 ] is activated during a low-level period of the first cycle of the clock signal CLK.
- a second scan signal SCAN[ 2 ] is at a low level only when both the output signal SR 2 of the second flip-flop FF 2 and an output signal SR 3 of the third flip-flop FF 3 are at a low level. Accordingly, the second scan signal SCAN[ 2 ] is activated during a high-level period of the first cycle of the clock signal CLK. Also, a third scan signal SCAN[ 3 ] is activated during a low-level period of the second cycle of the clock signal CLK.
- m scan signals may be sequentially activated during each frame period.
- the respective scan signals are sequentially transmitted with a phase difference of half of the cycle of the clock signal CLK to the scan lines during progressive scanning.
- the mode selection signal MODE is at a low level to perform interlaced scanning.
- the mode selection circuit of FIG. 9A outputs a high-level signal irrespective of the output signals of sequential flip-flops. Accordingly, all mode selection circuits output high level output signals out[ 1 , 2 , . . . ,m].
- output signals SR 2 , SR 4 , . . . , and SRm of even-numbered flip-flops are masked during an odd field period in which odd scan lines are scanned.
- output signals SR 1 , SR 3 , . . . , and SRm ⁇ 1 of odd-numbered flip-flops are masked during an even field period in which even scan lines are scanned.
- a low level even line control signal EVEN masks the output signals SR 2 , SR 4 , . . . , and SRm of the even-numbered flip-flops during the odd field period.
- the mode selection signal MODE is at a low level so that all output signals out[ 1 , 2 , . . . ,m] of the mode selection circuit are at a high level.
- the even line control signal EVEN is at a low level, the line selection circuit of the even line selection unit 460 selects the output signal out[ 2 , 4 , . . . ,m] of the even-numbered flip-flop. Accordingly, the even scan signal SCAN[ 2 , 4 , . . .
- the output signals SR 2 , SR 4 , . . . , and SRm of the even-numbered flip-flops are not selected by the line selection circuit. Rather, they are masked to a high level.
- the odd line control signal ODD is at a high level.
- the line selection circuit of the odd line selection unit 440 selects the output signals SR 1 , SR 3 , . . . , and SRm ⁇ 1 of the odd-numbered flip-flop in response to the high level odd line control signal ODD.
- the odd scan signals SCAN[ 1 , 3 , . . . ,m ⁇ 1] are sequentially output at a low level in response to the clock signal CLK.
- the first scan signal SCAN[ 1 ] is at a low level during a first cycle of the clock signal CLK
- the third scan signal SCAN[ 3 ] is at a low level during a second cycle thereof.
- the (m ⁇ 1)th scan signal SCAN[m ⁇ 1] is at a low level during an m/2th cycle of the clock signal CLK.
- a low level odd line control signal ODD masks the output signals SR 1 , SR 3 , . . . , and SRm ⁇ 1 of the odd-numbered flip-flops.
- the mode selection signal MODE is at a low level so that all output signals out[ 1 , 2 , . . . ,m] of the mode selection circuit are at a high level.
- the line selection circuit of the odd line selection unit 440 selects the output signal out[ 1 , 3 , . . . ,m ⁇ 1]. Accordingly, the odd scan signal SCAN[ 1 , 3 , . . .
- the output signals SR 1 , SR 3 , . . . , and SRm ⁇ 1 of the odd-numbered flip-flops are not selected by the line selection circuit. Rather, they are masked to a high level.
- the even line control signal EVEN is at a high level.
- the line selection circuit of the even line selection unit 460 selects the output signal SR 2 , SR 4 , . . . , and SRm of the even-numbered flip-flop in response to the high level even line control signal EVEN.
- the even scan signals SCAN[ 2 , 4 , . . . ,m] are sequentially output at a low level in response to the clock signal CLK.
- the second scan signal SCAN[ 2 ] is at a low level in a low-level period of an (m/2+2)th cycle of the clock signal CLK and in a high-level period of a (m/2+3)th cycle thereof
- the fourth scan signal SCAN[ 4 ] is at a low level in a low-level period of the (m/2+3)th cycle of the clock signal and in a high-level period of an (m/2+4)th cycle thereof.
- the mth scan signal SCAN[m] is at a low level in a low-level period of an (m+1)th cycle of the clock signal CLK and in a high-level period of an (m+2)th cycle thereof.
- the output signals SR 1 , SR 3 , . . . , and SRm ⁇ 1 of the odd-numbered flip-flops are masked to a high level, and the output signals SR 2 , SR 4 , . . . , and SRm of the even-numbered flip-flops are selected by the line selection circuit and output as scan signals.
- the odd scan signals SCAN[ 1 , 3 , . . . ,m ⁇ 1] are sequentially formed by a combination of the mode selection signal MODE and the odd line control signal ODD and transmitted to the respective odd scan lines during the odd field period.
- the even scan signal SCAN[ 2 , 4 , . . . ,m] is masked and output in response to the even line control signal EVEN.
- the even scan signal SCAN[ 2 , 4 , . . . ,m] has no data required for a scan operation and is set at a high level.
- the even scan signals SCAN[ 2 , 4 , . . . ,m] are sequentially formed by a combination of the mode selection signal MODE and the even line control signal EVEN and transmitted to the respective even scan lines.
- the odd scan signal SCAN[ 1 , 3 , . . . ,m ⁇ 1] is masked and output in response to the odd line control signal ODD.
- the odd scan signal SCAN[ 1 , 3 , . . . ,m ⁇ 1] has no data required for a scan operation and is set at a high level.
- progressive scanning and interlaced scanning can be selectively performed using the mode selection signal MODE, the odd line control signal ODD, and the even line control signal EVEN.
- progressive scanning and interlaced scanning can be selectively performed according to the levels of an odd line control signal and an even line control signal.
- an output signal of a shift register can be generated as a scan signal required for progressive scanning or interlaced scanning using the mode selection signal, the odd line control signal, and the even line control signal. Therefore, one scan driver may be used to selectively enable progressive scanning and interlaced scanning.
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Abstract
Description
- This application claims priority to and the benefit of Korean Patent Application No. 10-2004-0098255, filed Nov. 26, 2004, and Korean Patent Application No. 10-2004-0098267, filed Nov. 26, 2004, which are hereby incorporated by reference for all purposes as if fully set forth herein.
- 1. Field of the Invention
- The present invention relates to a scan driver for a flat panel display (FPD), and more particularly, to a scan driver that may selectively perform progressive scanning and interlaced scanning.
- 2. Discussion of the Background
- A scan driver is an indispensable circuit for a FPD. The scan driver is used to is drive a plurality of pixels that are arranged in rows and columns. In order to drive the pixels, the scan driver enables a selected row of pixels to emit light or enables data to be input to selected pixels.
- Generally, formation of one image frame requires a vertical synchronous signal, which defines an image frame display period, and a horizontal synchronous signal, which drives each of a plurality of pixel lines forming the image frame. While the horizontal synchronous signal is activated, image data is input to pixels arranged in a line to which the horizontal synchronous signal is transmitted.
- In a passive matrix (PM) display, pixels start to emit light when image data is input; however, in an active matrix (AM) display, after storing input image data, all pixels arranged in one line emit light during a predetermined time duration.
- In a liquid crystal display (LCD), an organic electroluminescent (EL) display, and a plasma display panel (PDP), the horizontal synchronous signal is typically referred to as a scan signal. Therefore, a signal that selects and activates lines will hereinafter be referred to as a scan signal.
- A circuit that transmits the scan signal to a panel in which pixels are arranged is a scan driver. More specifically, the scan driver transmits the scan signal to respective lines of the panel. The selection and activation of lines via transmission of the scan signal may be performed according to a progressive scan method or an interlaced scan method.
- In the progressive scan method, a scan signal is sequentially transmitted to the panel lines. That is, the scan signal is sequentially transmitted to each of a first line through a final line.
- In the interlaced scan method, a frame is displayed through two processes. Specifically, in a first process, a scan signal is sequentially transmitted to odd-numbered lines during an odd field period corresponding to half of a frame period. In a second process, a scan signal is sequentially transmitted to even-numbered lines during an even field period corresponding to the remaining half of the frame period.
- Accordingly, a conventional FPD utilizes either progressive scanning or interlaced scanning to display image data because the FPD does not include a scan driver that can selectively perform progressive scanning and interlaced scanning.
- The present invention, therefore, provides a scan driver that can selectively perform progressive scanning and interlaced scanning.
- The present invention also provides an organic EL display that can selectively perform progressive scanning and interlaced scanning.
- The present invention also provides a scan driver that selectively performs progressive scanning and interlaced scanning using a mode selection unit.
- Additional features of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention.
- The present invention discloses a scan driver that selectively performs progressive scanning and interlaced scanning and that includes a shift register for receiving a start pulse and a clock signal and outputting data at intervals of a cycle of the clock signal, an odd line selection unit for receiving an output signal of an odd-numbered flip-flop of the shift register and an odd line control signal and performing a logical operation on the received signals to generate an odd scan signal, and an even line selection unit for receiving an output signal of an even-numbered flip-flop of the shift register and an even line control signal and performing a logical operation on the received signals to generate an even scan signal.
- The present invention also discloses a display including a pixel array having a plurality of pixels, a scan driver for transmitting a scan signal and an emission control signal to the pixel array and selectively performing progressive scanning and interlaced scanning, and a data driver for transmitting data to a pixel selected by the scan signal of the scan driver. The scan driver includes a shift register for receiving a start pulse and a clock signal and outputting data at intervals of a cycle of the clock signal, an odd line selection unit for receiving an output signal of an odd-numbered flip-flop of the shift register and an odd line control signal and performing a logical operation on the received signals to generate an odd scan signal, and an even line selection unit for receiving an output signal of an even-numbered flip-flop of the shift register and an even line control signal and performing a logical operation on the received signals to generate an even scan signal.
- The present invention also discloses a scan driver that selectively performs progressive scanning and interlaced scanning and that includes a shift register for receiving a start pulse and a clock signal and outputting data at intervals of half of a cycle of the clock signal, a mode selection unit for receiving an output signal of a flip-flop of the shift register and performing a logical operation on the output signal of the flip-flop in response to a mode selection signal, an odd line selection unit for selecting an output signal of an odd-numbered flip-flop or an output signal of the mode selection unit in response to an odd line control signal, and an even line selection unit for selecting an output signal of an even-numbered flip-flop or the output signal of the mode selection unit in response to an even line control signal.
- The present invention also discloses a scan driver that selectively performs progressive scanning and interlaced scanning and that includes a shift register including a plurality of flip-flops connected in series, wherein odd-numbered flip-flops sample an input signal and output the sampled signal on a rising edge of a clock signal and even-numbered flip-flops sample an input signal and output the sampled signal on a falling edge of the clock signal, a mode selection unit for performing a logical OR operation on output signals of adjacent flip-flops or masking the output signals of the flip-flops in response to a mode selection signal, an odd line selection unit for selecting an output signal of an odd-numbered flip-flop or an output signal of the mode selection unit in response to an odd line control signal, and an even line selection unit for selecting an output signal of an even-numbered flip-flop or the output signal of the mode selection unit in response to an even line control signal.
- It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
- The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the principles of the invention.
-
FIG. 1 is a circuit diagram of a scan driver that performs progressive scanning and interlaced scanning according to an exemplary embodiment of the present invention. -
FIG. 2 is a circuit diagram of a flip-flop according to an exemplary embodiment of the present invention. -
FIG. 3 is a timing diagram showing the progressive scanning of the scan driver ofFIG. 1 . -
FIG. 4A andFIG. 4B are timing diagrams showing interlaced scanning of the scan driver ofFIG. 1 . -
FIG. 5A is a block diagram of an organic EL display including a scan driver according to another exemplary embodiment of the present invention. -
FIG. 5B is a circuit diagram of a pixel driving circuit of the organic EL display ofFIG. 5A . -
FIG. 6A andFIG. 6B are timing diagrams showing the progressive scanning and interlaced scanning of the organic EL display ofFIG. 5A . -
FIG. 7 is a circuit diagram of a scan driver according to still another exemplary embodiment of the present invention. -
FIG. 8 is a circuit diagram of a flip-flop ofFIG. 7 . -
FIG. 9A andFIG. 9B are a circuit diagram and a truth table, respectively, of a mode selection circuit ofFIG. 7 . -
FIG. 10 is a circuit diagram of a line selection circuit ofFIG. 7 . -
FIG. 11A andFIG. 11B are timing diagrams showing the progressive scanning and interlaced scanning of the scan driver ofFIG. 7 . - The invention is described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity.
-
FIG. 1 is a circuit diagram of a scan driver that selectively performs progressive scanning and interlaced scanning according to an exemplary embodiment of the present invention. - Referring to
FIG. 1 , the scan driver includes ashift register 100, an oddline selection unit 120, and an evenline selection unit 140. - The
shift register 100 includes flip-flops corresponding to the number of scan lines of a panel. Accordingly, when a panel includes m scan lines, theshift register 100 includes at least m flip-flops. A clock signal CLK and an inverted clock signal /CLK are input to each flip-flop. Each flip-flop transmits stored data to the next flip-flop per a clock cycle in synchronization with the input clock signal CLK. - Accordingly, an output signal SR1 of data stored in a flip-flop FF1 through a start pulse VSP is delayed by one clock cycle and output as an output signal SR2 of a flip-flop FF2. That is, output signals SR1, SR2, SR3, . . . , and SRm of flip-flops FF1, FF2, FF3, . . . , and FFm are delayed by one clock cycle and output as delayed signals.
- The odd
line selection unit 120 includes a plurality of NAND gates. An odd line control signal ODD is input to the NAND gates of the oddline selection unit 120. Also, output signals SR1, SR3, . . . , and SRm-1 of odd-numbered flip-flops are input to the NAND gates of the oddline selection unit 120. - More specifically, a
first NAND gate 121 receives the odd line control signal ODD and the output signal SR1 of the flip-flop FF1 and performs a logical operation on the received signals to generate a first scan signal SCAN[1]. Also, athird NAND gate 123 receives the odd line control signal ODD and the output signal SR3 of the flip-flop FF3 and performs a logical operation on the received signals to generate a third scan signal SCAN[3]. Thefirst NAND gate 121 to an (m−1)th NAND gate 125 of the oddline selection unit 120 perform the same operation on the same principle as described above. Accordingly, as the oddline selection unit 120 operates to generate odd scan signals. - The even
line selection unit 140 also includes a plurality of NAND gates. An even line control signal EVEN is input to the NAND gates of the evenline selection unit 140. Also, output signals SR2, SR4, . . . , and SRm of even-numbered flip-flops are input to the NAND gates of the evenline selection unit 140. - More specifically, a
second NAND gate 142 receives the even line control signal EVEN and the output signal SR2 of the flip-flop FF2 and performs a logical operation on the received signals to generate a second scan signal SCAN[2]. Also, afourth NAND gate 144 receives the even line control signal EVEN and the output signal SR4 of the flip-flop FF4 and performs a logical operation on the received signals to generate a fourth scan signal SCAN[4]. Thesecond NAND gate 142 to anmth NAND gate 146 of the evenline selection unit 140 perform the same operation on the same principle as described above. - When the scan driver performs progressive scanning, the odd line control signal ODD is at a high level, and the odd-numbered NAND gates invert input signals. Thus, the first scan signal SCAN[1] is an inverted signal of the output signal SR1 of the flip-flop FF1, the third scan signal SCAN[3] is an inverted signal of the output signal SR3 of the flip-flop FF3, and an (m−1)th scan signal SCAN[m−1] is an inverted signal of the output signal SRm−1 of the flip-flop FFm−1.
- Additionally, during progressive scanning, the even line control signal EVEN is at a high level, and the even-numbered NAND gates invert input signals. Thus, the second scan signal SCAN[2] is an inverted signal of the output signal SR2 of the flip-flop FF2, the fourth scan signal SCAN[4] is an inverted signal of the output signal SR4 of the flip-flop FF4, and an mth scan signal SCAN[m] is an inverted signal of the output signal SRm of the flip-flop FFm.
- Accordingly, the scan driver performs progressive scanning when both the odd line control signal ODD and the even line control signal EVEN are at a high level.
- On the other hand, when the scan driver performs interlaced scanning, the odd line control signal ODD is at a high level during an odd field period corresponding to half of a frame period. Accordingly, the odd-numbered NAND gates invert input signals during the odd field period.
- Further, the odd line control signal ODD is at a low level during an even field period corresponding to the other half of the frame period. Accordingly, the odd-numbered NAND gates perform a masking operation during the even field period, thereby outputting high-level signals irrespective of output signal levels of the odd-number flip-flops.
- Furthermore, the even line control signal EVEN is at a low level during the odd field period when the scan driver performs interlaced scanning. Accordingly, the even-numbered NAND gates output high-level signals during the odd field period. On the other hand, the even line control signal EVEN is at a high level during the even field period. Accordingly, the even-numbered NAND gates invert input signals during the even field period.
- Hence, when the scan driver of
FIG. 1 performs progressive scanning, the oddline selection unit 120 and the evenline selection unit 140 are activated. But when the scan driver performs interlaced scanning, only the oddline selection unit 120 is activated during the odd field period, and only the evenline selection unit 140 is activated during the even field is period. -
FIG. 2 is a circuit diagram of one of the flip-flops ofFIG. 1 . - Referring to
FIG. 2 , the flip-flop includes afirst latch 200 and asecond latch 210. - The
first latch 200 includes afirst sampler 202 and afirst holder 204. Thefirst sampler 202 samples an input signal in a low-level period of a clock signal CLK, and thefirst holder 204 holds an output signal of thefirst sampler 202 in a high-level period of the clock signal CLK. Hence, a signal, which is input to thefirst sampler 202 during a low-level period of the clock signal CLK, is held in thefirst holder 204 for a high-level period of the clock signal CLK. Since the input signal has a lower frequency than the frequency of the clock signal CLK, thefirst latch 200 samples the input signal during a low-level period of the clock signal CLK and holds the sampled input signal during a high-level period thereof. - The
second latch 210 includes asecond sampler 212 and asecond holder 214. Thesecond sampler 212 samples an input signal in a high-level period of the clock signal CLK, and thesecond holder 214 holds an output signal of thesecond sampler 212 in a low-level period of the clock signal CLK. - Operations of the flip-flop of
FIG. 2 will now be described. - While the clock signal CLK is at a low level, the
first sampler 202 receives an input signal, inverts the input signal, and outputs the inverted signal to thefirst holder 204. Since thefirst holder 204 operates at a high level, it does not hold the inverted signal during a low-level period of the clock signal CLK. Once the clock signal CLK makes a low-to-high transition, thefirst sampler 202 stops receiving the input signal, and thefirst holder 204 holds the inverted signal. Simultaneously, thesecond sampler 212 receives an input signal. An output signal of thefirst holder 204, which is input to thesecond sampler 212, is output via an inverter of thefirst holder 204. But while the clock signal CLK is at a high level, thesecond holder 214 does not hold received data, and while the clock signal CLK is at a low level again, thesecond holder 214 holds the received data. - Accordingly, the flip-flop of
FIG. 2 stores data, which is input directly before a rising edge of the clock signal CLK, and outputs the data during one cycle of the clock signal CLK until a new sampling operation starts. -
FIG. 3 is a timing diagram showing progressive scanning of the scan driver ofFIG. 1 . - The progressive scanning of the scan driver will now be described with reference to
FIG. 1 andFIG. 3 . - As described above with reference to
FIG. 1 , when the scan driver performs progressive scanning, as the NAND gates of the oddline selection unit 120 and of the evenline selection unit 140 invert output signals of the flip-flops because the odd line control signal ODD and the even line control signal EVEN are at a high level. - At the outset, a start pulse VSP is input to the flip-flop FF1 with the same frequency as a frame frequency and during a low-level period of a clock signal CLK. The flip-flop FF1 samples the start pulse VSP before a rising edge of the clock signal CLK and outputs the sampled data. Thus, an output signal SR1 of the flip-flop FF1 is at a high level during a first cycle.
- The output signal SR1 is input to the
first NAND gate 121 and the flip-flop FF2. Since the odd line control signal ODD is at a high level, thefirst NAND gate 121 inverts the output signal SR1 and outputs the inverted signal. Thus, a first scan signal SCAN[1] is at a low level during the first cycle. - The output signal SR1 is also input to the flip-flop FF2, delayed by one cycle, and then output as a delayed signal. That is, data, which is sampled directly before a rising edge of a second cycle of the clock signal CLK, is output on the rising edge of the second cycle thereof. Accordingly, the flip-flop FF2 outputs an output signal SR2, which is delayed by one cycle as compared to the output signal SR1.
- The output signal SR2 of the flip-flop FF2 is input to the
second NAND gate 142 and the flip-flop FF3. Since the even line control signal EVEN is at a high level, thesecond NAND gate 142 inverts the output signal SR2 and outputs the inverted signal. Thus, a second scan signal SCAN[2] is at a low level during the second cycle. - Thereafter, the flip-flop FF3 receives the output signal SR2 and outputs an output signal SR3, which is delayed by one cycle as compared to the output signal SR2. The
third NAND gate 123 receives and inverts the output signal SR3 and outputs a third scan signal SCAN[3], which is at a low level during a third cycle. - The above-described operation continues until the final flip-flop FFm outputs an output signal SRm and an mth scan signal SCAN[m] is generated.
- In other words, with progressive scanning, all scan signals may be sequentially generated during one frame period as described above.
-
FIG. 4A andFIG. 4B are timing diagrams showing interlaced scanning of the scan driver ofFIG. 1 . - The interlaced scanning of the scan driver will now be described with reference to
FIG. 4A andFIG. 1 . - As described above with reference to
FIG. 1 , during interlaced scanning, one frame period is divided into an odd field period and an even field period. Odd scan signals SCAN[1,3, . . . ,m−1] are activated during the odd field period, while even scan signals SCAN[2,4, . . . , m] are activated during the even field period. - The odd line control signal ODD is at a high level during the odd field period to generate the odd scan signals SCAN[1,3, . . . ,m−1]. Similarly, the even line control signal EVEN is at a high level during the even field period to generate the even scan signals SCAN[2,4, . . . ,m].
- During the interlaced scanning of
FIG. 4A , during the odd field period, which corresponds to about half of a frame period, output signals of odd-numbered flip-flops are inverted and output, and output signals of even-numbered flip-flops are masked. In order The odd line control signal ODD remains at a high level during the odd field period to invert the output signals of the odd-numbered flip-flops, and the even line control signal EVEN remains at a low level during the odd field period to mask the output signals of the even-numbered flip-flops. - On the other hand, during the even field period, which corresponds to the other half of the frame period, the output signals of the odd-numbered flip-flops are masked, and the output signals of the even-numbered flip-flops are inverted and output from the NAND gates of the even
line selection unit 140. The odd line control signal ODD remains at a low level during the even field period to mask the output signals of the odd-numbered flip-flops, and the even line control signal EVEN remains at a high level during the even field period to invert the output signals of the even-numbered flip-flops. - At the outset, a start pulse VSP is input to the flip-flop FF1 with a frequency that is double the frame frequency. Also, a clock frequency of
FIG. 4A is about twice the clock frequency ofFIG. 3 , which illustrates progressive scanning. Thus, inFIG. 4A , the start pulse VSP has a high-level period corresponding to at least two clock cycles. Accordingly, the output signal of each flip-flop has a high-level period corresponding to two clock cycles. - The output signal SR1 output from the flip-flop FF1, the output signal SR2 output from the flip-flop FF2, the output signal SR3 output from the flip-flop FF3, . . . , and the output signal SRm output from the flip-flop FF3 are generated through the same process as shown in
FIG. 3 . Accordingly, the output signals SR1, SR2, SR3, . . . , SRm−1, and SRm of the flip-flops have a high-level period that is delayed by one cycle. Also, since each output signal has a high-level period corresponding to two clock cycles, output signals of two sequential flip-flops have high-level periods that overlap for one clock cycle. - During n cycles of the clock signal CLK, m output signals of the flip-flops are at a high level at intervals of one cycle. Also, during the remaining n+1 cycles of the clock signal CLK, the m output signals of the flip-flops are at a high level at intervals of one cycle.
- During the odd field period, the odd line control signal ODD is at a high level. But considering a timing margin, such as a time delay due to a transmission line, during a logical operation on the output signal SR1 of the flip-flop FF1, the odd line control signal ODD may be elevated to a high level half of a clock cycle earlier than the first cycle of the clock signal CLK. In response to the odd line control signal ODD being at a high level, the NAND gates of the odd
line selection unit 120 invert the output signals SR1, SR3, . . . , and SRm−1 of the odd-numbered flip-flops and output the inverted signals. - Also, the even line control signal EVEN is at a low level during the odd field period. But considering a timing margin, the even line control signal EVEN may fall to a low level half of a clock cycle later than the first clock cycle of the clock signal CLK. In response to the even line control signal EVEN having a low level, the NAND gates of the even
line selection unit 140 mask the output signals of the even numbered flip-flops. Accordingly, the even-numbered scan signals SCAN[2,4, . . . ,m] become a high level. - During the even field period, which corresponds to the other half of the frame period, the odd line control signal ODD is at a low level, and the even line control signal EVEN is at a high level. Thus, the output signals of the odd-numbered flip-flops are masked, and the odd line scan signals SCAN[1,3, . . . ,m−1] remain at a high level. Further, the even
line selection unit 140 inverts the output signals SR2, SR4, . . . , and SRm of the even-numbered flip-flops and outputs the inverted signals. Accordingly, the even line scan signals SCAN[2,4, . . . ,m] are at a low level during two clock cycles. - Here, the even field period may have one more clock cycle than the odd field period so that the output signal SRm of the final flip-flop is inverted and an intact signal can be transmitted to the mth scan line.
- In comparison with
FIG. 4A ,FIG. 4B shows that the number of clock signals included in an odd field period may equal the number of clock signals included in an even field period. That is, the odd field period of one frame period may have n+1 clock cycles, and the even field period of the frame period may also have n+1 clock cycles. InFIG. 4A , the output signal SRm of the mth flip-flop FFm has a high-level period during the odd field period and the even field period. However, inFIG. 4B , the output signal SRm of the mth flip-flop FFm has a high-level period during two clock cycles included in the odd field period. - The generation of flip-flop output signals and the operations of the odd
line selection unit 120 and the evenline selection unit 140 are the same as described above with reference toFIG. 4A . Thus, a detailed description thereof will be omitted here. -
FIG. 5A is a block diagram of an organic electroluminescent (EL) display including a scan driver according to another exemplary embodiment of the present invention, andFIG. 5B is a circuit diagram of a pixel driving circuit of the organic EL display shown inFIG. 5A . - Referring to
FIG. 5A , the organic EL display includes ascan driver 301, adata driver 303, and apixel array 305. - The
scan driver 301 selectively performs progressive scanning and interlaced scanning as shown inFIG. 1 . Thescan driver 301 also applies scan signals via m scan lines and applies emission control signals via m emission control lines. - The
data driver 303 applies data to a line of thepixel array 305, which is selected by an emission control signal and a scan signal. The applied data may be a voltage or current. When the applied data is a voltage, the organic EL display may be a voltage-write type, and when the applied data is a current, the organic EL display may be a current-write type. - Although a current-write organic EL display is shown in
FIG. 5A , it would be apparent to those skilled in the art that a voltage-write display can be used instead. - The
pixel array 305 includes a plurality ofpixels 310. A first scan signal SCAN[1] and a first emission control signal EMI[1] are applied topixels 310 arranged in a first row, and a second scan signal SCAN[2] and a second emission control signal EMI[2] are applied topixels 310 arranged in a second row. That is, at least one scan signal and at least one emission control signal are applied topixels 310 arranged in one row that forms one horizontal line. -
FIG. 5B is a circuit diagram of a current-write pixel driving circuit of the organic EL display shown inFIG. 5A . - Referring to
FIG. 5B , the pixel driving circuit includes four transistors M1, M2, M3, and M4, a program capacitor Cst, and an organic light emitting diode OLED. - A driving transistor M1 supplies substantially the same current as the data current, which is sunk via a data line data[n], to an emission control transistor M4 during an emission operation of a pixel. To generate substantially the same current as the data current, a gate of the driving transistor M1 is electrically connected with a terminal of the program capacitor Cst and a switching transistor M2. The driving transistor M1 is also electrically connected with a power supply voltage ELVdd and transistors M3 and M4.
- The switching transistor M2 is turned on in response to a scan signal SCAN[m], thereby forming a path between the data line data[n] and the program capacitor Cst. Also, the switching transistor M2 applies a predetermined bias voltage to the gate of the driving transistor M1, thus forming a voltage Vgs of the driving transistor M1 corresponding to the data current.
- The transistor M3 is turned on in response to the scan signal SCAN[m] and supplies a current from the driving transistor M1 to the data line data[n] during a data current program operation.
- The transistor M4 is turned on in response to an emission control signal EMI[m] and supplies a current from the driving transistor M1 to the organic light emitting diode OLED during an emission operation.
- The current-write pixel driving circuit stores a voltage Vgs corresponding to the data current in the program capacitor Cst and turns on the emission control transistor M4 so that substantially the same current as the data current may be supplied to the organic light emitting diode OLED.
- Initially, once the emission control signal EMI[m] makes a low-to-high transition, the emission control transistor M4 is turned off thereby interrupting the emission operation of the organic light emitting diode OLED.
- While the emission control transistor M4 is being turned off, when the scan signal SCAN[m] makes a high-to-low transition, both the switching transistor M2 and the transistor M3 are turned on. In response to the low level scan signal SCAN[m], a pixel is selected and starts to program data.
- The transistors M2 and M3 are turned on in response to the low level scan signal SCAN[m]. While the transistors M2 and M3 are being turned on, when a data current Idata is sunk via the data line data[n], the power supply voltage ELVdd, the driving transistor M1, and the transistor M3 form a current path. Also, when the data current Idata is sunk, the switching transistor M2 operates in a triode region. That is, direct current is not substantially supplied to the program capacitor Cst and the gate of the driving transistor M1, but only a bias voltage for turning on the driving transistor M1 is applied to the gate of the driving transistor M1.
- Also, the driving transistor M1 may operate in a saturation region in order to supply the data current Idata from the power supply voltage ELVdd to the data line data[n]. When the driving transistor M1 operates in the saturation region, the data current Idata, which flows through the driving transistor M1, is given by:
Idata=K(Vgs−Vth)2 (1), - where K denotes a proportional constant, Vgs denotes a voltage difference between the gate and source of the driving transistor M1, and Vth denotes a threshold voltage of the driving transistor M1.
- When the scan signal SCAN[m] subsequently makes a low-to-high transition, both the transistors M2 and M3 are turned off and the program capacitor Cst maintains the voltage difference Vgs.
- Thereafter, when the emission control signal EMI[m] makes a high-to-low is transition, the emission control transistor M4 is turned on. As the emission control transistor M4 is turned on, the driving transistor M1 operates in the saturation region, and the data current Idata corresponding to the voltage Vgs stored in the program capacitor Cst is supplied to the transistor M4. A current substantially equal to the data current Idata is supplied to the organic light emitting diode OLED through the emission control transistor M4, thus the organic light emitting diode OLED emits light with luminance corresponding to the data current Idata.
- As described above, the current-write pixel driving circuit may have various configurations.
-
FIG. 6A andFIG. 6B are timing diagrams showing progressive scanning and interlaced scanning of the organic EL display shown inFIG. 5A . - Specifically,
FIG. 6A is a timing diagram showing progressive scanning of the organic EL display shown inFIG. 5A . - Referring to
FIG. 6A , the organic EL display applies emission control signals EMI[1,2, . . . ,m] to thepixel array 305, thereby enabling thedata driver 303 to perform a current-write operation. Also, when an emission control signal EMI[1,2, . . . ,m] is time-synchronized with a scan signal SCAN[1,2, . . . ,m], a pixel may consecutively perform a data current program operation and an emission operation. Therefore, the scan signal SCAN[1,2, . . . ,m] and the emission control signal EMI[1,2, . . . ,m] are applied to the pixel at predetermined time intervals. Accordingly, a low-level period of the scan signal SCAN[1,2, . . . ,m] is shorter than a high-level period of the emission control signal EMI[1,2, . . . ,m]. - In order for the scan signal SCAN[1,2, . . . ,m] to be shorter than the emission control signal EMI[1,2, . . . ,m], the odd line control signal ODD and the even line control signal EVEN may be pulse trains.
- As can be seen from
FIG. 1 , when the odd line control signal ODD is at a low level, the output signals SR1, SR3, . . . , and SRm−1 of the odd-numbered flip-flops are masked, and the odd scan signals SCAN[1,3, . . . ,m−1] are at a high level. - Similarly, when the even line control signal EVEN is at a low level, the output signals SR2, SR4, . . . , and SRm of the even-numbered flip-flops are masked, and the even scan signals SCAN[2,4, . . . ,m] are at a high level.
- Accordingly, when the odd line control signal ODD is a pulse train, its low-level period is reflected in the odd scan signals SCAN[1,3, . . . ,m−1]. In other words, while the output signal of an odd-numbered flip-flop is at a high level and the odd line control signal ODD is at a low level, the odd scan signal SCAN[1,3, . . . ,m−1] becomes a high level. Accordingly, the odd scan signals SCAN[1,3, . . . ,m−1] of
FIG. 6A have shorter low-level time intervals than the odd scan signals ofFIG. 3 . - Furthermore, as
FIG. 6A shows, the high-level period of the odd emission control signals EMI[1,3, . . . ,m−1] is longer than the low-level period of the odd scan signals. Here, the odd emission control signals EMI[1,3, . . . ,m−1 have the substantially same waveform as the output signal of the odd-numbered flip-flops. Hence, the odd emission control signals EMI[1,3, . . . ,m−1] may be formed using the output signals of the odd-numbered flip-flops, or they may be formed using an additional waveform generating circuit according to another embodiment. - The above-described waveform generation process is likewise applied to generate the even scan signals SCAN[2,4, . . . ,m]. Accordingly, the first emission control signal EMI[1] and the first scan signal SCAN[1], the second emission control signal EMI[2] and the second scan signal SCAN[2], . . . , and the mth emission control signal EMI[m] and the m-th scan signal SCAN[m] are sequentially generated in response to the odd line control signal ODD and the even line control signal EVEN.
- While the emission control signal EMI[1,2, . . . ,m] is at a high level, a
pixel 310 to which it is applied does not emit light. Also, when the scan signal SCAN[1,2, . . . ,m], which has a time interval with the emission control signal EMI[1,2, . . . ,m], is input to thepixel 310, thepixel 310 starts to perform a data current program operation. Once the scan signal SCAN[1,2, . . . ,m] elevates to a high level, thepixel 310 finishes the program operation, and the programmedpixel 310 may then start to emit light from a falling edge of the emission control signal EMI[1,2, . . . ,m], which occurs a short time after the rising edge of the scan signal SCAN[1,2, . . . ,m]. -
FIG. 6B is a timing diagram showing interlaced scanning of the organic EL display shown inFIG. 5A . - The timing diagram of
FIG. 6B may be obtained by adding emission control signals EMI[1,2, . . . ,m] to the timing diagram ofFIG. 4B . Further, so that a low-level period of the scan signal SCAN[1,2, . . . ,m] may be shorter than a high-level period of the emission control signal EMI[1,2, . . . ,m], the odd line control signal ODD and the even line control signal EVEN have different waveforms from those shown inFIG. 4B . - During an odd field period, the odd line control signal ODD activates the odd scan signals SCAN[1,3, . . . ,m−1]. But since the odd line control signal ODD has a low-level period during each cycle of the clock signal CLK, output signals of odd-numbered flip-flops are masked during the low-level period. Accordingly, as described above with reference to
FIG. 6A , a high-level period of the emission control signals is longer than a low-level period of the scan signals. - Since an emission control signal has the substantially same waveform as the output signal of a flip-flop, the output signals of the flip-flops can be used as the emission control signals. Alternatively, an additional circuit may be added to generate the emission control signals.
- During an even field period, the even line control signal EVEN activates even scan signals SCAN[2,4, . . . ,m]. Since the even line control signal EVEN has a low-level period during each cycle of the clock signal CLK, the output signal of the even-numbered flip-flop is masked and output as a high-level signal during the low-level period.
- As described above, it can be seen that progressive scanning or interlaced scanning may be carried out using the odd line control signal ODD and the even line control signal EVEN. In other words, the scan driver may selectively perform progressive scanning and interlaced scanning in response to the odd line control signal ODD and the even line control signal EVEN. Consequently, a display including the scan driver, such as an organic EL display, an LCD, or a PDP, can selectively perform progressive scanning and interlaced scanning.
-
FIG. 7 is a circuit diagram of a scan driver according to still another exemplary embodiment of the present invention. - Referring to
FIG. 7 , the scan driver includes ashift register 400, amode selection unit 420, an oddline selection unit 440, and an evenline selection unit 460. - The
shift register 400 includes a plurality of flip-flops, and there are more flip-flops than scan lines of a panel. Thus, when the panel includes m scan lines, theshift register 400 includes at least m+1 flip-flops. At least one of clock signal CLK and an inverted clock signal /CLK is input to each flip-flop. - A first flip-flop FF1 receives a start pulse VSP, and the clock signal CLK is input is to a clock input pin CK. The first flip-flop FF1 samples data of the start pulse VSP and outputs the sampled data on a rising edge of the clock signal CLK.
- A second flip-flop FF2 receives an output signal SR1 of the first flip-flop FF1, and the inverted signal /CLK of the clock signal CLK is input to a clock input pin CK of the second flip-flop FF2. The second flip-flop FF2 samples the output signal SR1 and outputs the sampled signal on a falling edge of the clock signal CLK.
- That is, odd-numbered flip-flops FF1, FF3, . . . , FFm−1, and FFm+1 sample an input signal and output the sampled signal on a rising edge of the clock signal CLK and store data, which is input directly before a falling edge of the clock signal CLK, in a low-level period of the clock signal CLK. Also, even-numbered flip-flops FF2, FF4, . . . , and FFm sample an input signal and output the sampled signal on a falling edge of the clock signal CLK and store data, which is input directly before a rising edge of the clock signal CLK, in a high-level period of the clock signal CLK.
- The
mode selection unit 420 includes a plurality of mode selection circuits that are arranged in parallel. Each mode selection circuit receives output signals of two serial flip--flops and performs a logical operation on the received output signals in response to a mode selection signal MODE. Each mode selection circuit includes a NOR gate to receive the output signals of the two serial flip-flops and a NAND gate to receive the NOR gate's output signal and the mode selection signal MODE. - The odd
line selection unit 440 provides odd line scan signals SCAN[1,3, . . . ,m−1] to odd-numbered scan lines according to an operation determined by themode selection unit 420. The oddline selection unit 440 includes a plurality of line selection circuits that select the output signal of the flip-flop or an output signal of the mode selection circuit according to control of the odd line control signal ODD. - The even
line selection unit 460 provides even line scan signals SCAN[2,4, . . . ,m] to even-numbered scan lines according to an operation determined by themode selection unit 420. The evenline selection unit 460 includes a plurality of line selection circuits that select the output signal of the flip-flop or the output signal of the mode selection circuit according to control of the even line control signal EVEN. -
FIG. 8 is a circuit diagram of one of the flip-flops ofFIG. 7 . - Referring to
FIG. 8 , the flip-flop includes asampler 501 and aholder 503. With an odd numbered flip-flop, thesampler 501 samples an input signal SRk, or the start pulse VSP in the case of the first flip-flop FF1, during a high-level period of an input clock signal CLK, and theholder 503 outputs the input signal SRk during a high-level period of the clock signal CLK and holds the input signal SRk during a low-level period thereof. - The
sampler 501 may include an inverter that operates in response to the clock signal CLK. Thus, thesampler 501 samples the input signal SRk during a high-level period of the clock signal CLK. While the clock signal CLK remains at a high level, the input signal SRk is input to the flip-flop and output. Once the clock signal CLK falls to a low level, thesampler 501 interrupts the input of the input signal SRk, which is simultaneously held in theholder 503. Theholder 503 starts to hold the input signal SRk on a falling edge of the clock signal CLK. Thus, with an odd numbered flip-flop, the flip-flop receives the input signal SRk and outputs the received input signal SRk during a high-level period of the clock signal CLK and holds the input signal SRk, which is input directly before a falling edge of the clock signal CLK, and outputs the held input signal SRk during a low-level period thereof. -
FIG. 9A andFIG. 9B are a circuit diagram and a truth table, respectively, of a mode selection circuit ofFIG. 7 . - Referring to
FIG. 9A , the mode selection circuit includes a NORgate 601 and aNAND gate 603. The NORgate 601 receives an output signal SRk of a kth flip-flop and an output signal SRk+1 of a (k+1)th flip-flop. - The
NAND gate 603 receives the output signal of the NORgate 601 and the mode selection signal MODE and performs a NAND operation on the two input signals and then inputs the operation result out[k] to the line selection circuit. -
FIG. 9B shows a logic state of the mode selection signal MODE and a state of the operation result out[k] that is obtained from the NAND operation. - When the mode selection signal MODE is at a low level, the
NAND gate 603 outputs a high-level signal irrespective of the output of the NORgate 601. - On the other hand, when the mode selection signal MODE is at a high level, the
NAND gate 603 inverts the output of the NORgate 601. Accordingly, when the input signals SRk and SRk+1 are at a low level, the result out[k] is also a low level. In all other cases, the result out[k] is a high level. Hence, during progressive scanning (i.e. when the mode selection signal MODE is at a high level), the mode selection unit performs a logical OR operation on the output signals SRk and SRk+1. - Accordingly, the mode selection circuit outputs a low-level signal only when the mode selection signal MODE is at a high level and the input signals SRk and SRk+1 are at a low level.
-
FIG. 10 is a circuit diagram of a line selection circuit ofFIG. 7 . - Referring to
FIG. 10 , the line selection circuit includes threeNAND gates inverter 703. The line selection circuit selects either the output signal SRk of the flip-flop or the output signal out[k] of the mode selection circuit in response to the odd line control signal ODD or the even line control signal EVEN. For example, when a high level odd line control signal ODD is input to the line selection circuit, thefirst NAND gate 701 inverts the output signal SRk of the flip-flop. Also, since theinverter 703 outputs a low-level signal to thesecond NAND gate 705, thesecond NAND gate 705 outputs a high-level signal irrespective of the level of the output signal out[k] of the mode selection circuit. Since the high-level output signal of thesecond NAND gate 705 is input to thethird NAND gate 707, thethird NAND gate 707 inverts the output signal of thefirst NAND gate 701. Thus, an output signal SCAN[k] of thethird NAND gate 707 becomes the output signal SRk of the flip-flop. - On the other hand, when a low level odd line control signal ODD is input to the line selection circuit, the
first NAND gate 701 outputs a high-level signal irrespective of the level of the output signal SRk of the flip-flop. Also, since theinverter 703 outputs a high-level signal to thesecond NAND gate 705, thesecond NAND gate 705 inverts the output signal out[k] of the mode selection circuit and outputs the result to thethird NAND gate 707. Since thethird NAND gate 707 receives the high-level output signal of thefirst NAND gate 701, it inverts the output signal of thesecond NAND gate 705. Accordingly, the output signal SCAN[k] of thethird NAND gate 707 becomes the output signal out[k] of the mode selection circuit. - In other words, the line selection circuit of
FIG. 10 selects and outputs the output signal SRk of the flip-flop when the odd line control signal ODD or the even line control signal EVEN are at a high level, and selects and outputs the output signal out[k] of the mode selection circuit when the odd line control signal ODD or the even line control signal EVEN are at a low level. -
FIG. 11A andFIG. 11B are timing diagrams showing progressive scanning and interlaced scanning, respectively, of the scan driver ofFIG. 7 . - Referring to
FIG. 7 andFIG. 11A , during progressive scanning, the scan driver sequentially activates m scan signals during one frame period. - Initially, a start pulse VSP, which has the same frequency as a vertical synchronous signal that defines an image frame display period, is input to an input terminal of the first flip-flop FF1. The first flip-flop FF1 samples the input signal on a rising edge of the clock signal CLK. Thus, an output signal SR1 of the first flip-flop FF1 makes a high-to-low transition on a rising edge of a final cycle of the previous frame. Also, since the start pulse VSP is at a high level when it is sampled on the rising edge of the clock signal CLK in the first cycle of the present frame, the output signal SR1 of the first flip-flop FF1 makes a low-to-high transition. Accordingly, the output signal SR1 remains at a low level from a high-level period of the final cycle of the previous frame to a low-level period of a first cycle of the present frame of the clock signal CLK.
- The output signal SR1 of the first flip-flop FF1 is input to the second flip-flop FF2, and an inverted clock signal /CLK is input to a clock input terminal CK of the second flip-flop FF2. Thus, the second flip-flop FF2 samples the output signal SR1 of the first flip-flop FF1 on a falling edge of the clock signal CLK. As a result, an output signal SR2 of the second flip-flop FF2 makes a high-to-low transition on a falling edge of the first cycle of the clock signal CLK and then makes a low-to-high transition on a falling edge of a second cycle thereof.
- In a similar process to the above-described process, an output signal SR3 of the third flip-flop FF3 makes a high-to-low transition on a rising edge of a first cycle of the clock signal CLK and makes a low-to-high transition on a rising edge of a second cycle of the clock signal.
- Also, an output signal SRm of the mth flip-flop FFm makes a high-to-low transition on a falling edge of an m/2th cycle of the clock signal CLK and makes a low-to-high transition on a falling edge of a first cycle of the next frame.
- Further, an output signal SRm+1 of the (m+1)th flip-flop makes a high-to-low transition on a rising edge of the m/2th cycle of the clock signal CLK and makes a low-to-high transition on a rising edge of the first cycle of the next frame.
- When the scan driver performs progressive scanning, the mode selection signal MODE is set to a high level. In this case, as shown in
FIG. 9A andFIG. 9B , the mode selection circuits of themode selection unit 420 output a low-level signal only when the output signals SRk and SRk+1 of sequential flip-flops are at a low level. - Also, the odd line control signal ODD and the even line control signal EVEN are set to a low level. Since the odd line control signal ODD is at a low level, the line selection circuit of the odd
line selection unit 440 selects an output signal out[1,3, . . . ,m+1] of an odd mode selection circuit and outputs the output signal out[1,3, . . . ,m+1] to a corresponding scan line. - Furthermore, since the even line control signal EVEN is at a low level, the line selection circuit of the even
line selection unit 460 selects an output signal out[2,4, . . . ,m] of an even mode selection circuit and outputs the output signal out[2,4, . . . ,m] to a corresponding scan line. - As described above, the mode selection circuit outputs a low level signal only when the output signals of sequential flip-flops are at a low level. Therefore, a first scan signal SCAN[1] is at a low level only when both the output signal SR1 of the first flip-flop FF1 and the output signal SR2 of the second flip-flop FF2 are at a low level. Accordingly, the first scan signal SCAN[1] is activated during a low-level period of the first cycle of the clock signal CLK.
- A second scan signal SCAN[2] is at a low level only when both the output signal SR2 of the second flip-flop FF2 and an output signal SR3 of the third flip-flop FF3 are at a low level. Accordingly, the second scan signal SCAN[2] is activated during a high-level period of the first cycle of the clock signal CLK. Also, a third scan signal SCAN[3] is activated during a low-level period of the second cycle of the clock signal CLK.
- In the above-described process, m scan signals may be sequentially activated during each frame period. Thus, the respective scan signals are sequentially transmitted with a phase difference of half of the cycle of the clock signal CLK to the scan lines during progressive scanning.
- Referring to
FIG. 11B , the mode selection signal MODE is at a low level to perform interlaced scanning. Thus, the mode selection circuit ofFIG. 9A outputs a high-level signal irrespective of the output signals of sequential flip-flops. Accordingly, all mode selection circuits output high level output signals out[1,2, . . . ,m]. - Also, output signals SR2, SR4, . . . , and SRm of even-numbered flip-flops are masked during an odd field period in which odd scan lines are scanned. Similarly, output signals SR1, SR3, . . . , and SRm−1 of odd-numbered flip-flops are masked during an even field period in which even scan lines are scanned.
- A low level even line control signal EVEN masks the output signals SR2, SR4, . . . , and SRm of the even-numbered flip-flops during the odd field period. During interlaced scanning, the mode selection signal MODE is at a low level so that all output signals out[1,2, . . . ,m] of the mode selection circuit are at a high level. Also, since the even line control signal EVEN is at a low level, the line selection circuit of the even
line selection unit 460 selects the output signal out[2,4, . . . ,m] of the even-numbered flip-flop. Accordingly, the even scan signal SCAN[2,4, . . . ,m] is a high-level signal. That is, in response to the low level even line control signal EVEN, the output signals SR2, SR4, . . . , and SRm of the even-numbered flip-flops are not selected by the line selection circuit. Rather, they are masked to a high level. - During the odd field period, the odd line control signal ODD is at a high level. The line selection circuit of the odd
line selection unit 440 selects the output signals SR1, SR3, . . . , and SRm−1 of the odd-numbered flip-flop in response to the high level odd line control signal ODD. Thus, the odd scan signals SCAN[1,3, . . . ,m−1] are sequentially output at a low level in response to the clock signal CLK. - In other words, the first scan signal SCAN[1] is at a low level during a first cycle of the clock signal CLK, and the third scan signal SCAN[3] is at a low level during a second cycle thereof. Also, the (m−1)th scan signal SCAN[m−1] is at a low level during an m/2th cycle of the clock signal CLK.
- During the even field period, a low level odd line control signal ODD masks the output signals SR1, SR3, . . . , and SRm−1 of the odd-numbered flip-flops. In the case of interlaced scanning, the mode selection signal MODE is at a low level so that all output signals out[1,2, . . . ,m] of the mode selection circuit are at a high level. Also, since the odd line control signal ODD is at a low level, the line selection circuit of the odd
line selection unit 440 selects the output signal out[1,3, . . . ,m−1]. Accordingly, the odd scan signal SCAN[1,3, . . . ,m−1] is a high-level signal. That is, in response to the low level odd line control signal ODD, the output signals SR1, SR3, . . . , and SRm−1 of the odd-numbered flip-flops are not selected by the line selection circuit. Rather, they are masked to a high level. - Furthermore, during the even field period, the even line control signal EVEN is at a high level. The line selection circuit of the even
line selection unit 460 selects the output signal SR2, SR4, . . . , and SRm of the even-numbered flip-flop in response to the high level even line control signal EVEN. Thus, the even scan signals SCAN[2,4, . . . ,m] are sequentially output at a low level in response to the clock signal CLK. - That is, the second scan signal SCAN[2] is at a low level in a low-level period of an (m/2+2)th cycle of the clock signal CLK and in a high-level period of a (m/2+3)th cycle thereof, and the fourth scan signal SCAN[4] is at a low level in a low-level period of the (m/2+3)th cycle of the clock signal and in a high-level period of an (m/2+4)th cycle thereof. Also, the mth scan signal SCAN[m] is at a low level in a low-level period of an (m+1)th cycle of the clock signal CLK and in a high-level period of an (m+2)th cycle thereof. Hence, during the even field period, the output signals SR1, SR3, . . . , and SRm−1 of the odd-numbered flip-flops are masked to a high level, and the output signals SR2, SR4, . . . , and SRm of the even-numbered flip-flops are selected by the line selection circuit and output as scan signals.
- In the above-described process, when the scan driver performs interlaced scanning, the odd scan signals SCAN[1,3, . . . ,m−1] are sequentially formed by a combination of the mode selection signal MODE and the odd line control signal ODD and transmitted to the respective odd scan lines during the odd field period.
- During the odd field period, the even scan signal SCAN[2,4, . . . ,m] is masked and output in response to the even line control signal EVEN. Hence, during the odd field period, the even scan signal SCAN[2,4, . . . ,m] has no data required for a scan operation and is set at a high level.
- On the other hand, during the even field period, the even scan signals SCAN[2,4, . . . ,m] are sequentially formed by a combination of the mode selection signal MODE and the even line control signal EVEN and transmitted to the respective even scan lines.
- Additionally, the odd scan signal SCAN[1,3, . . . ,m−1] is masked and output in response to the odd line control signal ODD. Hence, during the even field period, the odd scan signal SCAN[1,3, . . . ,m−1] has no data required for a scan operation and is set at a high level.
- As described above, progressive scanning and interlaced scanning can be selectively performed using the mode selection signal MODE, the odd line control signal ODD, and the even line control signal EVEN.
- According to exemplary embodiments of the present invention described above, progressive scanning and interlaced scanning can be selectively performed according to the levels of an odd line control signal and an even line control signal.
- Further, an output signal of a shift register can be generated as a scan signal required for progressive scanning or interlaced scanning using the mode selection signal, the odd line control signal, and the even line control signal. Therefore, one scan driver may be used to selectively enable progressive scanning and interlaced scanning.
- It will be apparent to those skilled in the art that various modifications and variation can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
Claims (44)
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5568163A (en) * | 1993-09-06 | 1996-10-22 | Nec Corporation | Apparatus for driving gate storage type liquid crystal, display panel capable of simultaneously driving two scan lines |
US5883609A (en) * | 1994-10-27 | 1999-03-16 | Nec Corporation | Active matrix type liquid crystal display with multi-media oriented drivers and driving method for same |
US6392629B1 (en) * | 1997-10-08 | 2002-05-21 | Fujitsu Limited | Drive circuit for liquid-crystal displays and liquid-crystal display including drive circuits |
US20020163493A1 (en) * | 1998-03-30 | 2002-11-07 | Sharp Kabushiki Kaisha | Liquid crystal display device and method of driving same |
US6784864B1 (en) * | 1999-07-12 | 2004-08-31 | Semiconductor Energy Laboratory Co., Ltd. | Digital driver and display device |
US20050046619A1 (en) * | 2003-08-28 | 2005-03-03 | Sharp Kabushiki Kaisha | Driving circuit for display device, and display device |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0270269A3 (en) * | 1986-12-05 | 1990-10-10 | Gec-Marconi Limited | Image scanning system |
US4922240A (en) * | 1987-12-29 | 1990-05-01 | North American Philips Corp. | Thin film active matrix and addressing circuitry therefor |
JPH02253232A (en) * | 1989-03-28 | 1990-10-12 | Toshiba Corp | Driving circuit for matrix display panel |
JPH05307166A (en) * | 1992-04-28 | 1993-11-19 | Seiko Instr Inc | Driving circuit of electrooptic device |
JP3202345B2 (en) * | 1992-09-09 | 2001-08-27 | 株式会社東芝 | Liquid crystal display |
JPH07199154A (en) * | 1993-12-29 | 1995-08-04 | Casio Comput Co Ltd | Liquid crystal display device |
JPH08234702A (en) * | 1995-02-28 | 1996-09-13 | Sony Corp | Display device |
JPH08234703A (en) * | 1995-02-28 | 1996-09-13 | Sony Corp | Display device |
JP2980042B2 (en) | 1996-11-27 | 1999-11-22 | 日本電気株式会社 | Scanning circuit |
JP3129271B2 (en) | 1998-01-14 | 2001-01-29 | 日本電気株式会社 | Gate driver circuit, driving method thereof, and active matrix liquid crystal display device |
JP2002333870A (en) * | 2000-10-31 | 2002-11-22 | Matsushita Electric Ind Co Ltd | Liquid crystal display device, el display device and drive method therefor and display pattern evaluation method of subpixel |
JP2003025589A (en) | 2001-07-16 | 2003-01-29 | Konica Corp | Ink jet recording head and recorder using the same |
JP2003255899A (en) * | 2001-12-28 | 2003-09-10 | Sanyo Electric Co Ltd | Display device |
-
2005
- 2005-11-10 JP JP2005326742A patent/JP4594215B2/en not_active Expired - Fee Related
- 2005-11-23 US US11/284,973 patent/US20060152459A1/en not_active Abandoned
- 2005-11-24 EP EP05111211A patent/EP1662463B1/en not_active Expired - Fee Related
- 2005-11-24 DE DE602005026490T patent/DE602005026490D1/en active Active
-
2009
- 2009-03-16 US US12/404,827 patent/US8077168B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5568163A (en) * | 1993-09-06 | 1996-10-22 | Nec Corporation | Apparatus for driving gate storage type liquid crystal, display panel capable of simultaneously driving two scan lines |
US5883609A (en) * | 1994-10-27 | 1999-03-16 | Nec Corporation | Active matrix type liquid crystal display with multi-media oriented drivers and driving method for same |
US6392629B1 (en) * | 1997-10-08 | 2002-05-21 | Fujitsu Limited | Drive circuit for liquid-crystal displays and liquid-crystal display including drive circuits |
US20020163493A1 (en) * | 1998-03-30 | 2002-11-07 | Sharp Kabushiki Kaisha | Liquid crystal display device and method of driving same |
US6784864B1 (en) * | 1999-07-12 | 2004-08-31 | Semiconductor Energy Laboratory Co., Ltd. | Digital driver and display device |
US20050046619A1 (en) * | 2003-08-28 | 2005-03-03 | Sharp Kabushiki Kaisha | Driving circuit for display device, and display device |
Cited By (50)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140285408A1 (en) * | 2006-05-29 | 2014-09-25 | Sony Corporation | Image display |
US10885878B2 (en) | 2006-05-29 | 2021-01-05 | Sony Corporation | Image display |
US9734799B2 (en) | 2006-05-29 | 2017-08-15 | Sony Corporation | Image display |
US10062361B2 (en) | 2006-05-29 | 2018-08-28 | Sony Corporation | Image display |
US9001012B2 (en) * | 2006-05-29 | 2015-04-07 | Sony Corporation | Image display |
US10438565B2 (en) | 2006-05-29 | 2019-10-08 | Sony Corporation | Image display |
US9013376B2 (en) | 2006-07-03 | 2015-04-21 | Seiko Epson Corporation | Light emitting device, method of driving pixel circuit, and driving circuit |
US20080074412A1 (en) * | 2006-07-03 | 2008-03-27 | Seiko Epson Corporation | Light emitting device, method of driving pixel circuit, and driving circuit |
US9275754B2 (en) * | 2006-09-07 | 2016-03-01 | Lg Display Co., Ltd. | Shift register, data driver having the same, and liquid crystal display device |
US20080062113A1 (en) * | 2006-09-07 | 2008-03-13 | Lg.Philips Lcd Co., Ltd. | Shift resister, data driver having the same, and liquid crystal display device |
US20080068300A1 (en) * | 2006-09-20 | 2008-03-20 | Hiroki Ikeda | Plasma Display Device |
US8130183B2 (en) | 2006-09-22 | 2012-03-06 | Samsung Mobile Display Co., Ltd. | Scan driver and scan signal driving method and organic light emitting display using the same |
US20080111837A1 (en) * | 2006-11-09 | 2008-05-15 | Kim Do-Ki | Driving method of a display |
US20080170029A1 (en) * | 2007-01-15 | 2008-07-17 | Kim Mihae | Scan driving circuit, electroluminescent display having the same |
US8013810B2 (en) * | 2007-01-15 | 2011-09-06 | Samsung Mobile Display Co., Ltd. | Scan driving circuit, electroluminescent display having the same |
US20080246697A1 (en) * | 2007-04-06 | 2008-10-09 | Jongyun Kim | Organic light emitting display |
US8022920B2 (en) | 2007-04-06 | 2011-09-20 | Samsung Mobile Display Co., Ltd. | Organic light emitting display |
EP1978503A2 (en) * | 2007-04-06 | 2008-10-08 | Samsung SDI Co., Ltd. | Organic light emitting display |
EP1978503A3 (en) * | 2007-04-06 | 2009-08-19 | Samsung Mobile Display Co., Ltd. | Organic light emitting display |
US20080278467A1 (en) * | 2007-05-09 | 2008-11-13 | In-Jae Hwang | Liquid crystal display having progressive and interlaced modes, and driving method of the liquid crystal display |
US8614701B2 (en) | 2007-05-30 | 2013-12-24 | Sharp Kabushiki Kaisha | Scan signal line driver circuit, display device, and method of driving scan signal lines |
US8654115B2 (en) | 2007-05-30 | 2014-02-18 | Sharp Kabushiki Kaisha | Scan signal line driver circuit, display device, and method of driving scan signal lines |
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US20100134474A1 (en) * | 2007-05-30 | 2010-06-03 | Takuya Watanabe | Scan signal line driver circuit, display device, and method of driving scan signal lines |
US8305404B2 (en) * | 2007-06-28 | 2012-11-06 | Seiko Epson Corporation | Electro-optical apparatus, method of driving same, and electronic apparatus |
US20090002295A1 (en) * | 2007-06-28 | 2009-01-01 | Seiko Epson Corporation | Electro-optical apparatus, method of driving same, and electronic apparatus |
US20100134396A1 (en) * | 2008-11-28 | 2010-06-03 | Semiconductor Energy Laboratory Co., Ltd. | Display device and electronic device including the same |
US8669969B2 (en) * | 2010-01-05 | 2014-03-11 | Samsung Display Co., Ltd. | Scan driver and flat panel display device including the same |
US20110164017A1 (en) * | 2010-01-05 | 2011-07-07 | Chung Kyung-Hoon | Scan driver and flat panel display device including the same |
US8681142B2 (en) | 2010-02-04 | 2014-03-25 | Samsung Display Co., Ltd. | Scan driver and flat panel display apparatus including the same |
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US8686990B2 (en) | 2011-04-08 | 2014-04-01 | Sharp Kabushiki Kaisha | Scanning signal line drive circuit and display device equipped with same |
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US10235938B2 (en) * | 2013-07-18 | 2019-03-19 | Joled Inc. | Gate driver circuit including variable clock cycle control, and image display apparatus including the same |
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US9583066B2 (en) * | 2014-07-16 | 2017-02-28 | Boe Technology Group Co., Ltd. | Gating control module logic for a gate driving method to switch between interlaced and progressive driving of the gate lines |
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Also Published As
Publication number | Publication date |
---|---|
US8077168B2 (en) | 2011-12-13 |
EP1662463A2 (en) | 2006-05-31 |
JP2006154810A (en) | 2006-06-15 |
US20090231311A1 (en) | 2009-09-17 |
DE602005026490D1 (en) | 2011-04-07 |
EP1662463A3 (en) | 2006-09-27 |
EP1662463B1 (en) | 2011-02-23 |
JP4594215B2 (en) | 2010-12-08 |
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