CN100559437C

CN100559437C - Selectivity is carried out and is lined by line scan and interleaved scanner driver and display thereof

Info

Publication number: CN100559437C
Application number: CNB2005101269406A
Authority: CN
Inventors: 申洞蓉
Original assignee: Samsung Mobile Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2004-11-26
Filing date: 2005-11-28
Publication date: 2009-11-11
Anticipated expiration: 2025-11-28
Also published as: KR100601379B1; KR20060059082A; CN1783189A

Abstract

A kind of optionally the execution lined by line scan and interleaved scanner driver and the display that uses it.This scanner driver comprise the trigger with a plurality of series connection shift register, have the odd lines selected cell of a plurality of NAND doors and have the even lines selected cell of a plurality of NAND doors.In response to odd lines control signal that is input to odd lines selected cell and even lines selected cell respectively and even lines control signal, scanner driver is carried out and is lined by line scan or staggered scanning.Scanner driver also can comprise mode selecting unit, lines by line scan or staggered scanning optionally to carry out in response to mode select signal.

Description

Selectivity is carried out and is lined by line scan and interleaved scanner driver and display thereof

The cross reference of related application

The application requires the right of priority and the rights and interests of the korean patent application of submitting on November 26th, 2004 10-2004-0098255 number and the korean patent application of submitting on November 26th, 2004 10-2004-0098267 number, thus for here comprehensively all purposes of elaboration merge by reference.

Technical field

The present invention relates to a kind of scanner driver that is used for flat-panel monitor (FPD), and more specifically, relate to a kind of optionally the execution and line by line scan and interleaved scanner driver.

Background technology

Scanner driver is the requisite circuit of FPD.Scanner driver is used to drive a plurality of pixels of arranging along row and column.In order to drive these pixels, scanner driver makes that the pixel of selected row can be luminous, or makes data can be input to selected pixel.

In general, the formation of a picture frame need define the vertical synchronizing signal of picture frame display cycle and drive form each horizontal-drive signal of a plurality of pixel lines of this picture frame.In the activation level synchronizing signal, view data is imported into the pixel that is in line to its transmit level synchronizing signal.

In passive matrix (PM) display, when input image data, pixel begins luminous; Yet in active matrix (AM) display, after the view data of having stored input, all pixels that are in line are luminous during predetermined lasting time.

In LCD (LCD), organic electroluminescent (EL) display and plasma display panel (PDP), horizontal-drive signal is generally known as sweep signal.So the signal of selecting and activate line will be known as sweep signal below.

The circuit that sweep signal is transferred to the panel of wherein arranging pixel is a scanner driver.More specifically, scanner driver is transferred to sweep signal the homologous lines of panel.Via the selection of the line of the transmission of sweep signal with activate and to carry out according to method of lining by line scan or staggered scanning method.

In the method for lining by line scan, sweep signal is sequentially transferred to the panel line.That is to say that sweep signal is sequentially transferred to first line each in the last line.

In the staggered scanning method, handle and display frame by two.Specifically, in first handles, with half corresponding odd field cycle in frame period during, sweep signal is sequentially transferred to the line of odd-numbered.In second handles, with half corresponding even field cycle of residue in frame period during, sweep signal is sequentially transferred to the line of even-numbered.

Therefore, traditional F DP utilization is lined by line scan or staggered scanning comes display image data, does not line by line scan and interleaved scanner driver because this FDP does not comprise optionally carrying out.

Summary of the invention

So, the invention provides a kind of can optionally the execution and line by line scan and interleaved scanner driver.

The present invention also provides a kind of can optionally the execution to line by line scan and interleaved OLED display.

The present invention also provides a kind of and has utilized mode selecting unit optionally to carry out to line by line scan and interleaved scanner driver.

Other features of the present invention will be illustrated in the following description, and partly become clear according to this description, maybe can learn by practice of the present invention.

The invention discloses a kind of optionally the execution and line by line scan and interleaved scanner driver, it comprises: shift register, be used to receive initial pulse and clock signal, and every cycle of clock signal and output data; The odd lines selected cell is used to receive the output signal and the odd lines control signal of the odd-numbered trigger of shift register, and to the signal actuating logic computing that received to produce the odd number sweep signal; With the even lines selected cell, be used to receive the output signal and the even lines control signal of the even-numbered trigger of shift register, and to the signal actuating logic computing that received to produce the even-line interlace signal.

The invention also discloses a kind of display, comprising: pel array has a plurality of pixels; Scanner driver is used for sweep signal and emissioning controling signal are transferred to this pel array, and optionally carries out and line by line scan and staggered scanning; And data driver, be used for the sweep signal selected pixel of data transmission to scanner driver.This scanner driver comprises: shift register, be used to receive initial pulse and clock signal, and every cycle of clock signal and output data; The odd lines selected cell is used to receive the output signal and the odd lines control signal of the odd-numbered trigger of shift register, and to the signal actuating logic computing that received to produce the odd number sweep signal; With the even lines selected cell, be used to receive the output signal and the even lines control signal of the even-numbered trigger of shift register, and to the signal actuating logic computing that received to produce the even-line interlace signal.

The invention also discloses a kind of optionally the execution and line by line scan and interleaved scanner driver, it comprises: shift register, be used to receive initial pulse and clock signal, and every half and output data of clock signal period; Mode selecting unit is used to receive the output signal of the trigger of shift register, and in response to mode select signal to the output signal actuating logic computing of trigger; The odd lines selected cell is used for selecting the output signal of odd-numbered trigger or the output signal of mode selecting unit in response to the odd lines control signal; With the even lines selected cell, be used for selecting the output signal of even-numbered trigger or the output signal of mode selecting unit in response to the even lines control signal.

The invention also discloses a kind of optionally the execution lines by line scan and interleaved scanner driver, it comprises: shift register, the a plurality of triggers that comprise series connection, wherein the odd-numbered trigger is also exported the signal of being sampled at rising edge of clock signal up-sampling input signal, and the signal that the even-numbered trigger is sampled in the negative edge up-sampling input signal and the output of clock signal; Mode selecting unit is used in response to mode select signal the output signal actuating logic OR computing of adjacent trigger or the output signal of shielding (mask) trigger; The odd lines selected cell is used for selecting the output signal of odd-numbered trigger or the output signal of mode selecting unit in response to the odd lines control signal; With the even lines selected cell, be used for selecting the output signal of even-numbered trigger or the output signal of mode selecting unit in response to the even lines control signal.

It is exemplary and indicative should understanding above general description and following detailed description, and is intended to provide the of the present invention further explanation to claimed.

Description of drawings

Comprise and incorporate in this instructions that to provide further understanding of the present invention and the accompanying drawing that constitutes the part of this instructions are illustrated embodiments of the invention, and and this describe one and be used from and explain principle of the present invention.

Fig. 1 is that the execution of the example embodiment according to the present invention is lined by line scan and the circuit diagram of interleaved scanner driver.

Fig. 2 is the circuit diagram of the trigger of example embodiment according to the present invention.

Fig. 3 shows the sequential chart of lining by line scan of the scanner driver of Fig. 1.

Fig. 4 A and Fig. 4 B show the interleaved sequential chart of the scanner driver of Fig. 1.

Fig. 5 A is the block scheme of the OLED display that comprises scanner driver of another example embodiment according to the present invention.

Fig. 5 B is the circuit diagram of pixel-driving circuit of the OLED display of Fig. 5 A.

Fig. 6 A and Fig. 6 B show Fig. 5 A OLED display line by line scan and interleaved sequential chart.

Fig. 7 is the circuit diagram of the scanner driver of another example embodiment according to the present invention.

Fig. 8 is the circuit diagram of the trigger of Fig. 7.

Fig. 9 A and Fig. 9 B are respectively the circuit diagram and the truth tables of the mode selection circuit of Fig. 7.

Figure 10 is the circuit diagram of the line options circuit of Fig. 7.

Figure 11 A and Figure 11 B show Fig. 7 scanner driver line by line scan and interleaved sequential chart.

Embodiment

Below with reference to the accompanying drawing that wherein shows embodiments of the invention the present invention is described more fully.Yet the present invention can implement with different forms, and should not be construed as limited to the embodiment that proposes here.On the contrary, it is more thorough in order to expose that these embodiment are provided, and these embodiment will pass on scope of the present invention to those skilled in the art comprehensively.In the accompanying drawings, for the sake of clarity, the size and the relative size in layer and zone can be exaggerated.

Fig. 1 is that optionally carrying out of example embodiment lined by line scan and the circuit diagram of interleaved scanner driver according to the present invention.

With reference to figure 1, scanner driver comprises shift register 100, odd lines selected cell 120 and even lines selected cell 140.

This shift register 100 comprises the corresponding trigger of number with the sweep trace of panel.Therefore, when panel comprised m sweep trace, shift register 100 comprised m trigger at least.Clock signal clk and inversion clock signal/CLK are imported into each trigger.Each trigger with input clock signal CLK in each synchronous clock period, with the data transmission of being stored to next trigger.

Therefore, the output signal SR1 of the data of storing among the trigger FF1 from initial pulse VSP is delayed a clock period and as the output signal SR2 of trigger FF2 and export.That is, trigger FF1, FF2, FF3 ... and the output signal SR1 of FFm, SR2, SR3 ... and SRm is delayed a clock period and exports as the signal that postpones.

Odd lines selected cell 120 comprises a plurality of NAND (with non-) door.Odd lines control signal ODD is imported into the NAND door of odd lines selected cell 120.And, the output signal SR1 of odd-numbered trigger, SR3 ... and SRm-1 is imported into the NAND door of odd lines selected cell 120.

More specifically, a NAND door 121 receives the output signal SR1 of odd lines control signal ODD and trigger FF1, and the signal actuating logic computing to being received, to produce the first sweep signal SCAN[1].And the 3rd NAND door 123 receives the output signal SR3 of odd lines control signal ODD and trigger FF3, and the signal actuating logic computing to being received, to produce the 3rd sweep signal SCAN[3].The one NAND door 121 to (m-1) NAND doors 125 of odd lines selected cell 120 are carried out identical operation according to same principle as mentioned above.Therefore, 120 work of odd lines selected cell are to produce the odd number sweep signal.

Even lines selected cell 140 also comprises a plurality of NAND doors.Even lines control signal EVEN is imported into the NAND door of even lines selected cell 140.In addition, the output signal SR2 of even-numbered trigger, SR4 ... and SRm is imported into the NAND door of even lines selected cell 140.

More specifically, the 2nd NAND door 142 receives the output signal SR2 of even lines control signal EVEN and trigger FF2, and the signal actuating logic computing to being received, to produce the second sweep signal SCAN[2].And the 4th NAND door 144 receives the output signal SR4 of even lines control signal EVEN and trigger FF4, and the signal actuating logic computing to being received, to produce the 4th sweep signal SCAN[4].The 2nd NAND door 142 to the m NAND doors 146 of even lines selected cell 140 are carried out identical operation according to same principle as mentioned above.

When the scanner driver execution was lined by line scan, odd lines control signal ODD was in high level, and the NAND door of odd-numbered makes input signal anti-phase.Thus, the first sweep signal SCAN[1] be the inversion signal of the output signal SR1 of trigger FF1, the 3rd sweep signal SCAN[3] be the inversion signal of the output signal SR3 of trigger FF3, and m-1 sweep signal SCAN[m-1] be the inversion signal of the output signal SRm-1 of trigger FFm-1.

In addition, during lining by line scan, even lines control signal EVEN is in high level, and the NAND door of even-numbered makes input signal anti-phase.Thus, the second sweep signal SCAN[2] be the inversion signal of the output signal SR2 of trigger FF2, the 4th sweep signal SCAN[4] be the inversion signal of the output signal SR4 of trigger FF4, and m sweep signal SCAN[m] be the inversion signal of the output signal SRm of trigger FFm.

Therefore, when odd lines control signal ODD and even lines control signal EVEN were in high level, scanner driver was carried out and is lined by line scan.

On the other hand, when scanner driver is carried out staggered scanning, with half corresponding odd field cycle in frame period during, odd lines control signal ODD is in high level.Therefore, during the odd field cycle, the NAND door of odd-numbered makes input signal anti-phase.

In addition, with second half corresponding even field cycle in frame period during, odd lines control signal ODD is in low level.Therefore, during the even field cycle, the NAND door of odd-numbered is carried out masking operation, does not consider the output signal level of odd-numbered trigger thus and exports high level signal.

In addition, when scanner driver was carried out staggered scanning, during the odd field cycle, even lines control signal EVEN was in low level.Therefore, during the odd field cycle, the NAND door of even-numbered output high level signal.On the other hand, during the even field cycle, even lines control signal EVEN is in high level.Therefore, during the even field cycle, the NAND door of even-numbered makes input signal anti-phase.

Thus, when the scanner driver execution of Fig. 1 is lined by line scan, activate odd lines selected cell 120 and even lines selected cell 140.But when scanner driver is carried out staggered scanning, only during the odd field cycle, activate odd lines selected cell 120, and only during the even field cycle, activate even lines selected cell 140.

Fig. 2 is the circuit diagram of one of trigger of Fig. 1.

With reference to figure 2, this trigger comprises first latch 200 and second latch 210.

First latch 200 comprises first sampling thief 202 and first retainer 204.First sampling thief 202 is sampled to input signal in the low-level period of clock signal clk, and first retainer 204 keeps the output signal of first sampling thief 202 in the high level period of clock signal clk.Thus, the signal that is input to first sampling thief 202 during the low-level period of clock signal clk is maintained in the high level period of clock signal clk in first retainer 204 always.Because input signal has the frequency lower than the frequency of clock signal clk,, and during its high level period, keep the input signal of being sampled during the low-level period of clock signal clk so first latch 200 is sampled to input signal.

Second latch 210 comprises second sampling thief 212 and second retainer 214.Second sampling thief 212 is sampled to input signal in the high level period of clock signal clk, and second retainer 214 keeps the output signal of second sampling thief 212 in the low-level period of clock signal clk.

The operation of the trigger of Fig. 2 will be described now.

When clock signal clk was low level, first sampling thief, 202 receiving inputted signals made input signal anti-phase, and anti-phase signal is outputed to first retainer 204.Because first retainer 204 works when high level, thus its during the low-level period of clock signal clk, do not keep anti-phase signal.In case clock signal clk has carried out transformation from low to high, then first sampling thief 202 stops receiving inputted signal, and first retainer 204 keep anti-phase signal.Simultaneously, second sampling thief, 212 receiving inputted signals.The output signal that is input to first retainer 204 of second sampling thief 212 is exported via the phase inverter of first retainer 204.But when clock signal clk was high level, second retainer 214 did not keep the data that received, and when clock signal clk is low level once more, and second retainer 214 keeps the data that received.

Therefore, the trigger of Fig. 2 is stored in the data near input before the rising edge of clock signal clk, and is exporting these data during the one-period of clock signal clk till new sampling operation begins.

Referring now to Fig. 1 and Fig. 3 lining by line scan of scanner driver described.

As described in reference to figure 1, when the scanner driver execution is lined by line scan, the NAND door of odd lines selected cell 120 and even lines selected cell 140 makes the output signal of trigger anti-phase, because odd lines control signal ODD and even lines control signal EVEV are high level.

At first, during the low-level period of clock signal clk, the initial pulse VSP that has with the frame rate same frequency is imported into trigger FF1.Trigger FF1 sampled to initial pulse VSP before the rising edge of clock signal clk, and exported the data of being sampled.Thus, during the period 1, the output signal SR1 of trigger FF1 is a high level.

Output signal SR1 is imported into a NAND door 121 and trigger FF2.Because odd lines control signal ODD is high level, thus a NAND door 121 make the anti-phase and output of output signal SR1 anti-phase signal.Thus, during the period 1, the first sweep signal SCAN[1] be low level.

Output signal SR1 also is imported into trigger FF2, postpones one-period, also exports as inhibit signal then.That is, on the rising edge of data in its second round of sampling before the rising edge near the second round of clock signal clk, be output.Therefore, trigger FF2 output specific output signal SR1 postpones the output signal SR2 of one-period.

The output signal SR2 of trigger FF2 is imported into the 2nd NAND door 142 and trigger FF3.Because even lines control signal EVEN is high level, thus the 2nd NAND door 142 make the anti-phase and output of output signal SR2 anti-phase signal.Thus, during second round, the second sweep signal SCAN[2] be low level.

Thereafter, trigger FF3 receives output signal SR2 and exports the output signal SR3 that specific output signal SR2 postpones one-period.The 3rd NAND door 123 receives output signal SR3 and makes it anti-phase, and output is low level the 3rd sweep signal SCAN[3 during the period 3].

Aforesaid operations continues, to the last a trigger FFm output signal output SRm and produce m sweep signal SCAN[m] till.

In other words, utilization is lined by line scan, and as mentioned above, during a frame period, can produce all sweep signals successively.

The staggered scanning of scanner driver is described referring now to Fig. 4 A and Fig. 1.

As described above with reference to Figure 1, during staggered scanning, a frame period is divided into odd field cycle and even field cycle.Odd number sweep signal SCAN[1,3 ..., m-1] during the odd field cycle, be activated, and even-line interlace signal SCAN[2,4 ..., m] during the even field cycle, be activated.

Odd lines control signal ODD is high level during the odd field cycle producing odd number sweep signal SCAN[1,3 ..., m-1].Similarly, even lines control signal EVEN is high level during the even field cycle producing even-line interlace signal SCAN[2,4 ..., m].

During the staggered scanning of Fig. 4 A, with only about half of corresponding odd field cycle in frame period during, the output signal of odd-numbered trigger is by anti-phase and output, and the output signal conductively-closed of even-numbered trigger.Odd lines control signal ODD remains high level during the odd field cycle so that the output signal of odd-numbered trigger is anti-phase, and even lines control signal EVEN remains the output signal of low level with shielding even-numbered trigger during the even field cycle.

On the other hand, with second half corresponding even field cycle in frame period during, the output signal conductively-closed of odd-numbered trigger, and the output signal of even-numbered trigger is by anti-phase and from the NAND door output of even lines selected cell 140.Odd lines control signal ODD remains the output signal of low level with shielding odd-numbered trigger during the even field cycle, and even lines control signal EVEN remains high level during the even field cycle so that the output signal of even-numbered trigger is anti-phase.

At first, the initial pulse VSP of frequency with twice of frame rate is imported into trigger FF1.And the clock frequency of Fig. 4 A approximately is the twice that illustrates the clock frequency of the Fig. 3 that lines by line scan.Thus, in Fig. 4 A, initial pulse VSP has and two corresponding high level period of clock period at least.Therefore, the output signal of each trigger has and two corresponding high level period of clock period.

Produce by processing same as shown in Figure 3 slave flipflop FF1 output output signal SR1, slave flipflop FF2 output output signal SR2, slave flipflop FF3 output output signal SR3 ... and the output signal SRm of slave flipflop FFm output.Therefore, the output signal SR1 of trigger, SR2, SR3 ..., SRm-1 and SRm have the high level period that postpones one-period.And, owing to each output signal has and two corresponding high level period of clock period, so the output signal of the trigger of two orders has the high level period of an overlapping clock period.

During n the cycle of clock signal clk, the m of a trigger output signal is a high level every one-period.And during residue n+1 the cycle of clock signal clk, the m of a trigger output signal is a high level every one-period.

During the odd field cycle, odd lines control signal ODD is a high level.But consider regularly tolerance limit, the time delay that causes owing to transmission line for example, during the output signal SR1 to trigger FF1 carries out logical operation, can locate than Zao half clock period of the period 1 of clock signal clk, ODD rises to high level with the odd lines control signal.In response to the odd lines control signal ODD of high level, the NAND door of odd lines selected cell 120 make the odd-numbered trigger output signal SR1, SR3 ... and SRm-1 is anti-phase, and output anti-phase signal.

And during the odd field cycle, even lines control signal EVEN is a low level.But consider regularly tolerance limit, even lines control signal EVEN can locate to drop to low level than late half clock period of the period 1 of clock signal clk.In response to having low level even lines control signal EVEN, the output signal of the NAND door shielding even-numbered trigger of even lines selected cell 140.Therefore, even-numbered sweep signal SCAN[2,4 ..., m] become high level.

With second half corresponding even field cycle in frame period during, odd lines control signal ODD is a low level, and even lines control signal EVEN is a high level.Thus, the output signal conductively-closed of odd-numbered trigger, and odd lines sweep signal SCAN[1,3 ..., m-1] remain high level.And, even lines selected cell 140 make the even-numbered trigger output signal SR2, SR4 ... and SRm is anti-phase, and output anti-phase signal.Therefore, during two clock period, even lines sweep signal SCAN[2,4 ..., m] be low level.

Here, many clock period in comparable odd field cycle in even field cycle, make the output signal SRm of last trigger by anti-phase, and complete (intact) signal can be transferred to the m sweep trace.

Compare with Fig. 4 A, the number that Fig. 4 B shows the clock signal that odd field comprises in the cycle can equal the number of the clock signal that even field comprises in the cycle.That is, the odd field cycle in a frame period can have n+1 clock period, and the even field cycle that should the frame period also can have n+1 clock period.In Fig. 4 A, the output signal SRm of m trigger FFm has high level period during odd field cycle and even field cycle.Yet in Fig. 4 B, the output signal SRm of m trigger FFm has high level period during two clock period that odd field comprised in the cycle.

The operation of the generation of trigger output signal and odd lines selected cell 120 and even lines selected cell 140 is with above described identical with reference to figure 4A.Thus, will omit its detailed description here.

Embodiment 2

Fig. 5 A is the block scheme of the organic electroluminescent that comprises scanner driver (EL) display of another example embodiment according to the present invention, and Fig. 5 B is the circuit diagram of the pixel-driving circuit of the OLED display shown in Fig. 5 A.

With reference to figure 5A, this OLED display comprises scanner driver 301, data driver 303 and pel array 305.

This scanner driver 301 is optionally carried out shown in Figure 1 lining by line scan and staggered scanning.Scanner driver 301 also applies sweep signal via m sweep trace, and applies emissioning controling signal via m launch-control line.

Data driver 303 is applied to data on the line of emissioning controling signal and the selected pel array 305 of sweep signal.The data that applied can be voltage or electric current.When the data that applied were voltage, OLED display can be the voltage once-type, and when working as the data that applied and being electric current, OLED display can be the electric current once-type.

Although electric current once-type OLED display has been shown among Fig. 5 A, those skilled in the art should understand that can replace working voltage writes display.

Pel array 305 comprises a plurality of pixels 310.The first sweep signal SCAN[1] and the first emissioning controling signal EMI[1] be applied in the pixel 310 of arranging in first row, and the second sweep signal SCAN[2] and the second emissioning controling signal EMI[2] be applied in the pixel 310 of arranging in second row.That is, at least one sweep signal and at least one emissioning controling signal are applied to and form the pixel 310 of arranging in the horizontal delegation.

Fig. 5 B is the circuit diagram that the electric current of the OLED display shown in Fig. 5 A writes pixel-driving circuit.

With reference to figure 5B, this pixel-driving circuit comprises four transistor M1, M2, M3 and M4, programming capacitor Cst and Organic Light Emitting Diode OLED.

Driving transistors M1 will be provided to emission control transistor M4 with the essentially identical electric current of data current during the firing operation of pixel, described electric current is via data line data[n] and sink (sunk).In order to produce and the essentially identical electric current of data current, the grid of driving transistors M1 is electrically connected to an end and the switching transistor M2 of programming capacitor Cst.Driving transistors M1 also is electrically connected to supply voltage ELVdd and transistor M3 and M4.

Switching transistor M2 is in response to sweep signal SCAN[m] and conducting forms data line data[n thus] and programming capacitor Cst between the path.And switching transistor M2 is applied to the grid of driving transistors M1 with predetermined bias, forms the voltage Vgs of the driving transistors M1 corresponding with data current thus.

Transistor M3 is in response to sweep signal SCAN[m] and conducting, and during the data current programming operation in the future the electric current of self-driven transistor M1 be provided to data line data[n].

Transistor M4 is in response to emissioning controling signal EMI[m] and conducting, and during firing operation in the future the electric current of self-driven transistor M1 be provided to Organic Light Emitting Diode OLED.

Electric current writes pixel-driving circuit storage voltage Vgs corresponding with data current in programming capacitor Cst, and conducting emission control transistor M4, and making to provide and the essentially identical electric current of data current to Organic Light Emitting Diode OLED.

Initially, in case emissioning controling signal EMI[m] carried out transformation from low to high, then emission control transistor M4 ends, and interrupts the firing operation of Organic Light Emitting Diode OLED thus.

When emission control transistor M4 ends, as sweep signal SCAN[m] when having carried out transformation from high to low, switching transistor M2 and all conductings of transistor M3.In response to low level sweep signal SCAN[m], pixel is selected and begin data are programmed.

Transistor M2 and M3 are in response to low level sweep signal SCAN[m] and conducting.In transistor M2 and M3 conducting, when data current Idata via data line data[n] when sinking, supply voltage ELVdd, driving transistors M1 and transistor M3 form current path.And when data current Idata sank, switching transistor M2 was operated in the triode region.That is, direct current is not provided to the grid of programming capacitor Cst and driving transistors M1 basically, and the bias voltage that only is used for conducting driving transistors M1 is provided to the grid of driving transistors M1.

And driving transistors M1 can be operated in the zone of saturation, being provided to data line data[n from the data current Idata of supply voltage ELVdd].When driving transistors M1 is operated in the zone of saturation, as follows the providing of data current Idata of flowing by driving transistors M1:

Idata＝K(Vgs-Vth) ² (1)

Wherein K represents proportionality constant, and Vgs represents the grid of driving transistors M1 and the pressure reduction between the source electrode, and Vth represents the threshold voltage of driving transistors M1.

As sweep signal SCAN[m] when having carried out transformation from low to high subsequently, transistor M2 and M3 end, and programming capacitor Cst keeps this pressure reduction Vgs.

Thereafter, as emissioning controling signal EMI[m] when having carried out transformation from high to low, emission control transistor M4 conducting.Along with the conducting of emission control transistor M4, driving transistors M1 is operated in the zone of saturation, and the data current Idata corresponding with stored voltage Vgs among the programming capacitor Cst is provided to transistor M4.Be provided to Organic Light Emitting Diode OLED with the electric current that data current Idata equates substantially by emission control transistor M4, it is luminous that Organic Light Emitting Diode OLED uses the brightness corresponding with data current Idata thus.

As mentioned above, electric current writes pixel-driving circuit and can have various configurations.

Fig. 6 A and Fig. 6 B show lining by line scan of the OLED display shown in Fig. 5 A and interleaved sequential chart.

Specifically, Fig. 6 A shows the sequential chart of lining by line scan of the OLED display shown in Fig. 5 A.

With reference to figure 6A, this OLED display is emissioning controling signal EMI[1, and 2 ..., m] be applied to pel array 305, make data driver 303 can carry out the electric current write operation thus.And, as emissioning controling signal EMI[1,2 ..., m] with sweep signal SCAN[1,2 ..., m] during time synchronized, pixel can be carried out current programmed operation of data and firing operation continuously.So, sweep signal SCAN[1,2 ..., m] and emissioning controling signal EMI[1,2 ..., m] be applied to pixel with predetermined time interval.Therefore, sweep signal SCAN[1,2 ..., m] low-level period than emissioning controling signal EMI[1,2 ..., m] high level period short.

In order to make sweep signal SCAN[1,2 ..., m] than emissioning controling signal EMI[1,2 ..., m] short, odd lines control signal ODD and even lines control signal EVEN can be pulse train (pulse trains).

As can be seen from Figure 1, when odd lines control signal ODD is low level, the output signal SR1 of odd-numbered trigger, SR3 ... and the SRm-1 conductively-closed, and odd number sweep signal SCAN[1,3 ..., m-1] be high level.

Similarly, when even lines control signal EVEN is low level, the output signal SR2 of even-numbered trigger, SR4 ... and the SRm conductively-closed, and even-line interlace signal SCAN[2,4 ..., m] be high level.

Therefore, when odd lines control signal ODD was pulse train, its low-level period was reflected in odd number sweep signal SCAN[1, and 3 ..., m-1] in.In other words, when the output signal of odd-numbered trigger is high level and odd lines control signal ODD when being low level, odd number sweep signal SCAN[1,3 ..., m-1] become high level.Therefore, the odd number sweep signal SCAN[1 of Fig. 6 A, 3 ..., m-1] have at interval than the short low level time of the odd number sweep signal of Fig. 3.

In addition, as shown in Figure 6A, odd number emissioning controling signal EMI[1,3 ..., m-1] high level period longer than the low-level period of odd number sweep signal.Here, odd number emissioning controling signal EMI[1,3 ..., m-1] have and the essentially identical waveform of the output signal of odd-numbered trigger.Thus, odd number emissioning controling signal EMI[1,3 ..., m-1] can utilize the output signal of odd-numbered trigger and form, perhaps they can utilize the additional Waveform generating circuit according to another embodiment to form.

The above-mentioned waveform generation of same application is handled with generation even-line interlace signal SCAN[2, and 4 ..., m].Therefore, in response to odd lines control signal ODD and even lines control signal EVEN and produce the first emissioning controling signal EMI[1 successively] and the first sweep signal SCAN[1], the second emissioning controling signal EMI[2] and the second sweep signal SCAN[2] ... and m emissioning controling signal EMI[m] and m sweep signal SCAN[m].

At emissioning controling signal EMI[1,2 ..., m] when being high level, the pixel 310 that has been applied in this signal is not luminous.And, when having and emissioning controling signal EMI[1,2 ..., m] the sweep signal SCAN[1 in the identical time interval, 2 ..., m] when being imported into pixel 310, pixel 310 begins to carry out the current programmed operation of data.In case sweep signal SCAN[1,2 ..., m] be thus lifted to high level, pixel 310 is just finished this programming operation, and the pixel 310 of programming then can be from sweep signal SCAN[1, and 2 ..., m] rising edge after the emissioning controling signal EMI[1 that takes place of short time, 2 ..., m] negative edge begin luminous.

Fig. 6 B shows the interleaved sequential chart of the OLED display shown in Fig. 5 A.

The sequential chart of Fig. 6 B can add emissioning controling signal EMI[1 by the sequential chart to Fig. 4 B, and 2 ..., m] and obtain.In addition because sweep signal SCAN[1,2 ..., m] the comparable emissioning controling signal EMI[1 of low-level period, 2 ..., m] high level period short, so odd lines control signal ODD has and different waveform shown in Fig. 4 B with even lines control signal EVEN.

During the odd field cycle, odd lines control signal ODD activates odd number sweep signal SCAN[1, and 3 ..., m-1].But because odd lines control signal ODD has low-level period during each cycle of clock signal clk, so the conductively-closed during low-level period of the output signal of odd-numbered trigger.Therefore, as above described with reference to figure 6A, the high level period of emissioning controling signal is longer than the low-level period of sweep signal.

Because emissioning controling signal has and the essentially identical waveform of the output signal of trigger, so the output signal of trigger can be used as emissioning controling signal.Replacedly, can add adjunct circuit to produce emissioning controling signal.

During the even field cycle, even lines control signal EVEN activates even-line interlace signal SCAN[2, and 4 ..., m].Because even lines control signal EVEN has low-level period during each cycle of clock signal clk, so the conductively-closed and export during low-level period of the output signal of even-numbered trigger as high level signal.

As mentioned above, can find out and to utilize odd lines control signal ODD and even lines control signal EVEN to line by line scan or staggered scanning.In other words, scanner driver can optionally be carried out and line by line scan and staggered scanning in response to odd lines control signal ODD and even lines control signal EVEN.As a result, the display (for example OLED display, LCD or PDP) that comprises scanner driver is optionally carried out and is lined by line scan and staggered scanning.

Embodiment 3

With reference to figure 7, scanner driver comprises shift register 400, mode selecting unit 420, odd lines selected cell 440 and even lines selected cell 460.

Shift register 400 comprises a plurality of triggers, and has the many triggers of sweep trace of ratio panels.Thus, when panel comprised m sweep trace, shift register 400 comprised m+1 trigger at least.Among clock signal clk and the inversion clock signal/CLK at least one is imported into each trigger.

The first trigger FF1 receives initial pulse VSP, and clock signal clk is imported into clock input pin CK.The first trigger FF1 samples to the data of initial pulse VSP on the rising edge of clock signal clk, and exports the data of being sampled.

The second trigger FF2 receives the output signal SR1 of the first trigger FF1, and the inversion signal/CLK of clock signal clk is imported into the clock input pin CK of the second trigger FF2.The second trigger FF2 samples to output signal SR1 on the negative edge of clock signal clk, and exports the signal of being sampled.

Promptly, odd-numbered trigger FF1, FF3 ..., FFm-1 and FFm+1 sample to input signal on the rising edge of clock signal clk, and the output signal of being sampled, and the data of before the negative edge of storage near clock signal clk during the low-level period of clock signal clk, importing.And, even-numbered trigger FF2, FF4 ... and FFm samples to input signal on the negative edge of clock signal clk, and the output signal of being sampled, and the data of before the rising edge of storage near clock signal clk during the high level period of clock signal clk, importing.

Mode selecting unit 420 comprises a plurality of mode selection circuits in parallel.Each mode selection circuit receives the output signal of two flip-flops in series, and the output signal actuating logic computing to being received in response to mode select signal MODE.Each mode selection circuit comprises the NOR door, is used to receive the output signal of two flip-flops in series; And the NAND door, be used to receive the output signal and the mode select signal MODE of NOR door.

420 determined operations provide odd lines sweep signal SCAN[1 to odd lines selected cell 440 according to mode selecting unit, and 3 ..., m-1] to the odd-numbered sweep trace.Odd lines selected cell 440 comprises a plurality of line options circuit, is used for selecting the output signal of trigger or the output signal of mode selection circuit according to the control of odd lines control signal ODD.

420 determined operations provide even lines sweep signal SCAN[2 to even lines selected cell 460 according to mode selecting unit, and 4 ..., m] to the even-numbered sweep trace.Even lines selected cell 460 comprises a plurality of line options circuit, is used for selecting the output signal of trigger or the output signal of mode selection circuit according to the control of even lines control signal EVEN.

Fig. 8 is the circuit diagram of one of trigger of Fig. 7.

With reference to figure 8, trigger comprises sampling thief 501 and retainer 503.About the odd-numbered trigger, sampling thief 501 is being sampled to input signal SRk (or the initial pulse VSP under the situation of the first trigger FF1) during the high level period of input clock signal CLK, and retainer 503 is exported this input signal SRk during the high level period of clock signal clk, and keeps this input signal SRk during its low-level period.

Sampling thief 501 can comprise the phase inverter of working in response to clock signal clk.Thus, sampling thief 501 is sampled to input signal SRk during the high level period of clock signal clk.When clock signal clk kept high level, input signal SRk was imported into trigger and output.In case clock signal clk drops to low level, sampling thief 501 just interrupts the input of the input signal SRk of maintenance simultaneously in retainer 503.Retainer 503 begins to keep input signal SRk on the negative edge of clock signal clk.Thus, about the odd-numbered trigger, this trigger receiving inputted signal SRk, during the high level period of clock signal clk, export the input signal SRk that is received, the input signal SRk that maintenance is imported before near the negative edge of clock signal clk, and during its low-level period, export the input signal SRk that is kept.

With reference to figure 9A, mode selection circuit comprises NOR door 601 and NAND door 603.NOR door 601 receives the output signal SRk of k trigger and the output signal SRk+1 of k+1 trigger.

NAND door 603 receives the output signal and the mode select signal MODE of NOR doors 601, and the signal of two inputs is carried out the NAND computing, and then with operation result out[k] output to the line options circuit.

Fig. 9 B shows the logic state of mode select signal MODE and the operation result out[k that is obtained from the NAND computing] state.

When mode select signal MODE was low level, NAND door 603 was irrespectively exported high level signal with the output of NOR door 601.

On the other hand, when mode select signal MODE was high level, NAND door 603 made the output of NOR door 601 anti-phase.Therefore, when input signal SRk and SRk+1 are low level, out[k as a result] also be low level.Under other all situations, out[k as a result] be high level.Thus, during lining by line scan (promptly when mode select signal MODE is high level), mode selecting unit is to output signal SRk and SRk+1 actuating logic OR computing.

Therefore, only when mode select signal MODE be high level and input signal SRk and SRk+1 when being low level, this mode selection circuit is output low level signal.

Figure 10 is the circuit diagram of the line options circuit of Fig. 7.

With reference to Figure 10, the line options circuit comprises three NAND doors 701,705 and 707 and phase inverter 703.This line options circuit in response to odd lines control signal ODD or even lines control signal EVEN and select the output signal SRk of trigger or the output signal out[k of mode selection circuit].For example, when high level odd lines control signal ODD was imported into the line options circuit, a NAND door 701 made the output signal SRk of trigger anti-phase.And, because phase inverter 703 output low level signals to the two NAND doors 705, so the output signal out[k of the 2nd NAND door 705 and mode selection circuit] level irrespectively export high level signal.Because the high level output signal of the 2nd NAND door 705 is imported into the 3rd NAND door 707, so the 3rd NAND door 707 makes the output signal of a NAND door 701 anti-phase.Thus, the output signal SCAN[k of the 3rd NAND door 707] become the output signal SRk of trigger.

On the other hand, when low level odd lines control signal ODD was imported into the line options circuit, a NAND door 701 was irrespectively exported high level signal with the level of the output signal SRk of trigger.And, because phase inverter 703 output high level signals to the two NAND doors 705, so the 2nd NAND door 705 makes the output signal out[k of mode selection circuit] anti-phase, and the result outputed to the 3rd NAND door 707.Because the 3rd NAND door 707 receives the high level output signal of a NAND door 701, so it makes the output signal of the 2nd NAND door 705 anti-phase.Therefore, the output signal SCAN[k of the 3rd NAND door 707] become the output signal out[k of mode selection circuit].

In other words, the line options circuit of Figure 10 is selected during for high level and the output signal SRk of output trigger at odd lines control signal ODD or even lines control signal EVEN, and selects during for low level and output mode is selected the output signal out[k of circuit at odd lines control signal ODD or even lines control signal EVEN].

Figure 11 A and Figure 11 B be show respectively Fig. 7 scanner driver line by line scan and interleaved sequential chart.

With reference to figure 7 and Figure 11 A, during lining by line scan, scanner driver activates m sweep signal successively during a frame period.

Initially, the initial pulse VSP that has a same frequency with the vertical synchronizing signal of definition picture frame display cycle is imported into the input end of the first trigger FF1.The first trigger FF1 samples to input signal on the rising edge of clock signal clk.Thus, the output signal SR1 of the first trigger FF1 carries out transformation from high to low on the rising edge in last cycle of former frame.And, because this initial pulse VSP is a high level when sampling on the rising edge at the clock signal clk of period 1 of present frame, so the output signal SR1 of the first trigger FF1 carries out transformation from low to high.Therefore, the low-level period from the high level period in last cycle of the former frame of clock signal clk to the period 1 of present frame, this output signal SR1 keeps low level.

The output signal SR1 of the first trigger FF1 is imported into the second trigger FF2, and inversion clock signal/CLK is imported into the input end of clock CK of the second trigger FF2.Thus, the second trigger FF2 samples to the output signal SR1 of the first trigger FF1 on the negative edge of clock signal clk.As a result, transformation from high to low takes place in the output signal SR2 of the second trigger FF2 on the negative edge of the period 1 of clock signal clk, and then transformation from low to high takes place on the negative edge of its second round.

In similarly handling with above-mentioned processing, transformation from high to low takes place in the output signal SR3 of the 3rd trigger FF3 on the rising edge of the period 1 of clock signal clk, and then transformation from low to high takes place on the rising edge of the second round of this clock signal.

And transformation from high to low takes place in the output signal SRm of m trigger FFm on the negative edge in the m/2 cycle of clock signal clk, and on the negative edge of period 1 of next frame transformation from low to high takes place.

In addition, transformation from high to low takes place in the output signal SRm+1 of m+1 trigger on the rising edge in the m/2 cycle of clock signal clk, and on the rising edge of period 1 of next frame transformation from low to high takes place.

When the scanner driver execution was lined by line scan, mode select signal MODE was set to high level.In this case, shown in Fig. 9 A and Fig. 9 B, only when the output signal SRk of trigger of order and SRk+1 were low level, the mode selection circuit of mode selecting unit 420 is the output low level signal.

And odd lines control signal ODD and even lines control signal EVEN are set to low level.Because odd lines control signal ODD is a low level, so the line options circuit of odd lines selected cell 440 selects odd mode to select the output signal out[1 of circuit, 3, ..., m+1], and with this output signal out[1,3 ..., m+1] output to corresponding scanning line.

In addition, because even lines control signal EVEN is a low level, so the line options circuit of even lines selected cell 460 selects even-mode to select the output signal out[2 of circuit, 4, ..., m], and with this output signal out[2,4 ..., m] output to corresponding scanning line.

As mentioned above, only when the output signal of trigger in proper order was low level, mode selection circuit is the output low level signal.So, only when the output signal SR2 of the output signal SR1 of the first trigger FF1 and the second trigger FF2 is low level, the first sweep signal SCAN[1] just be low level.Therefore, during the low-level period of period 1 of clock signal clk, activate this first sweep signal SCAN[1].

Only when the output signal SR3 of the output signal SR2 of the second trigger FF2 and the 3rd trigger FF3 is low level, the second sweep signal SCAN[2] just be low level.Therefore, during the high level period of period 1 of clock signal clk, activate this second sweep signal SCAN[2].And, during the low-level period of the second round of clock signal clk, activate the 3rd sweep signal SCAN[3].

In above-mentioned processing, during each frame period, can activate m sweep signal successively.Thus, during lining by line scan, each sweep signal is sequentially transferred to sweep trace with the differing of half in the cycle of clock signal clk.

With reference to figure 11B, mode select signal MODE is that low level is to carry out staggered scanning.Thus, the mode selection circuit of Fig. 9 A is irrespectively exported high level signal with the output signal of the trigger of order.Therefore, all mode selection circuit output high level output signal out[1,2 ..., m].

And, the output signal SR2 of even-numbered trigger, SR4 ... and SRm conductively-closed during the odd field cycle of scanning odd-numbered scan lines.Similarly, the output signal SR1 of odd-numbered trigger, SR3 ... and SRm-1 conductively-closed during the even field cycle of scanning even-line interlace line.

During the odd field cycle, output signal SR2, the SR4 of low level even lines control signal EVEN shielding even-numbered trigger ... and SRm.During staggered scanning, mode select signal MODE is a low level, makes all output signal out[1 of mode selection circuit, 2 ..., m] all be high level.And, because even lines control signal EVEN is a low level, so the line options circuit of even lines selected cell 460 is selected the output signal out[2 of even-numbered trigger, 4 ..., m].Therefore, even-line interlace signal SCAN[2,4 ..., m] be high level signal.That is, in response to low level even lines control signal EVEN, the line options circuit do not select the even-numbered trigger output signal SR2, SR4 ... and SRm.On the contrary, their conductively-closeds are high level.

During the odd field cycle, odd lines control signal ODD is a high level.The line options circuit of odd lines selected cell 440 select in response to high level odd lines control signal ODD the odd-numbered trigger output signal SR1, SR3 ... and SRm-1.Thus, odd number sweep signal SCAN[1,3 ..., m-1] export with low level successively in response to clock signal clk.

In other words, the first sweep signal SCAN[1] during the period 1 of clock signal clk low level, and the 3rd sweep signal SCAN[3] during its second round low level.And, m-1 sweep signal SCAN[m-1] during the m/2 cycle of clock signal clk, be low level.

During the even field cycle, output signal SR1, the SR3 of low level odd lines control signal ODD shielding odd-numbered trigger ... and SRm-1.Under interleaved situation, mode select signal MODE is a low level, makes all output signal out[1 of mode selection circuit, 2 ..., m] all be high level.And, because odd lines control signal ODD is a low level, so the line options circuit of odd lines selected cell 440 is selected output signal out[1,3 ..., m-1].Therefore, odd number sweep signal SCAN[1,3 ..., m-1] be high level signal.That is, in response to low level odd lines control signal ODD, the line options circuit do not select the odd-numbered trigger output signal SR1, SR3 ... and SRm-1.On the contrary, their conductively-closeds are high level.

In addition, during the even field cycle, even lines control signal EVEN is a high level.The line options circuit of even lines selected cell 460 select in response to high level even lines control signal EVEN the even-numbered trigger output signal SR2, SR4 ... and SRm.Thus, even-line interlace signal SCAN[2,4 ..., m] export with low level successively in response to clock signal clk.

Promptly, the second sweep signal SCAN[2] in the low-level period in (m/2+2) cycle of clock signal clk and the high level period in (m/2+3) cycle thereof, be low level, and the 4th sweep signal SCAN[4] in the low-level period in (m/2+3) cycle of clock signal and the high level period in (m/2+4) cycle thereof, be low level.And, m sweep signal SCAN[m] in the low-level period in (m+1) cycle of clock signal clk and the high level period in (m+2) cycle thereof, be low level.Thus, during the even field cycle, the output signal SR1 of odd-numbered trigger, SR3 ... and the SRm-1 conductively-closed is high level, and the output signal SR2 of even-numbered trigger, SR4 ... and SRm is chosen by the line options circuit and exports as sweep signal.

In above-mentioned processing, when scanner driver is carried out staggered scanning, odd number sweep signal SCAN[1,3, ..., m-1] form successively by the combination of mode select signal MODE and odd lines control signal ODD, and during the odd field cycle, be transferred to corresponding odd-numbered scan lines.

During the odd field cycle, even-line interlace signal SCAN[2,4 ..., m] conductively-closed and output in response to even lines control signal EVEN.Therefore, during the odd field cycle, even-line interlace signal SCAN[2,4 ..., m] do not have the required data of scan operation and be set to high level.

On the other hand, during the even field cycle, even-line interlace signal SCAN[2,4 ..., m] form successively by the combination of mode select signal MODE and even lines control signal EVEN, and be transferred to corresponding even-line interlace line.

In addition, odd number sweep signal SCAN[1,3 ..., m-1] conductively-closed and output in response to odd lines control signal ODD.Therefore, during the even field cycle, odd number sweep signal SCAN[1,3 ..., m-1] do not have the required data of scan operation and be set to high level.

As mentioned above, can utilize mode select signal MODE, odd lines control signal ODD and even lines control signal EVEN and optionally carry out and line by line scan and staggered scanning.

According to the example embodiment of the invention described above, can optionally carry out and line by line scan and staggered scanning according to the level of odd lines control signal and even lines control signal.

In addition, can utilize mode select signal, odd lines control signal and even lines control signal and the output signal that produces shift register as the sweep signal of lining by line scan or staggered scanning is required.So a scanner driver can be used for optionally enabling to line by line scan and staggered scanning.

Those of ordinary skills should be understood that under the situation that does not break away from the spirit or scope of the present invention, can carry out various modifications and change in the present invention.Thus, interior modification of the present invention and the change of scope that this invention is intended to cover claims and be equal to.

Claims

1. optionally carry out and line by line scan and interleaved scanner driver for one kind, comprising:

Shift register is used to receive initial pulse and clock signal, and every cycle of clock signal and output data;

The odd lines selected cell is used to receive the output signal and the odd lines control signal of the odd-numbered trigger of shift register, and to the signal actuating logic computing that received to produce the odd number sweep signal; With

The even lines selected cell is used to receive the output signal and the even lines control signal of the even-numbered trigger of shift register, and to the signal actuating logic computing that received to produce the even-line interlace signal.

2. according to the scanner driver of claim 1, wherein each trigger comprises:

First latch is used for being stored in the input data that the low-level period of clock signal is sampled on rising edge of clock signal; With

Second latch is used for being stored on the negative edge of clock signal the data of storing in first latch that the high level period of clock signal samples.

3. according to the scanner driver of claim 2, wherein first latch comprises:

First sampling thief is used for the low-level period sampled input signal in clock signal; With

First retainer is used for the output signal at high level period maintenance first sampling thief of clock signal.

4. according to the scanner driver of claim 3, wherein second latch comprises:

Second sampling thief is used for the output signal at high level period sampling first retainer of clock signal; With

Second retainer is used for the output signal at low-level period maintenance second sampling thief of clock signal.

5. according to the scanner driver of claim 2, wherein this odd lines selected cell comprises a plurality of Sheffer stroke gates, and each Sheffer stroke gate receives the output signal and the odd lines control signal of odd-numbered trigger.

6. according to the scanner driver of claim 5, wherein this even lines selected cell comprises a plurality of Sheffer stroke gates, and each Sheffer stroke gate receives the output signal and the even lines control signal of even-numbered trigger.

7. according to the scanner driver of claim 6, wherein this scanner driver is optionally carried out and is lined by line scan and staggered scanning according to the level of even lines control signal and odd lines control signal.

8. according to the scanner driver of claim 7, wherein when even lines control signal and odd lines control signal all were high level, this scanner driver was carried out and is lined by line scan.

9. scanner driver according to Claim 8, wherein this odd lines selected cell and even lines selected cell make the output signal that is received of trigger anti-phase.

10. according to the scanner driver of claim 9, wherein each in even lines control signal and the odd lines control signal is converted to low level pulse train type signal during being included in each cycle of clock signal.

11. scanner driver according to claim 7, wherein when carrying out staggered scanning, the Sheffer stroke gate of odd lines selected cell with half corresponding odd field cycle in frame period during make the output signal that is received of odd-numbered trigger anti-phase, and the Sheffer stroke gate of even lines selected cell with half corresponding even field cycle of residue in frame period during make the output signal that is received of even-numbered trigger anti-phase.

12. according to the scanner driver of claim 11, wherein when the odd lines control signal be high level and even lines control signal when being low level, the odd lines selected cell activates this odd number sweep signal during the odd field cycle.

13. according to the scanner driver of claim 12, wherein this odd lines control signal is converted to low level pulse train type signal during being included in each cycle of the clock signal during the odd field cycle.

14. according to the scanner driver of claim 12, wherein when the odd lines control signal be low level and even lines control signal when being high level, the even lines selected cell activates this even-line interlace signal during the even field cycle.

15. according to the scanner driver of claim 14, wherein this even lines control signal is converted to low level pulse train type signal during being included in each cycle of the clock signal during the even field cycle.

16. a display comprises:

Pel array comprises a plurality of pixels;

Scanner driver is used for sweep signal and emissioning controling signal are transferred to this pel array, and optionally carries out and line by line scan and staggered scanning; With

Data driver is used for the sweep signal selected pixel of data transmission to scanner driver,

Wherein this scanner driver comprises:

17. according to the display of claim 16, wherein each trigger comprises:

18. according to the display of claim 17, wherein first latch comprises:

19. according to the display of claim 18, wherein second latch comprises:

20. according to the display of claim 17, wherein this odd lines selected cell comprises a plurality of Sheffer stroke gates, each Sheffer stroke gate receives the output signal and the odd lines control signal of odd-numbered trigger.

21. according to the display of claim 20, wherein this even lines selected cell comprises a plurality of Sheffer stroke gates, each Sheffer stroke gate receives the output signal and the even lines control signal of even-numbered trigger.

22. according to the display of claim 21, wherein this scanner driver is optionally carried out and is lined by line scan and staggered scanning according to the level of even lines control signal and odd lines control signal.

23. according to the display of claim 22, wherein when even lines control signal and odd lines control signal all were high level, this scanner driver was carried out and is lined by line scan.

24. according to the display of claim 23, wherein each in even lines control signal and the odd lines control signal is converted to low level pulse train type signal during being included in each cycle of clock signal.

25. according to the display of claim 22, wherein when the odd lines control signal be high level and even lines control signal when being low level, the odd lines selected cell with half corresponding odd field cycle in frame period during activate this odd number sweep signal, and

Wherein when the odd lines control signal be low level and even lines control signal when being high level, the even lines selected cell with half corresponding even field cycle of residue in frame period during activate this even-line interlace signal.

26. according to the display of claim 25, wherein this odd lines control signal is converted to low level pulse train type signal during being included in each cycle of the clock signal during the odd field cycle, and

This even lines control signal is converted to low level pulse train type signal during being included in each cycle of the clock signal during the even field cycle.

27. according to the display of claim 16, wherein this display is display of organic electroluminescence, LCD or plasma display panel.

28. optionally carry out and line by line scan and interleaved scanner driver for one kind, comprising:

Shift register is used to receive initial pulse and clock signal, and every half and the output data in cycle of clock signal;

Mode selecting unit is used to receive the output signal of the trigger of shift register, and in response to mode select signal to the output signal actuating logic computing of trigger;

The odd lines selected cell is used for selecting the output signal of odd-numbered trigger or the output signal of mode selecting unit in response to the odd lines control signal; With

The even lines selected cell is used for selecting the output signal of even-numbered trigger or the output signal of mode selecting unit in response to the even lines control signal.

29. according to the scanner driver of claim 28, wherein:

This shift register comprises a plurality of triggers of series connection;

The odd-numbered trigger of shift register is at rising edge of clock signal up-sampling input signal, and the output input signal of being sampled; With

The even-numbered trigger of shift register is at the negative edge up-sampling input signal of clock signal, and the output input signal of being sampled.

30. according to the scanner driver of claim 29, wherein each odd-numbered trigger comprises:

First sampling thief is used for the high level period sampled input signal in clock signal; With

First retainer is used for the output signal at low-level period maintenance first sampling thief of clock signal.

31. according to the scanner driver of claim 30, wherein each even-numbered trigger comprises:

Second sampling thief is used for the low-level period sampled input signal in clock signal; With

Second retainer is used for the output signal at high level period maintenance second sampling thief of clock signal.

32. according to the scanner driver of claim 28, wherein this mode selecting unit comprises:

Rejection gate is used to receive the output signal of odd-numbered trigger and the output signal of even-numbered trigger, and described even-numbered trigger is adjacent with described odd-numbered trigger; With

Sheffer stroke gate is used to receive the output signal and the mode select signal of rejection gate.

33. according to the scanner driver of claim 32, wherein during lining by line scan, this mode selecting unit is to the output signal of odd-numbered trigger and the output signal actuating logic exclusive disjunction of even-numbered trigger, and

During staggered scanning, this mode selecting unit shields the output signal of odd-numbered trigger and the output signal of even-numbered trigger by the output high level signal.

34. according to the scanner driver of claim 28, wherein this odd lines selected cell comprises:

First Sheffer stroke gate is used to receive the output signal and the odd lines control signal of odd-numbered trigger;

Second Sheffer stroke gate is used to receive the output signal of the mode selecting unit corresponding with the output signal of mode select signal and odd-numbered trigger and the inversion signal of odd lines control signal; With

The 3rd Sheffer stroke gate is used to receive the output signal of first Sheffer stroke gate and the output signal of second Sheffer stroke gate.

35. according to the scanner driver of claim 34, wherein when this odd lines control signal is high level, this odd lines selected cell select the odd-numbered trigger output signal and

When this odd lines control signal is low level, the output signal of the mode selecting unit that this odd lines selected cell selection is corresponding with the output signal of mode select signal and odd-numbered trigger.

36. according to the scanner driver of claim 35, wherein this even lines selected cell comprises:

The 4th Sheffer stroke gate is used to receive the output signal and the even lines control signal of even-numbered trigger;

The 5th Sheffer stroke gate is used to receive the output signal of the mode selecting unit corresponding with the output signal of mode select signal and even-numbered trigger and the inversion signal of even lines control signal; With

The 6th Sheffer stroke gate is used to receive the output signal of the 4th Sheffer stroke gate and the output signal of the 5th Sheffer stroke gate.

37. according to the scanner driver of claim 36, wherein when this even lines control signal was high level, this even lines selected cell was selected the output signal of even-numbered trigger, and

When this even lines control signal is low level, the output signal of the mode selecting unit that this even lines selected cell selection is corresponding with the output signal of mode select signal and even-numbered trigger.

38. optionally carry out and line by line scan and interleaved scanner driver for one kind, comprising:

Shift register, the a plurality of triggers that comprise series connection, wherein the odd-numbered trigger is also exported the signal of being sampled at rising edge of clock signal up-sampling input signal, and the signal that the even-numbered trigger is sampled in the negative edge up-sampling input signal and the output of clock signal;

Mode selecting unit is used in response to mode select signal the output signal to the output signal actuating logic exclusive disjunction or the shielding trigger of adjacent trigger;

39. according to the scanner driver of claim 38, wherein each odd-numbered trigger comprises:

40. according to the scanner driver of claim 39, wherein each even-numbered trigger comprises:

41. scanner driver according to claim 38, wherein when mode select signal need be lined by line scan, this mode selecting unit is to the output signal actuating logic exclusive disjunction of adjacent trigger, and when mode select signal needs staggered scanning, the output signal of this mode selecting unit shielding trigger.

42. according to the scanner driver of claim 41, wherein during lining by line scan, the result of the logical OR computing of each the preference pattern selected cell in odd lines selected cell and the even lines selected cell.

43. scanner driver according to claim 41, wherein during staggered scanning, the odd lines selected cell with half corresponding odd field cycle in frame period during select the output signal of odd-numbered trigger, and the output signal of the shielding of even lines selected cell preference pattern selected cell.

44. scanner driver according to claim 43, wherein with half corresponding even field cycle of residue in frame period during, the output signal of the shielding of this odd lines selected cell preference pattern selected cell, and this even lines selected cell is selected the output signal of even-numbered trigger.