US20060115932A1 - Method for fabricating semiconductor components with conductive vias - Google Patents

Method for fabricating semiconductor components with conductive vias Download PDF

Info

Publication number
US20060115932A1
US20060115932A1 US11332929 US33292906A US2006115932A1 US 20060115932 A1 US20060115932 A1 US 20060115932A1 US 11332929 US11332929 US 11332929 US 33292906 A US33292906 A US 33292906A US 2006115932 A1 US2006115932 A1 US 2006115932A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
method
substrate
forming
conductive member
side
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11332929
Inventor
Warren Farnworth
Alan Wood
David Hembree
Original Assignee
Farnworth Warren M
Wood Alan G
Hembree David R
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486Via connections through the substrate with or without pins
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • H05K1/112Pads for surface mounting, e.g. lay-out directly combined with via connections
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • H01L2224/05009Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05569Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/0557Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009Pre-treatment of the connector or the bonding area
    • H01L2224/8203Reshaping, e.g. forming vias
    • H01L2224/82035Reshaping, e.g. forming vias by heating means
    • H01L2224/82039Reshaping, e.g. forming vias by heating means using a laser
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06541Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0102Calcium [Ca]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01022Titanium [Ti]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01027Cobalt [Co]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01032Germanium [Ge]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01039Yttrium [Y]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01042Molybdenum [Mo]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01073Tantalum [Ta]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01074Tungsten [W]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01077Iridium [Ir]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01087Francium [Fr]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12042LASER
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/09472Recessed pad for surface mounting; Recessed electrode of component
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/0959Plated through-holes or plated blind vias filled with insulating material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Other shape and layout details not provided for in H05K2201/09009 - H05K2201/09209; Shape and layout details covering several of these groups
    • H05K2201/09827Tapered, e.g. tapered hole, via or groove
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09818Other shape and layout details not provided for in H05K2201/09009 - H05K2201/09209; Shape and layout details covering several of these groups
    • H05K2201/09845Stepped hole, via, edge, bump or conductor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0026Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0029Etching of the substrate by chemical or physical means by laser ablation of inorganic insulating material
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0026Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032Etching of the substrate by chemical or physical means by laser ablation of organic insulating material

Abstract

A method for fabricating semiconductor components and interconnects includes the steps of providing a substrate, such as a semiconductor die, forming external contacts on opposing sides of the substrate by laser drilling vias through the substrate, and forming conductive members in the vias. The conductive members include enlarged terminal portions that are covered with a non-oxidizing metal. The method can be used to fabricate stackable semiconductor packages having integrated circuits in electrical communication with the external contacts. The method can also be used to fabricate interconnects for electrically engaging packages, dice and wafers for testing or for constructing electronic assemblies.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a division of Ser. No. 10/998,269 filed Nov. 26, 2004, which is a division of Ser. No. 10/316,349 filed Dec. 11, 2002, U.S. Pat. No. 6,903,442, which is a division of Ser. No. 10/035,355 filed Jan. 4, 2002, U.S. Pat. No. 6,620,731, which is a continuation-in-part of Ser. No. 09/961,646 filed Sep. 25, 2001, U.S. Pat. No. 6,833,613, which is a division of Ser. No. 09/385,606 filed Aug. 30, 1999, U.S. Pat. No. 6,294,387, which is a division of Ser. No. 08/993,965 filed Dec. 18, 1997, U.S. Pat. No. 6,107,109.
  • FIELD OF THE INVENTION
  • This invention relates generally to semiconductor manufacture, and specifically to a method for fabricating semiconductor components and interconnects with contacts on opposing sides.
  • BACKGROUND OF THE INVENTION
  • Semiconductor components include external contacts that allow electrical connections to be made from the outside to the integrated circuits contained on the components. A semiconductor die, for example, includes patterns of bond pads formed on the face of the die. Semiconductor packages, such as chip scale packages, also include external contacts. One type of semiconductor package includes solder balls arranged in a dense array, such as a ball grid array (BGA), or fine ball grid array (FBGA).
  • Typically, a component includes only one set of external contacts on either the face side (circuit side) or the back side of the component. However, it is sometimes necessary for a component to have external contacts on both sides. For example, for stacking a semiconductor package to another identical package, external contacts can be formed on the face of the package and on the back side as well. U.S. Pat. No. 6,271,056 to Farnworth et al. discloses this type of stackable package.
  • Interconnects configured to make electrical connections with semiconductor components also include external contacts. A wafer probe card is one type of interconnect adapted to make electrical connections between external contacts on a wafer under test, and test circuitry associated with a wafer handler. Another type of interconnect is adapted to electrically engage unpackaged dice, or chip scale packages, packaged within a test carrier. U.S. Pat. No. 5,541,525 to Wood et al. discloses this type of interconnect and test carrier.
  • In each of these examples, the interconnect includes external contacts for electrically engaging the external contacts on the semiconductor component. With a conventional needle probe card the external contacts comprise probe needles. With an interconnect used with a test carrier as described above, the interconnect contacts can comprise projections formed on a silicon substrate and covered with a conductive layer.
  • As with semiconductor components, the external contacts for an interconnect are often formed on both sides of the interconnect. For example, a probe card can include contacts on its face for electrically engaging the component, and contacts on its back side for electrically engaging spring loaded pins (e.g., “POGO PINS”) in electrical communication with test circuitry. U.S. Pat. No. 6,060,891 to Hembree et al. discloses this type of interconnect.
  • The present invention is directed to a method for fabricating semiconductor components and interconnects with contacts on opposing sides.
  • SUMMARY OF THE INVENTION
  • In accordance with the present invention, a method for fabricating semiconductor components and interconnects is provided. Also provided are improved components and interconnects fabricated using the method, and improved electronic assemblies and test systems incorporating the components and the interconnects.
  • Initially a substrate having a face side, an opposing back side and a plurality of substrate contacts on the face side. For fabricating semiconductor components, such as packages, the substrate can comprise a semiconductor die containing integrated circuits. The substrate contacts can comprise bond pads in electrical communication with the integrated circuits. For fabricating interconnects the substrate can comprise a semiconductor, a ceramic or a plastic. In addition, the substrate contacts can be dummies or omitted entirely.
  • The method also includes the step of forming vias through the substrate using a laser beam directed through the substrate contacts. The method also includes the steps of forming conductive members in the vias, and then forming external contacts on the face side and the back side of the substrate in electrical communication with the conductive members. The external contacts can also include a non-oxidizing layer which facilitates making permanent or temporary electrical connections with the external contacts. The external contacts on the face side and the back side can have matching patterns that allows identical components to be stacked to one another. Alternately the external contacts on the face side and the back side can be offset or redistributed with respect to one another.
  • A semiconductor component, such as a die, a package or a wafer, fabricated using the method, includes the substrate and the external contacts on the face side and the back side. The external contacts on the face side can be bonded to external contacts on the back side of an identical component to make a stacked assembly. An interconnect fabricated using the method includes the external contacts on the face side which can be configured to electrically engage a semiconductor component. The interconnect also includes external contacts on the back side which can be configured to electrically engage electrical connectors associated with test circuitry.
  • In an alternate embodiment of the method, the vias are initially formed as counter bores, and the conductive members are formed in the vias. The substrate is then thinned from the back side using a thinning process, such as chemical mechanical planarization (CMP) or etching, to expose the conductive members.
  • An electronic assembly includes multiple stacked components fabricated using the method. Another electronic assembly includes an interconnect fabricated using the method having semiconductor components attached to opposing sides. A test system for testing singulated components, such as dice and packages, includes a die level interconnect mounted to a test carrier configured to temporarily package the components. A test system for testing wafers, or other substrates containing multiple components, includes a wafer level interconnect mounted to a test apparatus such as a wafer prober.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1A-1G are schematic cross sectional views illustrating a method for fabricating semiconductor components and interconnects on a substrate in accordance with the invention;
  • FIG. 2A is a top view taken along line 2A-2A of FIG. 1B illustrating a substrate contact on the substrate;
  • FIG. 2B is a top view taken along line 2B-2B of FIG. 1D illustrating the substrate contact following an etching step but prior to a laser drilling step;
  • FIG. 2C is a top view taken along line 2C-2C of FIG. 1D illustrating the substrate contact following the laser drilling step;
  • FIGS. 3A-3F are schematic cross sectional views illustrating an alternate embodiment method for fabricating semiconductor components and interconnects;
  • FIG. 4A is a schematic side elevation view illustrating an electronic assembly fabricated using stackable components fabricated using the method;
  • FIG. 4B is a plan view taken along line 4B-4B of FIG. 4A;
  • FIG. 5A is a schematic cross sectional view illustrating an electronic assembly that includes an interconnect fabricated using the method;
  • FIG. 5B is a cross sectional view taken along section line 5B-5B of FIG. 5A;
  • FIG. 6 is a schematic cross sectional view illustrating a test system that includes an interconnect fabricated using the method;
  • FIGS. 7A and 7B are schematic perspective views illustrating a test system that includes a die level interconnect fabricated using the method;
  • FIG. 7C is an enlarged cross sectional view taken along section line 7C-7C of FIG. 7B;
  • FIG. 8 is a schematic view illustrating a test system that includes a wafer level interconnect fabricated using the method;
  • FIG. 9 is a schematic side elevation view illustrating an electronic assembly fabricated using stackable components fabricated using the method;
  • FIG. 10A is a schematic side elevation view illustrating an electronic assembly fabricated using stackable components fabricated using the method; and
  • FIG. 10B is a plan view taken along line 10B-10B of FIG. 10A.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • As used herein, the term “semiconductor component” means an electronic component that includes a semiconductor die. Exemplary semiconductor components include bare semiconductor dice, chip scale packages, ceramic or plastic semiconductor packages, BGA devices, semiconductor wafers, and panels and leadframes containing multiple dice or chip scale packages.
  • An “interconnect” means an electronic component configured to make electrical connections with a semiconductor component. A die level interconnect can be configured to electrically engage singulated components such as a die or a package. A wafer level interconnect can be configured to electrically engage a substrate, such as a wafer, a panel, or a leadframe, containing multiple components.
  • Referring to FIGS. 1A-1G, a method for fabricating semiconductor components and interconnects in accordance with the invention is illustrated. Initially as shown in FIG. 1A, a substrate 10 is provided. Preferably, the substrate 10 comprises a wafer of material on which multiple components or interconnects will be fabricated using semiconductor circuit fabrication techniques, and then singulated by cutting the wafer.
  • If the semiconductor component being fabricated is a package, such as a chip scale package, the substrate 10 can comprise a semiconductor die containing a plurality of integrated circuits. The die in turn can be contained on a wafer which includes a plurality of dice which are then singulated into individual packages. Depending on the application, the die can be configured as a memory device, as a vertical cavity surface emitting laser device (VCSEL), or in any other conventional configuration.
  • If the semiconductor component being fabricated is an interconnect, the substrate can comprise a semiconductor material such as monocrystalline silicon, germanium, silicon-on-glass, or silicon-on-sapphire. These materials have a TCE (thermal coefficient of expansion) that matches, or is close to, the TCE of the mating semiconductor component which the interconnect engages. Alternately, the substrate 10 can comprise a ceramic material, such as mullite, or a plastic material, such as a glass filled resin (e.g., FR-4).
  • The substrate 10 includes a face side 14 (“first side” in the claims) and an opposing back side 16 (“second side” in the claims). The face side 14 and the back side 16 are the major planar surfaces of the substrate 10, and are generally parallel to one another. A representative thickness of the substrate 10 can be from about 12 mils to 38 mils. A peripheral size and shape of the substrate 10 can be selected as required. For example, semiconductor dice have generally rectangular or square peripheral shapes.
  • As shown in FIG. 1A, the substrate 10 can include substrate contacts 18, and a front side insulating layer 20. The substrate contacts 18 are formed of a highly conductive metal such as aluminum, titanium, nickel, iridium, copper, gold, tungsten, silver, platinum, palladium, tantalum, molybdenum or alloys of these metals. If the substrate 10 is a semiconductor die, the substrate contacts 18 can be the device bond pads, or alternately redistribution layer pads, in electrical communication with the integrated circuits contained on the die.
  • If an interconnect is being fabricated, the substrate contacts 18 can be dummy contacts, or can be omitted entirely. As shown in FIG. 2A, the substrate contacts 18 have a generally square peripheral shape. However, other shapes such as rectangular, circular or oval can also be employed. A size of the substrate contacts 18 can also be selected as required (e.g., 10-100 μm on a side).
  • The front side insulating layer 20 can comprise an electrically insulating material deposited to a desired thickness using a suitable deposition process (e.g., CVD, sputtering, spin-on). Exemplary materials include glass materials such as BPSG, oxide materials, such as SiO2, or polymer materials, such as polyimide. If the substrate 10 is a die, the front side insulating layer 20 can be the outer passivation layer for the die. A thickness for the front side insulating layer 20 will be dependent on the material. For example oxide materials can be deposited to thicknesses of 500 Å or less, and polymer materials can be deposited to thicknesses of several mils or more.
  • As shown in FIG. 1B, a back side insulating layer 22 is blanket deposited on the back side 16 of the substrate 10. The purpose of the back side insulating layer 22 is to provide electrical insulation for the back side 16. The back side insulating layer 22 can be formed of the same materials as previously described for the front side insulating layer 22 using a suitable deposition process (e.g., CVD, sputtering, spin-on).
  • As shown in FIG. 1C, a front side protective mask 24 is formed on the front side insulating layer 20, and a back side protective mask 26 is formed on the back side insulating layer 22. Preferably the protective masks 24, 26 comprise a photoimageable material, such as a photoresist, or a photoimageable polymer, such as polyimide. The protective masks 24, 26 can be deposited using a suitable deposition process such as spin-on and then soft baked to drive out solvents. Depending on the material, a representative thickness for the protective masks 24, 26 can be from 10,000 Å to 50 Åm. Following the softbake, the front side protective mask 24 is aligned with a mask and exposed using UV light.
  • As shown in FIG. 1D, the front side protective mask 24 is developed to form openings 28 aligned with the substrate contacts 18. The substrate contacts 18 are then etched such that the openings 28 also extend through the substrate contacts 18 to the substrate 10. Depending on the material for the substrate contacts 18 a wet etchant can be used to etch the substrate contacts 18. For example, for substrate contacts 18 made of aluminum, one suitable wet etchant is H3PO4.
  • FIG. 2B illustrates the mask 24 and the substrate contacts 18 following the etching step but prior to a laser drilling step. As shown in FIG. 2B, the openings 28 in the mask 24 and in the substrate contacts 18 are generally circular, and are smaller in diameter than the width of the substrate contacts 18. The substrate contacts 18 thus have metal around their peripheries but no metal in the center. In the illustrative embodiment the openings 28 have a diameter that is about half the width of the substrate contacts 18. In addition, the openings 28 surround a portion of the substrate 10, such that the substrate contacts 18 and the openings 28 form targets, or bullseyes, for a subsequent laser drilling step in which a laser beam 33 (FIG. 1D) is directed at the openings 28 and through the substrate 10. The laser beam 33 (FIG. 1D) initially pierces the substrate 10 on the portions of the substrate 10 surrounded by the openings 28.
  • As shown in FIG. 1D, the laser drilling step forms lasered openings 29 through the substrate 10, through the back side insulating layer 22 and through the back side protective mask 26. FIG. 2C illustrates the mask 24 and the substrate contacts 18 following the laser drilling step. As shown in FIG. 2C, the lasered openings 29 do not touch the metal of the substrate contacts 18, as they are located in the middle of the openings 28 in the substrate contacts 18. In the illustrative embodiment, the lasered openings 29 have diameters that are about half the diameters of the openings 28. The laser beam 33 (FIG. 1D) thus initially contacts and pierces the substrate 10 without having to contact and pierce the metal that forms the substrate contacts 18. This eliminates shorting between the completed external contacts 38 (FIG. 1G) and the substrate 10 because any conducting or semiconducting material redeposited by penetration of the laser beam 33 will not contact the external contacts 38.
  • Following the laser drilling step, a cleaning step can be performed in which the lasered openings 29 are cleaned using a suitable wet or dry etchant. One suitable wet etchant for cleaning the lasered openings 29 with the substrate 10 comprising silicon is tetramethylammoniumhydroxide (TMAH).
  • As shown in FIG. 1E, the cleaning step forms vias 30 which extend through the substrate 10, through the back side insulating layer 22, and through the back side protective mask 26. In the illustrative embodiment the vias have diameters that are about twice the inside diameters of the lasered openings 29, and about equal to the inside diameters of the openings 28. By way of example, the diameters of the vias 30 can be from 10 μm to 2 mils or greater.
  • A suitable laser system for performing the laser drilling step is manufactured by Electro Scientific, Inc., of Portland, Oreg. and is designated a Model No. 2700. A representative laser fluence for forming the vias 30 through a silicon substrate having a thickness of about 28 mils, is from 2 to 10 watts/per opening at a pulse duration of 20-25 ns, and at a repetition rate of up to several thousand per second. The wavelength of the laser beam can be a standard UV wavelength (e.g., 455 nm).
  • As shown in FIG. 1E, the vias 30 are preferably generally perpendicular to the face side 14, and to the back side 16 of the substrate 10. In addition, the vias 30 are located along a longitudinal axis 31 which preferably extends through the centers of the openings 28 in the front side protective mask 24 and the substrate contacts 18. The openings 28 and the substrate contacts 18 thus provide targets for aligning the laser beam. In addition, the openings 28 help to compensate for misalignment of the laser beam because the openings 28 will subsequently determine the peripheral shape of the external contacts 38 (FIG. 1G). Further, during the laser drilling step the protective masks 24, 26 protect the face side 14 and the back side 16 of the substrate 10.
  • As also shown in FIG. 1E, following formation of the vias 30, insulating layers 32 can be formed on the inside surfaces of the vias 30. The insulating layers 32 electrically insulate the vias 30 from the rest of the substrate 10, and are required if the substrate 10 comprises a semiconductor material. The insulating layers 32 can be a grown or deposited material.
  • With the substrate 10 comprising silicon, the insulating layers 32 can be an oxide, such as SiO2, formed by a growth process by exposure of the substrate 10 to an O2 atmosphere at an elevated temperature (e.g., 950° C). In this case the insulating layers 32 do not completely close the vias 30, but form only on the sidewalls of the vias 30. Alternately, the insulating layers 32 can comprise a deposited electrically insulating material, such as an oxide or a nitride, deposited using a deposition process such as CVD.
  • The insulating layers 32 can also comprise a polymer material deposited using a suitable deposition process such as screen printing. In this case, if the insulating material completely fills the vias 30, a subsequent laser drilling step, substantially as previously described, may be required to re-open the vias 30. If the substrate 10 comprises an electrically insulating material, such as ceramic, or a glass filled resin, such as FR-4, the insulating layers 32 are not required.
  • Following formation of the insulating layers 32, conductive members 34 (FIG. 1G) can be formed within the vias 30. The conductive members 34 can be plugs that completely fill the vias 30, or alternately, can be layers that cover just the inside surfaces or sidewalls of the vias 30. The conductive members 34 can comprise a highly conductive metal, such as aluminum, titanium, nickel, iridium, copper, gold, tungsten, silver, platinum, palladium, tantalum, molybdenum or alloys of these metals. The above metals can be deposited within the openings 28 using a deposition process, such as electroless deposition, CVD, or electrolytic deposition. Alternately a solder metal can be screen printed in the vias 30 and drawn into the vias 30 with capillary action. A solder metal can also be drawn into the vias 30 using a vacuum system and a hot solder wave.
  • Rather than being a metal, the conductive members 34 can comprise a conductive polymer, such as a metal filled silicone, or an isotropic epoxy. Suitable conductive polymers are sold by A.I. Technology, Trenton, N.J.; Sheldahl, Northfield, Minn.; and 3M, St. Paul, Minn. A conductive polymer can be deposited within the vias 30, as a viscous material, and then cured as required. A suitable deposition process, such as screen printing, or stenciling, can be used to deposit the conductive polymer into the vias 30.
  • In the embodiment illustrated in FIGS. 1A-1G, the conductive members 34 are formed by an electroless deposition process. To perform the electroless deposition process, a seeding step is performed in which the substrate 10, with the protective masks 24, 26 thereon, is dipped in a seed solution. Seed solutions for electroless deposition of various metals ate known to those skilled in the art. For example, for depositing copper conductive members 34 the seed solution can comprise a copper sulfate solution available from Shipley. The seed solution adheres to all exposed surfaces including on the protective masks 24, 26 and in the openings 28.
  • As shown in FIG. 1F, following the seeding step, a stripping step is performed in which the protective masks 24, 26 are stripped. Depending on the material for the masks 24, 26, the stripping step can be performed using a suitable stripper or solvent. For example, acetone and methylethylketone can be used for a positive resist, and a solution of H2SO4 and H2O2 can be used for a negative resist. However, the stripper must be selected to not attack the seed solution which adheres to the sidewalls of the vias 30.
  • Next, as shown in FIG. 1G, an electroless deposition step is performed in which a metal is electrolessly deposited into the vias 30 to form the conductive members 34. The electroless deposition step can be performed by dipping the substrate 10 in a suitable electroless deposition solution. For example, for depositing copper conductive members 34, the electroless deposition solution can comprise a nickel hypophosphate solution available from Shipley or Packaging Technology of Nauen, Germany.
  • As shown in FIG. 1G, the electroless deposition step forms the conductive members 34 with generally concave terminal portions 36 (dish shaped buttons) on the insulating layers 20, 22. As will be further explained, the concave terminal portions 36 facilitate making electrical connections with bumped contacts, such as solder balls or bumps. The conductive members 34 are also in electrical communication with the substrate contacts 18. In addition, the conductive members 34 at least partially fill the vias 30, and physically contact the substrate contacts 18.
  • As also shown in FIG. 1G, following formation of the conductive members 34, non-oxidizing metal layers 42 are formed on the concave terminal portions 36 of the conductive members 34. The non-oxidizing metal layers 42 can be formed using a suitable deposition process such as electroless deposition or CVD. With electroless deposition, a mask is not required, as the substrate 10 is dipped into a suitable solution and deposition onto the terminal portions 36 occurs as previously described. With CVD, a mask (not shown) can be formed on the insulating layers 20, 22, having openings aligned with the terminal portions 36 of the conductive members 34. The non-oxidizing metal can then be deposited through the openings to a desired thickness.
  • Suitable metals for the non-oxidizing metal layers 42 include gold, platinum, and palladium. A representative thickness for the non-oxidizing metal layers 42 can be from 600 Å to 3000 Å or more. In addition, the non-oxidizing metal layers 42 have a concave shape substantially similar to that of the concave terminal portions 36. Following the depositing of the non-oxidizing metal layers 42 the substrate 10 can be singulated into individual components or interconnects if required using a suitable process such as sawing, shearing, punching or etching.
  • As shown in FIG. 1G, the face side insulating layer 20 on the face side 14 of the substrate 10 includes face side external contacts 38 (“first external contacts” in the claims). The back side insulating layer 22 on the back side 16 of the substrate 10 includes back side external contacts 40 (“second external contacts” in the claims).
  • The size and spacing of the face side external contacts 38 matches the size and the spacing of the back side external contacts 40, such that each face side external contact 38 has a mating back side external contact 40 located along a common longitudinal axis 31 (FIG. 1E). Stated differently, the face side external contacts 38 and the back side external contacts 40 have matching patterns such as a dense grid array. As will be further explained, alternately the back side external contacts 40 can be “offset” or “redistributed” with respect to the face side external contacts 38.
  • The conductive members 34 establish electrical communication between the mating external contacts 38, 40 on the opposing sides of the substrate 10. In addition, the conductive members 34 establish electrical communication between mating external contacts 38, 40 and the substrate contacts 18. If the substrate 10 includes integrated circuits in electrical communication with the substrate contacts 18, the external contacts 38, 40 are also in electrical communication with the integrated circuits. Referring to FIGS. 3A-3F, an alternate embodiment method for fabricating semiconductor components and interconnects is illustrated. Initially, as shown in FIG. 3A, a substrate 10A is provided having a front side 14A, a back side 16A, substrate contacts 18A and a front side insulating layer 20A as previously described.
  • As shown in FIG. 3B, a front side protective mask 24A is formed on the front side 14A of the substrate 10A. The mask 24A is then used to etch openings 28A in the substrate contacts 18A as previously described. In addition, lasered openings 29A are formed in the substrate 10A by directing a laser beam 33A through the substrate 10A as previously described. However, in this case the laser drilling step is performed such that the laser openings 29A are counter bores that do not extend completely through the substrate 10A. For forming the laser openings 29A, parameters of the laser system, such as beam power, power distribution, pulse length and pulse duration of the laser beam 33, can be adjusted such that the substrate is not pierced.
  • Next, as shown in FIG. 3C, a cleaning step is performed in which the lasered openings 29A are cleaned and enlarged as previously described to form vias 30A. Again the vias 30A are counter bores that do not extend completely through the substrate 10A. As also shown in FIG. 3C, insulating layers 32A are formed in the vias 30A as previously described.
  • Next, as shown in FIG. 3D, conductive members 34A are formed in the vias 30A. The conductive members 34A can comprise a metal or a conductive polymer deposited as previously described using a deposition process such as CVD or screen printing. However, in this case the mask 24A is retained, and the conductive members 34A are also formed in the openings 28A and have surfaces generally planar to a surface of the mask 24A.
  • Next, as shown in FIG. 3E, the mask 24A is stripped as previously described. In addition, a thinning step is performed in which the substrate 10A is thinned from the back side 16A to form a thinned substrate 10A-T. In addition, the thinning step is controlled to planarize and expose the conductive members 34A on a thinned back side 16A-T of the thinned substrate 10A-T. One process for performing the thinning step is chemical mechanical planarization (CMP). One suitable CMP apparatus for performing the thinning step is a Model 372 manufactured by Westech. The thinning step can also be performed by etching the back side 16A of the substrate 10A using a suitable etchant.
  • Next, as shown in FIG. 3F, non-oxidizing layers 42A are formed on the conductive members 34A, as previously described. However, unless the substrate 10 comprises an electrically insulating material such as ceramic or plastic, the non-oxidizing layers 42A on the thinned back side 16A-T must only contact the conductive members 34A and insulating layers 32A. The completed front side external contacts 38A and back side external contacts 40A function substantially as previously described.
  • Referring to FIGS. 4A and 4B, an electronic assembly 52 constructed using stackable components 54-1, 54-2 fabricated in accordance with the method of the invention are illustrated. In this embodiment, the stackable components 54-1, 54-2 are in the form of singulated packages having a chip scale configuration. However, it is to be understood that the stackable components 54-1, 54-2 can also comprise stackable semiconductor dice, stackable semiconductor wafers or stackable panels. In addition, although only two components 54-1, 54-2 form the assembly 52, it is to be understood that any number of stackable components can be utilized.
  • In addition to the stackable components 54-1, 54-2, the electronic assembly 52 includes a supporting substrate 56, such as a printed circuit board or multi chip module substrate, having a plurality of metal electrodes 58. The stackable components 54-1, 54-2 are stacked to one another with the back side external contacts 40 on the lowermost component 54-1 bonded to the electrodes 58 on the supporting substrate 56. In addition, the front side external contacts 38 on the lowermost component 54-1 are bonded to the back side external contacts 40 on the uppermost component 54-2. The external contacts 38, 40 can be bonded to one another by heating and reflowing the metal of the external contacts 38, 40. Alternately, solder and a solder reflow process can be used to bond the external contacts 38, 40 to one another. In either case the non-oxidizing layers 42 (FIG. 1G) on the external contacts 38, 40 facilitate the bonding process, and prevent the formation or resistance increasing oxide layers.
  • Referring to FIGS. 5A and 5B, an electronic assembly 60 constructed using an interconnect 66 fabricated in accordance with the invention is illustrated. In this embodiment, the electronic assembly 60 is in the form of a multi chip module. The interconnect 66 includes front side external contacts 38 and back side external contacts 40 as previously described. In addition, the interconnect 66 includes conductors 68 in electrical communication with the contacts 38, 40 and edge contacts 70 in electrical communication with the conductors 68.
  • The electronic assembly 60 also includes a semiconductor package 62-1 having bumped contacts 64, such as solder bumps or balls, bonded to the front side external contacts 38 on the interconnect 66. In addition, the electronic assembly 60 includes a semiconductor package 62-2 having bumped contacts 64 bonded to the back side external contacts 40 on the interconnect 66. Again, a reflow process or a soldering process can be used to bond the bumped contacts 64 to the external contacts 38, 40.
  • Referring to FIG. 6, a test assembly 72 constructed using an interconnect 74 fabricated in accordance with the invention is illustrated. The test assembly 72 includes test circuitry 84 configured to generate and apply test signals to a device under test 76. By way of example, the device under test 76 can comprise a die, a package, a wafer or a panel having bumped contacts 78. The test circuitry 84 is in electrical communication with the back side external contacts 40 on the interconnect 74. The front side external contacts 38 establish temporary electrical connections with the device contacts 78.
  • Referring to FIGS. 7A-7C, a die level test system 80 constructed with an interconnect 86 fabricated in accordance with the invention is illustrated. The test system 80 is configured to temporarily package and test multiple semiconductor components 88 such as dice, packages, or BGA devices having bumped contacts 90.
  • The test system 80 includes the interconnect 86 which is configured to electrically engage the bumped contacts 90 on the components 88. The test system 80 also includes an alignment member 92 configured to align the components 88 on the interconnect 86, and a force applying mechanism 94 with elastomeric members 98 configured to bias the components 88 and the interconnect 86 together.
  • The interconnect 86 includes the front side external contacts 38 formed as previously described, and configured to make temporary electrical connections with the bumped contacts 90 on the components 88. In addition, the interconnect 86 includes the back side external contacts 40 formed as previously described but with terminal contacts 96, such as solder balls attached thereto. The terminal contacts 96 are configured for mating electrical engagement with a test apparatus 82, such as a test socket or burn-in board in electrical communication with test circuitry 84. The test circuitry 84 is configured to apply test signals to the integrated circuits contained on the components 88 and to analyze the resultant signals.
  • As shown in FIG. 7B, the force applying mechanism 94 attaches to the alignment member 92 and the interconnect 86, and biases the components 88 and the interconnect 86 together. As shown in FIG. 7C, the alignment member 92 includes tapered alignment openings 100 configured to align the components 88 on the interconnect 86.
  • Referring to FIG. 8, a wafer level test system 102 suitable for testing a wafer sized semiconductor component 104 with bumped contacts 106 is illustrated. By way of example, the semiconductor component 104 can comprise a semiconductor wafer containing bare dice, a wafer or panel containing chip scale packages, a printed circuit board containing semiconductor dice, or an electronic assembly, such as a field emission display containing semiconductor dice.
  • The wafer level test system 102 includes an interconnect 108 constructed as previously described, and mounted to a testing apparatus 110. The testing apparatus 110 includes, or is in electrical communication with test circuitry 84. The testing apparatus 110 also includes a wafer chuck 116 configured to support and move the component 104 in x, y and z directions as required. The testing apparatus 110 can comprise a conventional wafer probe handler, or probe tester, modified for use with the interconnect 108. Wafer probe handlers and associated test equipment are commercially available from Electroglass, Advantest, Teradyne, Megatest, Hewlett-Packard and others. In this system 102, the interconnect 108 takes the place of a conventional probe card.
  • The interconnect 108 includes the previously described front side external contacts 38 configured to establish temporary electrical connections with the bumped contacts 106 on the component 108. In addition, the interconnect 108 includes the previously described back side external contacts 40 configured to electrically engage spring loaded electrical connectors 114 (e.g., “POGO PINS” manufactured by Pogo Instruments, Inc., Kansas City, Kans.) in electrical communication with the testing circuitry 112.
  • Referring to FIG. 9, an electronic assembly 118 constructed using stackable components 54B-1, 54B-2, 54B-3, 54B-4 fabricated in accordance with the method of the invention are illustrated. In this embodiment, the stackable components 54B-1, 54B-2, 54B-3, 54B-4 are in the form of singulated packages having a chip scale configuration substantially similar to the previously described stackable component 54. However, as before stackable semiconductor dice, stackable semiconductor wafers or stackable panels can be employed. In addition, although four components 54B-1, 54B-2, 54B-3, 120-4 form the assembly 118, it is to be understood that any number of stackable components can be utilized.
  • Each stackable component 54B-1, 54B-2, 54B-3, 54B-4 includes face side external contacts 38B and back side external contacts 40B having matching patterns. Each stackable component 54B-1, 54B-2, 54B-3, 54B-4 also includes conductive members 34B formed using a laser machining process as previously described. In addition, the back side external contacts 40B include bumped contacts 120 such as solder balls or bumps attached thereto using a suitable process such as ball bumping, bump deposition or reflow bonding. The bumped contacts 120 and face side external contacts 40B on adjacent components 54B-1, 54B-2, 54B-3, 54B-4 are bonded to one another using a suitable bonding process such as reflow bonding.
  • Referring to FIGS. 10A and 10B, an electronic assembly 122 constructed using stackable components 54C-1, 54C-2, 54C-3, 54C-4 fabricated in accordance with the method of the invention are illustrated. In this embodiment, the stackable components 54C-1, 54C-2, 54C-3, 54C-4 are in the form of singulated packages having a chip scale configuration substantially similar to the previously described stackable component 54. However, as before stackable semiconductor dice, stackable semiconductor wafers or stackable panels can be employed.
  • Each stackable component 54C-1, 54C-2, 54C-3 includes face side external contacts 38C and back side external contacts 40C having matching patterns. Each stackable component 54C-1, 54C-2, 54C-3 also includes conductive members 34C formed using a laser machining process as previously described. In addition, the back side external contacts 40C include bumped contacts 124 such as solder balls or bumps attached thereto using a suitable process such as ball bumping, bump deposition or reflow bonding. The bumped contacts 122 and face side external contacts 40C on adjacent components 54C-1, 54C-2, 54C-3 are bonded to one another using a suitable bonding process such as reflow bonding.
  • Although stackable components 54C-1, 54C-2, 54C-3 have identical configurations, the stackable component 54C-4 has a different configuration. Specifically, the back side external contacts 40C for stackable component 54C-4 are “offset” or “redistributed” with respect to the face side external contacts 38C. As shown in FIG. 10B, redistribution conductors 126 on the back side of the stackable component 54C-4 are in electrical communication with the conductive members 34C and with the back side external contacts 40C. This arrangement allows the back side external contacts 40C to have a different pattern than the face side external contacts 38C. For example, a pitch P1 of the back side external contacts 38C can be greater than a pitch P2 of the face side external contacts 38C. This arrangement can be used to facilitate bonding of the stackable component 54C-4 and thus the assembly 122 to a supporting substrate, such as a printed circuit board.
  • Thus the invention provides a method for fabricating semiconductor components and interconnect for semiconductor components. The invention also provides improved electronic assemblies and test systems constructed using components and interconnects fabricated in accordance with the invention.
  • Although the invention has been described with reference to certain preferred embodiments, as will be apparent to those skilled in the art, certain changes and modifications can be made without departing from the scope of the invention as defined by the following claims.

Claims (40)

  1. 1. A method for fabricating a semiconductor component comprising:
    providing a substrate comprising a first side, a substrate contact on the first side, and an opposing second side;
    forming an opening through the substrate contact;
    forming a via at least partially aligned with the opening through the substrate to the second side; and
    forming a conductive member in the opening and the via in electrical contact with the substrate contact.
  2. 2. The method of claim 1 wherein the forming the conductive member step comprises electroless deposition or electrolytic deposition of a metal into the opening and the via.
  3. 3. The method of claim 1 wherein the forming the conductive member step comprises depositing a conductive polymer into the opening and the via.
  4. 4. The method of claim 1 wherein the forming the opening step comprises etching the substrate contact.
  5. 5. The method of claim 1 wherein the forming the via step comprises laser machining the substrate.
  6. 6. The method of claim 1 wherein the forming the via step comprises etching.
  7. 7. The method of claim 1 further comprising forming an insulating layer on a surface of the via prior to the forming the conductive member step.
  8. 8. The method of claim 1 wherein the conductive member fills the via.
  9. 9. The method of claim 1 wherein the conductive member comprises a layer on a sidewall of the via.
  10. 10. The method of claim 1 wherein the substrate comprises a semiconductor die and the substrate contact comprises a pad in electrical communication with at least one integrated circuit on the substrate.
  11. 11. The method of claim 1 wherein the substrate comprises a semiconductor die and the substrate contact comprises a bond pad or a redistribution pad in electrical communication with at least one integrated circuit on the die.
  12. 12. The method of claim 1 wherein the conductive member comprises a metal, a solder or a conductive polymer.
  13. 13. The method of claim 1 further comprising forming a non oxidizing metal layer on a terminal portion of the conductive member.
  14. 14. The method of claim 1 further comprising forming a first external contact on the first side in electrical communication with the conductive member and a second external contact on the second side in electrical communication with the conductive member.
  15. 15. The method of claim 1 wherein the forming the conductive member step forms generally concave terminal portions on the conductive member.
  16. 16. A method for fabricating a semiconductor component comprising:
    providing a semiconductor substrate comprising a first side, a substrate contact on the first side in electrical communication with an integrated circuit on the substrate, and an opposing second side;
    forming an opening through the substrate contact;
    forming a via at least partially aligned with the opening through the substrate to the second side;
    forming an insulating layer on a surface of the via; and
    forming a conductive material in the opening and the via in electrical contact with the substrate contact.
  17. 17. The method of claim 16 wherein the forming the conductive material step comprises electroless deposition, CVD or electrolytic deposition.
  18. 18. The method of claim 16 wherein the forming the insulating layer step comprises depositing an oxide, a nitride or a polymer material on the surface.
  19. 19. The method of claim 16 further comprising forming a first external contact on the first side in electrical communication with the conductive member and a second external contact on the second side in electrical communication with the conductive member.
  20. 20. The method of claim 16 wherein the substrate contact comprises a bond pad or a redistribution pad.
  21. 21. The method of claim 16 wherein the substrate comprises a plurality of substrate contacts and the forming the opening step forms a plurality of openings, the forming the vias step forms a plurality of vias, the forming the insulating layer step forms a plurality of insulating layers, and the forming the conductive member step forms a plurality of conductive members.
  22. 22. The method of claim 16 wherein the conductive member fills the via.
  23. 23. The method of claim 16 wherein the conductive member comprises a layer on a sidewall of the via.
  24. 24. The method of claim 16 wherein the conductive member comprises a metal, a solder or a conductive polymer.
  25. 25. The method of claim 16 further comprising forming a non oxidizing metal layer on a terminal portion of the conductive member.
  26. 26. The method of claim 16 further comprising forming a first external contact on the first side in electrical communication with the conductive member and a second external contact on the second side in electrical communication with the conductive member.
  27. 27. The method of claim 16 wherein the forming the opening step comprises etching the substrate contact.
  28. 28. The method of claim 16 wherein the forming the via step comprises laser machining the substrate.
  29. 29. The method of claim 16 wherein the forming the via step comprises etching.
  30. 30. A method for fabricating a semiconductor component comprising:
    providing a substrate comprising a first side, a substrate contact on the first side, and an opposing second side;
    forming an opening through the substrate contact;
    forming a via part way through the substrate at least partially aligned with the opening;
    forming a conductive member in the opening and the via in electrical contact with the substrate contact; and
    thinning the substrate from the second side to expose the conductive member.
  31. 31. The method of claim 30 wherein the forming the conductive member step comprises a method selected from the group consisting of electroless deposition, CVD, electrolytic deposition, screen printing, and stenciling.
  32. 32. The method of claim 30 wherein the thinning the substrate step comprises a method selected from the group consisting of planarization, chemical mechanical planarization and etching.
  33. 33. The method of claim 30 wherein the substrate comprises a semiconductor die and the substrate contact comprises a pad in electrical communication with at least one integrated circuit on the substrate.
  34. 34. The method of claim 30 wherein the forming the opening step comprises etching.
  35. 35. The method of claim 30 wherein the forming the via step comprises laser machining and etching.
  36. 36. The method of claim 30 wherein the substrate comprises a semiconductor die and the substrate contact comprises a bond pad or a redistribution pad.
  37. 37. The method of claim 30 further comprising forming a first external contact on the first side in electrical communication with the conductive member.
  38. 38. The method of claim 37 further comprising forming a first non oxidizing layer on the first external contact.
  39. 39. The method of claim 30 further comprising forming a second external contact on the second side in electrical communication with the conductive member.
  40. 40. The method of claim 39 further comprising forming a second non oxidizing layer on the second external contact.
US11332929 1997-12-18 2006-01-17 Method for fabricating semiconductor components with conductive vias Abandoned US20060115932A1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
US08993965 US6107109A (en) 1997-12-18 1997-12-18 Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate
US09385606 US6294837B1 (en) 1997-12-18 1999-08-30 Semiconductor interconnect having laser machined contacts
US09961646 US6833613B1 (en) 1997-12-18 2001-09-25 Stacked semiconductor package having laser machined contacts
US10035355 US6620731B1 (en) 1997-12-18 2002-01-04 Method for fabricating semiconductor components and interconnects with contacts on opposing sides
US10316349 US6903443B2 (en) 1997-12-18 2002-12-11 Semiconductor component and interconnect having conductive members and contacts on opposing sides
US10998269 US20050101037A1 (en) 1997-12-18 2004-11-26 Test system with interconnect having conductive members and contacts on opposing sides
US11332929 US20060115932A1 (en) 1997-12-18 2006-01-17 Method for fabricating semiconductor components with conductive vias

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11332929 US20060115932A1 (en) 1997-12-18 2006-01-17 Method for fabricating semiconductor components with conductive vias

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US10998269 Division US20050101037A1 (en) 1997-12-18 2004-11-26 Test system with interconnect having conductive members and contacts on opposing sides

Publications (1)

Publication Number Publication Date
US20060115932A1 true true US20060115932A1 (en) 2006-06-01

Family

ID=46280239

Family Applications (4)

Application Number Title Priority Date Filing Date
US10035355 Expired - Lifetime US6620731B1 (en) 1997-12-18 2002-01-04 Method for fabricating semiconductor components and interconnects with contacts on opposing sides
US10316349 Expired - Fee Related US6903443B2 (en) 1997-12-18 2002-12-11 Semiconductor component and interconnect having conductive members and contacts on opposing sides
US10998269 Abandoned US20050101037A1 (en) 1997-12-18 2004-11-26 Test system with interconnect having conductive members and contacts on opposing sides
US11332929 Abandoned US20060115932A1 (en) 1997-12-18 2006-01-17 Method for fabricating semiconductor components with conductive vias

Family Applications Before (3)

Application Number Title Priority Date Filing Date
US10035355 Expired - Lifetime US6620731B1 (en) 1997-12-18 2002-01-04 Method for fabricating semiconductor components and interconnects with contacts on opposing sides
US10316349 Expired - Fee Related US6903443B2 (en) 1997-12-18 2002-12-11 Semiconductor component and interconnect having conductive members and contacts on opposing sides
US10998269 Abandoned US20050101037A1 (en) 1997-12-18 2004-11-26 Test system with interconnect having conductive members and contacts on opposing sides

Country Status (1)

Country Link
US (4) US6620731B1 (en)

Cited By (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050090089A1 (en) * 2003-10-22 2005-04-28 Keum-Hee Ma Method for forming solder bump structure
US20070070311A1 (en) * 2005-09-23 2007-03-29 Asml Netherlands B.V. Contacts to microdevices
US20080057691A1 (en) * 2006-08-29 2008-03-06 Dando Ross S Methods and systems for selectively filling apertures in a substrate to form conductive vias with a liquid using a vacuum
US20080116544A1 (en) * 2006-11-22 2008-05-22 Tessera, Inc. Packaged semiconductor chips with array
US20080116545A1 (en) * 2006-11-22 2008-05-22 Tessera, Inc. Packaged semiconductor chips
US20080171413A1 (en) * 2007-01-17 2008-07-17 International Business Machines Corporation Method of Reducing Detrimental STI-Induced Stress in MOSFET Channels
US20090014858A1 (en) * 2007-07-09 2009-01-15 Micron Technology, Inc. Packaged semiconductor assemblies and methods for manufacturing such assemblies
US20090065907A1 (en) * 2007-07-31 2009-03-12 Tessera, Inc. Semiconductor packaging process using through silicon vias
US20090212381A1 (en) * 2008-02-26 2009-08-27 Tessera, Inc. Wafer level packages for rear-face illuminated solid state image sensors
US20100053407A1 (en) * 2008-02-26 2010-03-04 Tessera, Inc. Wafer level compliant packages for rear-face illuminated solid state image sensors
US20100225006A1 (en) * 2007-03-05 2010-09-09 Tessera, Inc. Chips having rear contacts connected by through vias to front contacts
US7829438B2 (en) 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US7952195B2 (en) 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
US8043895B2 (en) 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
US8432045B2 (en) 2010-11-15 2013-04-30 Tessera, Inc. Conductive pads defined by embedded traces
US8431435B2 (en) 2006-10-10 2013-04-30 Tessera, Inc. Edge connect wafer level stacking
US8461672B2 (en) 2007-07-27 2013-06-11 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
US8466542B2 (en) 2009-03-13 2013-06-18 Tessera, Inc. Stacked microelectronic assemblies having vias extending through bond pads
US8551815B2 (en) 2007-08-03 2013-10-08 Tessera, Inc. Stack packages using reconstituted wafers
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US8680662B2 (en) 2008-06-16 2014-03-25 Tessera, Inc. Wafer level edge stacking
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
JP2016058535A (en) * 2014-09-09 2016-04-21 大日本印刷株式会社 Structure and method of manufacturing the same
US20160351473A1 (en) * 2015-05-29 2016-12-01 Kabushiki Kaisha Toshiba Semiconductor device and method for producing semiconductor device
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream

Families Citing this family (144)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6620731B1 (en) * 1997-12-18 2003-09-16 Micron Technology, Inc. Method for fabricating semiconductor components and interconnects with contacts on opposing sides
US6833613B1 (en) * 1997-12-18 2004-12-21 Micron Technology, Inc. Stacked semiconductor package having laser machined contacts
JP2001116795A (en) * 1999-10-18 2001-04-27 Mitsubishi Electric Corp Test socket and connection sheet for use in test socket
US6900534B2 (en) * 2000-03-16 2005-05-31 Texas Instruments Incorporated Direct attach chip scale package
US6943056B2 (en) * 2002-04-16 2005-09-13 Renesas Technology Corp. Semiconductor device manufacturing method and electronic equipment using same
US6762076B2 (en) * 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
CA2484794A1 (en) * 2002-05-23 2003-12-04 Schott Ag Glass material for use at high frequencies
JP3910493B2 (en) * 2002-06-14 2007-04-25 新光電気工業株式会社 Semiconductor device and manufacturing method thereof
US6784544B1 (en) * 2002-06-25 2004-08-31 Micron Technology, Inc. Semiconductor component having conductors with wire bondable metalization layers
US6803303B1 (en) * 2002-07-11 2004-10-12 Micron Technology, Inc. Method of fabricating semiconductor component having encapsulated, bonded, interconnect contacts
US6903442B2 (en) * 2002-08-29 2005-06-07 Micron Technology, Inc. Semiconductor component having backside pin contacts
JP4364514B2 (en) * 2003-01-08 2009-11-18 浜松ホトニクス株式会社 Wiring board, and a radiation detector using the same
JP4322508B2 (en) * 2003-01-15 2009-09-02 新光電気工業株式会社 A method of manufacturing a semiconductor device
WO2004068665A3 (en) * 2003-01-24 2005-09-22 Univ Arkansas Wafer scale packaging technique for sealed optical elements and sealed packages produced thereby
US6852627B2 (en) * 2003-03-05 2005-02-08 Micron Technology, Inc. Conductive through wafer vias
US6841883B1 (en) * 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication
DE10317596A1 (en) * 2003-04-16 2004-11-11 Epcos Ag A process for the production of solder balls on an electrical component
JP3646719B2 (en) * 2003-06-19 2005-05-11 セイコーエプソン株式会社 Semiconductor device and manufacturing method thereof, the circuit board and electronic equipment
US6858475B2 (en) * 2003-06-30 2005-02-22 Intel Corporation Method of forming an integrated circuit substrate
US6984583B2 (en) * 2003-09-16 2006-01-10 Micron Technology, Inc. Stereolithographic method for forming insulative coatings for via holes in semiconductor devices
US7345350B2 (en) * 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
US7101792B2 (en) * 2003-10-09 2006-09-05 Micron Technology, Inc. Methods of plating via interconnects
US7064010B2 (en) * 2003-10-20 2006-06-20 Micron Technology, Inc. Methods of coating and singulating wafers
JP2005150263A (en) * 2003-11-13 2005-06-09 Nitto Denko Corp Double-sided wiring circuit board
US7091124B2 (en) 2003-11-13 2006-08-15 Micron Technology, Inc. Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
US8084866B2 (en) * 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
US7049170B2 (en) * 2003-12-17 2006-05-23 Tru-Si Technologies, Inc. Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities
US7060601B2 (en) * 2003-12-17 2006-06-13 Tru-Si Technologies, Inc. Packaging substrates for integrated circuits and soldering methods
US7316063B2 (en) * 2004-01-12 2008-01-08 Micron Technology, Inc. Methods of fabricating substrates including at least one conductive via
US7282932B2 (en) * 2004-03-02 2007-10-16 Micron Technology, Inc. Compliant contact pin assembly, card system and methods thereof
US20050212144A1 (en) * 2004-03-25 2005-09-29 Rugg William L Stacked die for inclusion in standard package technology
US20050247894A1 (en) 2004-05-05 2005-11-10 Watkins Charles M Systems and methods for forming apertures in microfeature workpieces
US7411303B2 (en) * 2004-11-09 2008-08-12 Texas Instruments Incorporated Semiconductor assembly having substrate with electroplated contact pads
US7179738B2 (en) * 2004-06-17 2007-02-20 Texas Instruments Incorporated Semiconductor assembly having substrate with electroplated contact pads
US7232754B2 (en) 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US9368428B2 (en) * 2004-06-30 2016-06-14 Cree, Inc. Dielectric wafer level bonding with conductive feed-throughs for electrical connection and thermal management
US9601474B2 (en) 2005-07-22 2017-03-21 Invensas Corporation Electrically stackable semiconductor wafer and chip packages
US7135405B2 (en) * 2004-08-04 2006-11-14 Hewlett-Packard Development Company, L.P. Method to form an interconnect
KR100601506B1 (en) * 2004-08-24 2006-07-19 삼성전기주식회사 Method for manufacturing packaging substrate with fine circuit pattern using anodizing
US7598167B2 (en) * 2004-08-24 2009-10-06 Micron Technology, Inc. Method of forming vias in semiconductor substrates without damaging active regions thereof and resulting structures
US7083425B2 (en) 2004-08-27 2006-08-01 Micron Technology, Inc. Slanted vias for electrical circuits on circuit boards and other substrates
US7109068B2 (en) * 2004-08-31 2006-09-19 Micron Technology, Inc. Through-substrate interconnect fabrication methods
US7575999B2 (en) * 2004-09-01 2009-08-18 Micron Technology, Inc. Method for creating conductive elements for semiconductor device structures using laser ablation processes and methods of fabricating semiconductor device assemblies
US7279407B2 (en) * 2004-09-02 2007-10-09 Micron Technology, Inc. Selective nickel plating of aluminum, copper, and tungsten structures
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
JP4246132B2 (en) * 2004-10-04 2009-04-02 シャープ株式会社 Semiconductor device and manufacturing method thereof
US7262495B2 (en) * 2004-10-07 2007-08-28 Hewlett-Packard Development Company, L.P. 3D interconnect with protruding contacts
US7462925B2 (en) * 2004-11-12 2008-12-09 Macronix International Co., Ltd. Method and apparatus for stacking electrical components using via to provide interconnection
US7271482B2 (en) 2004-12-30 2007-09-18 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US20060177999A1 (en) * 2005-02-10 2006-08-10 Micron Technology, Inc. Microelectronic workpieces and methods for forming interconnects in microelectronic workpieces
JP4731191B2 (en) * 2005-03-28 2011-07-20 富士通セミコンダクター株式会社 The method of manufacturing a semiconductor device and a semiconductor device
US7371676B2 (en) * 2005-04-08 2008-05-13 Micron Technology, Inc. Method for fabricating semiconductor components with through wire interconnects
US7502606B2 (en) * 2005-04-11 2009-03-10 Microsoft Corporation Computer-readable medium, method, and device for associating information with a contact
US7393770B2 (en) 2005-05-19 2008-07-01 Micron Technology, Inc. Backside method for fabricating semiconductor components with conductive interconnects
EP1889083B1 (en) * 2005-05-27 2009-11-11 Nxp B.V. Device, system and method for testing and analysing integrated circuits
JP4644882B2 (en) * 2005-05-30 2011-03-09 富士フイルム株式会社 Wiring board manufacturing method, the wiring board, discharge head and an image forming apparatus
US7534722B2 (en) * 2005-06-14 2009-05-19 John Trezza Back-to-front via process
US7687400B2 (en) 2005-06-14 2010-03-30 John Trezza Side stacking apparatus and method
US20070281460A1 (en) * 2006-06-06 2007-12-06 Cubic Wafer, Inc. Front-end processed wafer having through-chip connections
US20060278996A1 (en) * 2005-06-14 2006-12-14 John Trezza Active packaging
US7687397B2 (en) 2006-06-06 2010-03-30 John Trezza Front-end processed wafer having through-chip connections
US7560813B2 (en) * 2005-06-14 2009-07-14 John Trezza Chip-based thermo-stack
US7215032B2 (en) * 2005-06-14 2007-05-08 Cubic Wafer, Inc. Triaxial through-chip connection
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
US20060281303A1 (en) * 2005-06-14 2006-12-14 John Trezza Tack & fuse chip bonding
US7786592B2 (en) 2005-06-14 2010-08-31 John Trezza Chip capacitive coupling
US8154131B2 (en) * 2005-06-14 2012-04-10 Cufer Asset Ltd. L.L.C. Profiled contact
US7838997B2 (en) 2005-06-14 2010-11-23 John Trezza Remote chip attachment
US7781886B2 (en) * 2005-06-14 2010-08-24 John Trezza Electronic chip contact structure
US7851348B2 (en) 2005-06-14 2010-12-14 Abhay Misra Routingless chip architecture
US7521806B2 (en) * 2005-06-14 2009-04-21 John Trezza Chip spanning connection
US7589406B2 (en) * 2005-06-27 2009-09-15 Micron Technology, Inc. Stacked semiconductor component
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7429529B2 (en) * 2005-08-05 2008-09-30 Farnworth Warren M Methods of forming through-wafer interconnects and structures resulting therefrom
JP4758712B2 (en) * 2005-08-29 2011-08-31 新光電気工業株式会社 A method of manufacturing a semiconductor device
US7772115B2 (en) * 2005-09-01 2010-08-10 Micron Technology, Inc. Methods for forming through-wafer interconnects, intermediate structures so formed, and devices and systems having at least one solder dam structure
US7262134B2 (en) 2005-09-01 2007-08-28 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7517798B2 (en) 2005-09-01 2009-04-14 Micron Technology, Inc. Methods for forming through-wafer interconnects and structures resulting therefrom
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US8154105B2 (en) * 2005-09-22 2012-04-10 International Rectifier Corporation Flip chip semiconductor device and process of its manufacture
US7307348B2 (en) * 2005-12-07 2007-12-11 Micron Technology, Inc. Semiconductor components having through wire interconnects (TWI)
US7892972B2 (en) * 2006-02-03 2011-02-22 Micron Technology, Inc. Methods for fabricating and filling conductive vias and conductive vias so formed
US20070212865A1 (en) * 2006-03-08 2007-09-13 Craig Amrine Method for planarizing vias formed in a substrate
US7659612B2 (en) * 2006-04-24 2010-02-09 Micron Technology, Inc. Semiconductor components having encapsulated through wire interconnects (TWI)
US7384819B2 (en) * 2006-04-28 2008-06-10 Freescale Semiconductor, Inc. Method of forming stackable package
US7749899B2 (en) 2006-06-01 2010-07-06 Micron Technology, Inc. Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces
KR100712561B1 (en) * 2006-08-23 2007-04-23 삼성전자주식회사 Wafer type probe card and method for fabricating the same and semiconductor test apparatus having wafer type probe card
US7629249B2 (en) 2006-08-28 2009-12-08 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
EP2074647B1 (en) * 2006-10-17 2012-10-10 Cufer Asset Ltd. L.L.C. Wafer via formation
US7531443B2 (en) * 2006-12-08 2009-05-12 Micron Technology, Inc. Method and system for fabricating semiconductor components with through interconnects and back side redistribution conductors
US20080157322A1 (en) * 2006-12-27 2008-07-03 Jia Miao Tang Double side stacked die package
US7538413B2 (en) * 2006-12-28 2009-05-26 Micron Technology, Inc. Semiconductor components having through interconnects
US7598163B2 (en) * 2007-02-15 2009-10-06 John Callahan Post-seed deposition process
US7705632B2 (en) * 2007-02-15 2010-04-27 Wyman Theodore J Ted Variable off-chip drive
US7670874B2 (en) 2007-02-16 2010-03-02 John Trezza Plated pillar package formation
US7812461B2 (en) * 2007-03-27 2010-10-12 Micron Technology, Inc. Method and apparatus providing integrated circuit having redistribution layer with recessed connectors
US20080237881A1 (en) * 2007-03-30 2008-10-02 Tony Dambrauskas Recessed solder socket in a semiconductor substrate
US7748116B2 (en) * 2007-04-05 2010-07-06 John Trezza Mobile binding in an electronic connection
US7850060B2 (en) * 2007-04-05 2010-12-14 John Trezza Heat cycle-able connection
US20080261392A1 (en) * 2007-04-23 2008-10-23 John Trezza Conductive via formation
US7960210B2 (en) * 2007-04-23 2011-06-14 Cufer Asset Ltd. L.L.C. Ultra-thin chip packaging
US7977155B2 (en) * 2007-05-04 2011-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer-level flip-chip assembly methods
US8586465B2 (en) * 2007-06-07 2013-11-19 United Test And Assembly Center Ltd Through silicon via dies and packages
US7466028B1 (en) * 2007-10-16 2008-12-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor contact structure
US7884015B2 (en) 2007-12-06 2011-02-08 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US8084854B2 (en) 2007-12-28 2011-12-27 Micron Technology, Inc. Pass-through 3D interconnect for microelectronic dies and associated systems and methods
EP2238612B1 (en) * 2008-01-30 2013-03-13 Innovent Technologies, Llc Method and apparatus for manufacture of via disk
US8033012B2 (en) * 2008-03-07 2011-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Method for fabricating a semiconductor test probe card space transformer
US8253230B2 (en) * 2008-05-15 2012-08-28 Micron Technology, Inc. Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
US7863721B2 (en) * 2008-06-11 2011-01-04 Stats Chippac, Ltd. Method and apparatus for wafer level integration using tapered vias
US7968460B2 (en) 2008-06-19 2011-06-28 Micron Technology, Inc. Semiconductor with through-substrate interconnect
JP2010034197A (en) * 2008-07-28 2010-02-12 Fujitsu Ltd Buildup board
US7872332B2 (en) * 2008-09-11 2011-01-18 Micron Technology, Inc. Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods
US8082537B1 (en) 2009-01-28 2011-12-20 Xilinx, Inc. Method and apparatus for implementing spatially programmable through die vias in an integrated circuit
US7989959B1 (en) * 2009-01-29 2011-08-02 Xilinx, Inc. Method of forming stacked-die integrated circuit
US8987868B1 (en) 2009-02-24 2015-03-24 Xilinx, Inc. Method and apparatus for programmable heterogeneous integration of stacked semiconductor die
KR101026489B1 (en) 2009-08-10 2011-04-01 주식회사 하이닉스반도체 Semiconductor package and method of manufacturing the same
US9799562B2 (en) * 2009-08-21 2017-10-24 Micron Technology, Inc. Vias and conductive routing layers in semiconductor substrates
US8907457B2 (en) * 2010-02-08 2014-12-09 Micron Technology, Inc. Microelectronic devices with through-substrate interconnects and associated methods of manufacturing
JP5609144B2 (en) * 2010-02-19 2014-10-22 ソニー株式会社 Method of testing a semiconductor device and the through electrode
US8294265B1 (en) * 2010-03-31 2012-10-23 Amkor Technology, Inc. Semiconductor device for improving electrical and mechanical connectivity of conductive pillers and method therefor
US8324511B1 (en) * 2010-04-06 2012-12-04 Amkor Technology, Inc. Through via nub reveal method and structure
US9015023B2 (en) 2010-05-05 2015-04-21 Xilinx, Inc. Device specific configuration of operating voltage
US8896336B2 (en) * 2010-07-06 2014-11-25 Formfactor, Inc. Testing techniques for through-device vias
JP2012069903A (en) * 2010-08-27 2012-04-05 Elpida Memory Inc Semiconductor device, and method of manufacturing the same
KR101768992B1 (en) * 2010-12-30 2017-08-17 삼성전자주식회사 Probe card and method of testing a semiconductor device
US8617988B2 (en) * 2011-06-06 2013-12-31 Hewlett-Packard Development Company, L.P. Through-substrate vias
US9076664B2 (en) 2011-10-07 2015-07-07 Freescale Semiconductor, Inc. Stacked semiconductor die with continuous conductive vias
US8796822B2 (en) 2011-10-07 2014-08-05 Freescale Semiconductor, Inc. Stacked semiconductor devices
CN102593087B (en) * 2012-03-01 2014-09-03 华进半导体封装先导技术研发中心有限公司 Mixed bonding structure for three-dimension integration and bonding method for mixed bonding structure
US9287245B2 (en) * 2012-11-07 2016-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Contoured package-on-package joint
US9209164B2 (en) 2012-11-13 2015-12-08 Delta Electronics, Inc. Interconnection structure of package structure and method of forming the same
US9159699B2 (en) 2012-11-13 2015-10-13 Delta Electronics, Inc. Interconnection structure having a via structure
WO2014113508A3 (en) 2013-01-15 2014-09-12 Microfabrica Inc. Methods of forming parts using laser machining
US9000459B2 (en) 2013-03-12 2015-04-07 Universal Display Corporation OLED display architecture having some blue subpixel components replaced with non-emissive volume containing via or functional electronic component and method of manufacturing thereof
US9018660B2 (en) 2013-03-25 2015-04-28 Universal Display Corporation Lighting devices
US9000490B2 (en) 2013-04-19 2015-04-07 Xilinx, Inc. Semiconductor package having IC dice and voltage tuners
US8979291B2 (en) 2013-05-07 2015-03-17 Universal Display Corporation Lighting devices including transparent organic light emitting device light panels and having independent control of direct to indirect light
US9082757B2 (en) 2013-10-31 2015-07-14 Freescale Semiconductor, Inc. Stacked semiconductor devices
US9659851B2 (en) * 2014-02-07 2017-05-23 Marvell World Trade Ltd. Method and apparatus for improving the reliability of a connection to a via in a substrate
US10002653B2 (en) 2014-10-28 2018-06-19 Nxp Usa, Inc. Die stack address bus having a programmable width
US20170271248A1 (en) * 2016-03-21 2017-09-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor package and manufacturing process thereof

Citations (70)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4617730A (en) * 1984-08-13 1986-10-21 International Business Machines Corporation Method of fabricating a chip interposer
US4622058A (en) * 1984-06-22 1986-11-11 International Business Machines Corporation Formation of a multi-layer glass-metallized structure formed on and interconnected to multi-layered-metallized ceramic substrate
US4830264A (en) * 1986-10-08 1989-05-16 International Business Machines Corporation Method of forming solder terminals for a pinless ceramic module
US4954313A (en) * 1989-02-03 1990-09-04 Amdahl Corporation Method and apparatus for filling high density vias
US5046239A (en) * 1990-07-10 1991-09-10 The United States Of America As Represented By The Secretary Of The Army Method of making a flexible membrane circuit tester
US5063177A (en) * 1990-10-04 1991-11-05 Comsat Method of packaging microwave semiconductor components and integrated circuits
US5166097A (en) * 1990-11-26 1992-11-24 The Boeing Company Silicon wafers containing conductive feedthroughs
US5172050A (en) * 1991-02-15 1992-12-15 Motorola, Inc. Micromachined semiconductor probe card
US5229647A (en) * 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
US5236551A (en) * 1990-05-10 1993-08-17 Microelectronics And Computer Technology Corporation Rework of polymeric dielectric electrical interconnect by laser photoablation
US5249450A (en) * 1992-06-15 1993-10-05 Micron Technology, Inc. Probehead for ultrasonic forging
US5277787A (en) * 1992-01-30 1994-01-11 Nippon Cmk Corp. Method of manufacturing printed wiring board
US5404044A (en) * 1992-09-29 1995-04-04 International Business Machines Corporation Parallel process interposer (PPI)
US5420520A (en) * 1993-06-11 1995-05-30 International Business Machines Corporation Method and apparatus for testing of integrated circuit chips
US5426072A (en) * 1993-01-21 1995-06-20 Hughes Aircraft Company Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate
US5432999A (en) * 1992-08-20 1995-07-18 Capps; David F. Integrated circuit lamination process
US5435480A (en) * 1993-12-23 1995-07-25 International Business Machines Corporation Method for filling plated through holes
US5473120A (en) * 1992-04-27 1995-12-05 Tokuyama Corporation Multilayer board and fabrication method thereof
US5474458A (en) * 1993-07-13 1995-12-12 Fujitsu Limited Interconnect carriers having high-density vertical connectors and methods for making the same
US5481795A (en) * 1992-05-06 1996-01-09 Matsushita Electric Industrial Co., Ltd. Method of manufacturing organic substrate used for printed circuits
US5483741A (en) * 1993-09-03 1996-01-16 Micron Technology, Inc. Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice
US5484647A (en) * 1993-09-21 1996-01-16 Matsushita Electric Industrial Co., Ltd. Connecting member of a circuit substrate and method of manufacturing multilayer circuit substrates by using the same
US5487218A (en) * 1994-11-21 1996-01-30 International Business Machines Corporation Method for making printed circuit boards with selectivity filled plated through holes
US5487999A (en) * 1991-06-04 1996-01-30 Micron Technology, Inc. Method for fabricating a penetration limited contact having a rough textured surface
US5493096A (en) * 1994-05-10 1996-02-20 Grumman Aerospace Corporation Thin substrate micro-via interconnect
US5528080A (en) * 1993-03-05 1996-06-18 Goldstein; Edward F. Electrically conductive interconnection through a body of semiconductor material
US5541525A (en) * 1991-06-04 1996-07-30 Micron Technology, Inc. Carrier for testing an unpackaged semiconductor die
US5578526A (en) * 1992-03-06 1996-11-26 Micron Technology, Inc. Method for forming a multi chip module (MCM)
US5592736A (en) * 1993-09-03 1997-01-14 Micron Technology, Inc. Fabricating an interconnect for testing unpackaged semiconductor dice having raised bond pads
US5599744A (en) * 1995-02-06 1997-02-04 Grumman Aerospace Corporation Method of forming a microcircuit via interconnect
US5607818A (en) * 1991-06-04 1997-03-04 Micron Technology, Inc. Method for making interconnects and semiconductor structures using electrophoretic photoresist deposition
US5633122A (en) * 1993-08-16 1997-05-27 Micron Technology, Inc. Test fixture and method for producing a test fixture for testing unpackaged semiconductor die
US5634267A (en) * 1991-06-04 1997-06-03 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
US5640051A (en) * 1993-12-13 1997-06-17 Matsushita Electric Industrial Co., Ltd. Chip package, a chip carrier, a terminal electrode for a circuit substrate and a chip package-mounted complex
US5674785A (en) * 1995-11-27 1997-10-07 Micron Technology, Inc. Method of producing a single piece package for semiconductor die
US5686317A (en) * 1991-06-04 1997-11-11 Micron Technology, Inc. Method for forming an interconnect having a penetration limited contact structure for establishing a temporary electrical connection with a semiconductor die
US5716218A (en) * 1991-06-04 1998-02-10 Micron Technology, Inc. Process for manufacturing an interconnect for testing a semiconductor die
US5780143A (en) * 1995-03-01 1998-07-14 Tokuyama Corporation Circuit board
US5781022A (en) * 1991-06-04 1998-07-14 Micron Technology, Inc. Substrate having self limiting contacts for establishing an electrical connection with a semiconductor die
US5783461A (en) * 1996-10-03 1998-07-21 Micron Technology, Inc. Temporary semiconductor package having hard-metal, dense-array ball contacts and method of fabrication
US5783865A (en) * 1995-07-31 1998-07-21 Fujitsu Limited Wiring substrate and semiconductor device
US5796590A (en) * 1996-11-05 1998-08-18 Micron Electronics, Inc. Assembly aid for mounting packaged integrated circuit devices to printed circuit boards
US5801452A (en) * 1996-10-25 1998-09-01 Micron Technology, Inc. Multi chip module including semiconductor wafer or dice, interconnect substrate, and alignment member
US5815000A (en) * 1991-06-04 1998-09-29 Micron Technology, Inc. Method for testing semiconductor dice with conventionally sized temporary packages
US5834848A (en) * 1996-12-03 1998-11-10 Kabushiki Kaisha Toshiba Electronic device and semiconductor package
US5834945A (en) * 1996-12-31 1998-11-10 Micron Technology, Inc. High speed temporary package and interconnect for testing semiconductor dice and method of fabrication
US5874043A (en) * 1996-06-12 1999-02-23 International Business Machines Corporation Lead-free, high tin ternary solder alloy of tin, silver, and indium
US5876580A (en) * 1996-01-12 1999-03-02 Micromodule Systems Rough electrical contact surface
US5878485A (en) * 1991-06-04 1999-03-09 Micron Technologoy, Inc. Method for fabricating a carrier for testing unpackaged semiconductor dice
US5915977A (en) * 1997-06-02 1999-06-29 Micron Technology, Inc. System and interconnect for making temporary electrical connections with bumped semiconductor components
US5929647A (en) * 1996-07-02 1999-07-27 Micron Technology, Inc. Method and apparatus for testing semiconductor dice
US5936847A (en) * 1996-05-02 1999-08-10 Hei, Inc. Low profile electronic circuit modules
US5952840A (en) * 1996-12-31 1999-09-14 Micron Technology, Inc. Apparatus for testing semiconductor wafers
US5960251A (en) * 1996-04-18 1999-09-28 International Business Machines Corporation Organic-metallic composite coating for copper surface protection
US5962921A (en) * 1997-03-31 1999-10-05 Micron Technology, Inc. Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with contact bumps
US6013948A (en) * 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US6040702A (en) * 1997-07-03 2000-03-21 Micron Technology, Inc. Carrier and system for testing bumped semiconductor components
US6107109A (en) * 1997-12-18 2000-08-22 Micron Technology, Inc. Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate
US6107119A (en) * 1998-07-06 2000-08-22 Micron Technology, Inc. Method for fabricating semiconductor components
US6114240A (en) * 1997-12-18 2000-09-05 Micron Technology, Inc. Method for fabricating semiconductor components using focused laser beam
US6119338A (en) * 1998-03-19 2000-09-19 Industrial Technology Research Institute Method for manufacturing high-density multilayer printed circuit boards
US6162997A (en) * 1997-06-03 2000-12-19 International Business Machines Corporation Circuit board with primary and secondary through holes
US6236115B1 (en) * 1995-12-27 2001-05-22 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US6353328B2 (en) * 1997-12-11 2002-03-05 Micron Technology, Inc. Test system with mechanical alignment for semiconductor chip scale packages and dice
US6356098B1 (en) * 1998-02-23 2002-03-12 Micron Technology, Inc. Probe card, test method and test system for semiconductor wafers
US6417685B1 (en) * 1999-06-14 2002-07-09 Micron Technology, Inc. Test system having alignment member for aligning semiconductor components
US6437591B1 (en) * 1999-03-25 2002-08-20 Micron Technology, Inc. Test interconnect for bumped semiconductor components and method of fabrication
US6451624B1 (en) * 1998-06-05 2002-09-17 Micron Technology, Inc. Stackable semiconductor package having conductive layer and insulating layers and method of fabrication
US6620731B1 (en) * 1997-12-18 2003-09-16 Micron Technology, Inc. Method for fabricating semiconductor components and interconnects with contacts on opposing sides
US6833613B1 (en) * 1997-12-18 2004-12-21 Micron Technology, Inc. Stacked semiconductor package having laser machined contacts

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5477160A (en) * 1992-08-12 1995-12-19 Fujitsu Limited Module test card
GB9301147D0 (en) * 1993-01-21 1993-03-10 Central Research Lab Ltd Infrared detector
US5477086A (en) * 1993-04-30 1995-12-19 Lsi Logic Corporation Shaped, self-aligning micro-bump structures
US5869974A (en) 1996-04-01 1999-02-09 Micron Technology, Inc. Micromachined probe card having compliant contact members for testing semiconductor wafers
US5872458A (en) * 1996-07-08 1999-02-16 Motorola, Inc. Method for electrically contacting semiconductor devices in trays and test contactor useful therefor
US5929467A (en) * 1996-12-04 1999-07-27 Sony Corporation Field effect transistor with nitride compound
US5940278A (en) * 1997-04-30 1999-08-17 Hewlett-Packard Company Backing plate for gate arrays or the like carries auxiliary components and provides probe access to electrical test points
US5880590A (en) * 1997-05-07 1999-03-09 International Business Machines Corporation Apparatus and method for burn-in and testing of devices with solder bumps or preforms
US5985682A (en) * 1997-08-25 1999-11-16 Motorola, Inc. Method for testing a bumped semiconductor die
US7983371B2 (en) * 2004-11-30 2011-07-19 Freescale Semiconductor, Inc. System and method for using programmable frequency offsets in a data network

Patent Citations (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4622058A (en) * 1984-06-22 1986-11-11 International Business Machines Corporation Formation of a multi-layer glass-metallized structure formed on and interconnected to multi-layered-metallized ceramic substrate
US4617730A (en) * 1984-08-13 1986-10-21 International Business Machines Corporation Method of fabricating a chip interposer
US4830264A (en) * 1986-10-08 1989-05-16 International Business Machines Corporation Method of forming solder terminals for a pinless ceramic module
US4954313A (en) * 1989-02-03 1990-09-04 Amdahl Corporation Method and apparatus for filling high density vias
US5236551A (en) * 1990-05-10 1993-08-17 Microelectronics And Computer Technology Corporation Rework of polymeric dielectric electrical interconnect by laser photoablation
US5046239A (en) * 1990-07-10 1991-09-10 The United States Of America As Represented By The Secretary Of The Army Method of making a flexible membrane circuit tester
US5063177A (en) * 1990-10-04 1991-11-05 Comsat Method of packaging microwave semiconductor components and integrated circuits
US5166097A (en) * 1990-11-26 1992-11-24 The Boeing Company Silicon wafers containing conductive feedthroughs
US5172050A (en) * 1991-02-15 1992-12-15 Motorola, Inc. Micromachined semiconductor probe card
US5229647A (en) * 1991-03-27 1993-07-20 Micron Technology, Inc. High density data storage using stacked wafers
US5541525A (en) * 1991-06-04 1996-07-30 Micron Technology, Inc. Carrier for testing an unpackaged semiconductor die
US5896036A (en) * 1991-06-04 1999-04-20 Micron Technology, Inc. Carrier for testing semiconductor dice
US5781022A (en) * 1991-06-04 1998-07-14 Micron Technology, Inc. Substrate having self limiting contacts for establishing an electrical connection with a semiconductor die
US5716218A (en) * 1991-06-04 1998-02-10 Micron Technology, Inc. Process for manufacturing an interconnect for testing a semiconductor die
US5686317A (en) * 1991-06-04 1997-11-11 Micron Technology, Inc. Method for forming an interconnect having a penetration limited contact structure for establishing a temporary electrical connection with a semiconductor die
US5878485A (en) * 1991-06-04 1999-03-09 Micron Technologoy, Inc. Method for fabricating a carrier for testing unpackaged semiconductor dice
US5634267A (en) * 1991-06-04 1997-06-03 Micron Technology, Inc. Method and apparatus for manufacturing known good semiconductor die
US5815000A (en) * 1991-06-04 1998-09-29 Micron Technology, Inc. Method for testing semiconductor dice with conventionally sized temporary packages
US5607818A (en) * 1991-06-04 1997-03-04 Micron Technology, Inc. Method for making interconnects and semiconductor structures using electrophoretic photoresist deposition
US5487999A (en) * 1991-06-04 1996-01-30 Micron Technology, Inc. Method for fabricating a penetration limited contact having a rough textured surface
US5277787A (en) * 1992-01-30 1994-01-11 Nippon Cmk Corp. Method of manufacturing printed wiring board
US5578526A (en) * 1992-03-06 1996-11-26 Micron Technology, Inc. Method for forming a multi chip module (MCM)
US5473120A (en) * 1992-04-27 1995-12-05 Tokuyama Corporation Multilayer board and fabrication method thereof
US5481795A (en) * 1992-05-06 1996-01-09 Matsushita Electric Industrial Co., Ltd. Method of manufacturing organic substrate used for printed circuits
US5249450A (en) * 1992-06-15 1993-10-05 Micron Technology, Inc. Probehead for ultrasonic forging
US5432999A (en) * 1992-08-20 1995-07-18 Capps; David F. Integrated circuit lamination process
US5404044A (en) * 1992-09-29 1995-04-04 International Business Machines Corporation Parallel process interposer (PPI)
US5426072A (en) * 1993-01-21 1995-06-20 Hughes Aircraft Company Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate
US5528080A (en) * 1993-03-05 1996-06-18 Goldstein; Edward F. Electrically conductive interconnection through a body of semiconductor material
US5420520A (en) * 1993-06-11 1995-05-30 International Business Machines Corporation Method and apparatus for testing of integrated circuit chips
US5474458A (en) * 1993-07-13 1995-12-12 Fujitsu Limited Interconnect carriers having high-density vertical connectors and methods for making the same
US5633122A (en) * 1993-08-16 1997-05-27 Micron Technology, Inc. Test fixture and method for producing a test fixture for testing unpackaged semiconductor die
US5483741A (en) * 1993-09-03 1996-01-16 Micron Technology, Inc. Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice
US5592736A (en) * 1993-09-03 1997-01-14 Micron Technology, Inc. Fabricating an interconnect for testing unpackaged semiconductor dice having raised bond pads
US5484647A (en) * 1993-09-21 1996-01-16 Matsushita Electric Industrial Co., Ltd. Connecting member of a circuit substrate and method of manufacturing multilayer circuit substrates by using the same
US5640051A (en) * 1993-12-13 1997-06-17 Matsushita Electric Industrial Co., Ltd. Chip package, a chip carrier, a terminal electrode for a circuit substrate and a chip package-mounted complex
US5435480A (en) * 1993-12-23 1995-07-25 International Business Machines Corporation Method for filling plated through holes
US5493096A (en) * 1994-05-10 1996-02-20 Grumman Aerospace Corporation Thin substrate micro-via interconnect
US5487218A (en) * 1994-11-21 1996-01-30 International Business Machines Corporation Method for making printed circuit boards with selectivity filled plated through holes
US5557844A (en) * 1994-11-21 1996-09-24 International Business Machines Corporation Method of preparing a printed circuit board
US5599744A (en) * 1995-02-06 1997-02-04 Grumman Aerospace Corporation Method of forming a microcircuit via interconnect
US5780143A (en) * 1995-03-01 1998-07-14 Tokuyama Corporation Circuit board
US5783865A (en) * 1995-07-31 1998-07-21 Fujitsu Limited Wiring substrate and semiconductor device
US5674785A (en) * 1995-11-27 1997-10-07 Micron Technology, Inc. Method of producing a single piece package for semiconductor die
US6013948A (en) * 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US6236115B1 (en) * 1995-12-27 2001-05-22 International Business Machines Corporation High density integrated circuit packaging with chip stacking and via interconnections
US5876580A (en) * 1996-01-12 1999-03-02 Micromodule Systems Rough electrical contact surface
US5960251A (en) * 1996-04-18 1999-09-28 International Business Machines Corporation Organic-metallic composite coating for copper surface protection
US5936847A (en) * 1996-05-02 1999-08-10 Hei, Inc. Low profile electronic circuit modules
US5874043A (en) * 1996-06-12 1999-02-23 International Business Machines Corporation Lead-free, high tin ternary solder alloy of tin, silver, and indium
US5929647A (en) * 1996-07-02 1999-07-27 Micron Technology, Inc. Method and apparatus for testing semiconductor dice
US5783461A (en) * 1996-10-03 1998-07-21 Micron Technology, Inc. Temporary semiconductor package having hard-metal, dense-array ball contacts and method of fabrication
US5801452A (en) * 1996-10-25 1998-09-01 Micron Technology, Inc. Multi chip module including semiconductor wafer or dice, interconnect substrate, and alignment member
US5796590A (en) * 1996-11-05 1998-08-18 Micron Electronics, Inc. Assembly aid for mounting packaged integrated circuit devices to printed circuit boards
US5834848A (en) * 1996-12-03 1998-11-10 Kabushiki Kaisha Toshiba Electronic device and semiconductor package
US5834945A (en) * 1996-12-31 1998-11-10 Micron Technology, Inc. High speed temporary package and interconnect for testing semiconductor dice and method of fabrication
US5952840A (en) * 1996-12-31 1999-09-14 Micron Technology, Inc. Apparatus for testing semiconductor wafers
US6362637B2 (en) * 1996-12-31 2002-03-26 Micron Technology, Inc. Apparatus for testing semiconductor wafers including base with contact members and terminal contacts
US5962921A (en) * 1997-03-31 1999-10-05 Micron Technology, Inc. Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with contact bumps
US5915977A (en) * 1997-06-02 1999-06-29 Micron Technology, Inc. System and interconnect for making temporary electrical connections with bumped semiconductor components
US5931685A (en) * 1997-06-02 1999-08-03 Micron Technology, Inc. Interconnect for making temporary electrical connections with bumped semiconductor components
US6162997A (en) * 1997-06-03 2000-12-19 International Business Machines Corporation Circuit board with primary and secondary through holes
US6040702A (en) * 1997-07-03 2000-03-21 Micron Technology, Inc. Carrier and system for testing bumped semiconductor components
US6353328B2 (en) * 1997-12-11 2002-03-05 Micron Technology, Inc. Test system with mechanical alignment for semiconductor chip scale packages and dice
US6833613B1 (en) * 1997-12-18 2004-12-21 Micron Technology, Inc. Stacked semiconductor package having laser machined contacts
US6114240A (en) * 1997-12-18 2000-09-05 Micron Technology, Inc. Method for fabricating semiconductor components using focused laser beam
US6952054B2 (en) * 1997-12-18 2005-10-04 Micron Technology, Inc. Semiconductor package having interconnect with conductive members
US6294837B1 (en) * 1997-12-18 2001-09-25 Micron Technology, Inc. Semiconductor interconnect having laser machined contacts
US6620731B1 (en) * 1997-12-18 2003-09-16 Micron Technology, Inc. Method for fabricating semiconductor components and interconnects with contacts on opposing sides
US6998344B2 (en) * 1997-12-18 2006-02-14 Micron Technology, Inc. Method for fabricating semiconductor components by forming conductive members using solder
US6400172B1 (en) * 1997-12-18 2002-06-04 Micron Technology, Inc. Semiconductor components having lasered machined conductive vias
US6107109A (en) * 1997-12-18 2000-08-22 Micron Technology, Inc. Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate
US6903443B2 (en) * 1997-12-18 2005-06-07 Micron Technology, Inc. Semiconductor component and interconnect having conductive members and contacts on opposing sides
US20050101037A1 (en) * 1997-12-18 2005-05-12 Farnworth Warren M. Test system with interconnect having conductive members and contacts on opposing sides
US6356098B1 (en) * 1998-02-23 2002-03-12 Micron Technology, Inc. Probe card, test method and test system for semiconductor wafers
US6119338A (en) * 1998-03-19 2000-09-19 Industrial Technology Research Institute Method for manufacturing high-density multilayer printed circuit boards
US6451624B1 (en) * 1998-06-05 2002-09-17 Micron Technology, Inc. Stackable semiconductor package having conductive layer and insulating layers and method of fabrication
US6107119A (en) * 1998-07-06 2000-08-22 Micron Technology, Inc. Method for fabricating semiconductor components
US6437591B1 (en) * 1999-03-25 2002-08-20 Micron Technology, Inc. Test interconnect for bumped semiconductor components and method of fabrication
US6417685B1 (en) * 1999-06-14 2002-07-09 Micron Technology, Inc. Test system having alignment member for aligning semiconductor components

Cited By (75)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7300864B2 (en) * 2003-10-22 2007-11-27 Samsung Electronics Co., Ltd. Method for forming solder bump structure
US20050090089A1 (en) * 2003-10-22 2005-04-28 Keum-Hee Ma Method for forming solder bump structure
US20070070311A1 (en) * 2005-09-23 2007-03-29 Asml Netherlands B.V. Contacts to microdevices
US7560371B2 (en) 2006-08-29 2009-07-14 Micron Technology, Inc. Methods for selectively filling apertures in a substrate to form conductive vias with a liquid using a vacuum
US20080057691A1 (en) * 2006-08-29 2008-03-06 Dando Ross S Methods and systems for selectively filling apertures in a substrate to form conductive vias with a liquid using a vacuum
US9899353B2 (en) 2006-10-10 2018-02-20 Tessera, Inc. Off-chip vias in stacked chips
US9048234B2 (en) 2006-10-10 2015-06-02 Tessera, Inc. Off-chip vias in stacked chips
US8461673B2 (en) 2006-10-10 2013-06-11 Tessera, Inc. Edge connect wafer level stacking
US8476774B2 (en) 2006-10-10 2013-07-02 Tessera, Inc. Off-chip VIAS in stacked chips
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US8431435B2 (en) 2006-10-10 2013-04-30 Tessera, Inc. Edge connect wafer level stacking
US9378967B2 (en) 2006-10-10 2016-06-28 Tessera, Inc. Method of making a stacked microelectronic package
US8426957B2 (en) 2006-10-10 2013-04-23 Tessera, Inc. Edge connect wafer level stacking
US8076788B2 (en) 2006-10-10 2011-12-13 Tessera, Inc. Off-chip vias in stacked chips
US7829438B2 (en) 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
US8999810B2 (en) 2006-10-10 2015-04-07 Tessera, Inc. Method of making a stacked microelectronic package
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US8022527B2 (en) 2006-10-10 2011-09-20 Tessera, Inc. Edge connect wafer level stacking
US7791199B2 (en) 2006-11-22 2010-09-07 Tessera, Inc. Packaged semiconductor chips
US8653644B2 (en) 2006-11-22 2014-02-18 Tessera, Inc. Packaged semiconductor chips with array
US8704347B2 (en) 2006-11-22 2014-04-22 Tessera, Inc. Packaged semiconductor chips
US20080116544A1 (en) * 2006-11-22 2008-05-22 Tessera, Inc. Packaged semiconductor chips with array
US9070678B2 (en) 2006-11-22 2015-06-30 Tessera, Inc. Packaged semiconductor chips with array
US20080116545A1 (en) * 2006-11-22 2008-05-22 Tessera, Inc. Packaged semiconductor chips
US9548254B2 (en) 2006-11-22 2017-01-17 Tessera, Inc. Packaged semiconductor chips with array
US8569876B2 (en) 2006-11-22 2013-10-29 Tessera, Inc. Packaged semiconductor chips with array
US8349654B2 (en) 2006-12-28 2013-01-08 Tessera, Inc. Method of fabricating stacked packages with bridging traces
US7952195B2 (en) 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
US20080171413A1 (en) * 2007-01-17 2008-07-17 International Business Machines Corporation Method of Reducing Detrimental STI-Induced Stress in MOSFET Channels
US8405196B2 (en) 2007-03-05 2013-03-26 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
US8310036B2 (en) 2007-03-05 2012-11-13 DigitalOptics Corporation Europe Limited Chips having rear contacts connected by through vias to front contacts
US8735205B2 (en) 2007-03-05 2014-05-27 Invensas Corporation Chips having rear contacts connected by through vias to front contacts
US20100225006A1 (en) * 2007-03-05 2010-09-09 Tessera, Inc. Chips having rear contacts connected by through vias to front contacts
US20090014858A1 (en) * 2007-07-09 2009-01-15 Micron Technology, Inc. Packaged semiconductor assemblies and methods for manufacturing such assemblies
US8232657B2 (en) 2007-07-09 2012-07-31 Micron Technology, Inc. Packaged semiconductor assemblies and methods for manufacturing such assemblies
US7855462B2 (en) 2007-07-09 2010-12-21 Micron Technology, Inc. Packaged semiconductor assemblies and methods for manufacturing such assemblies
US20110084402A1 (en) * 2007-07-09 2011-04-14 Micron Technology, Inc. Packaged semiconductor assemblies and methods for manufacturing such assemblies
US8629054B2 (en) 2007-07-09 2014-01-14 Micron Technology, Inc. Packaged semiconductor assemblies and methods for manufacturing such assemblies
US9911696B2 (en) 2007-07-09 2018-03-06 Micron Technology, Inc. Packaged semiconductor assemblies and methods for manufacturing such assemblies
US8461672B2 (en) 2007-07-27 2013-06-11 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
US8883562B2 (en) 2007-07-27 2014-11-11 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
US8735287B2 (en) 2007-07-31 2014-05-27 Invensas Corp. Semiconductor packaging process using through silicon vias
US20090065907A1 (en) * 2007-07-31 2009-03-12 Tessera, Inc. Semiconductor packaging process using through silicon vias
US8193615B2 (en) 2007-07-31 2012-06-05 DigitalOptics Corporation Europe Limited Semiconductor packaging process using through silicon vias
US8551815B2 (en) 2007-08-03 2013-10-08 Tessera, Inc. Stack packages using reconstituted wafers
US8043895B2 (en) 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
US8513794B2 (en) 2007-08-09 2013-08-20 Tessera, Inc. Stacked assembly including plurality of stacked microelectronic elements
US20090212381A1 (en) * 2008-02-26 2009-08-27 Tessera, Inc. Wafer level packages for rear-face illuminated solid state image sensors
US20100053407A1 (en) * 2008-02-26 2010-03-04 Tessera, Inc. Wafer level compliant packages for rear-face illuminated solid state image sensors
US8680662B2 (en) 2008-06-16 2014-03-25 Tessera, Inc. Wafer level edge stacking
US8466542B2 (en) 2009-03-13 2013-06-18 Tessera, Inc. Stacked microelectronic assemblies having vias extending through bond pads
US8791575B2 (en) 2010-07-23 2014-07-29 Tessera, Inc. Microelectronic elements having metallic pads overlying vias
US8796135B2 (en) 2010-07-23 2014-08-05 Tessera, Inc. Microelectronic elements with rear contacts connected with via first or via middle structures
US9640437B2 (en) 2010-07-23 2017-05-02 Tessera, Inc. Methods of forming semiconductor elements using micro-abrasive particle stream
US8809190B2 (en) 2010-09-17 2014-08-19 Tessera, Inc. Multi-function and shielded 3D interconnects
US8847380B2 (en) 2010-09-17 2014-09-30 Tessera, Inc. Staged via formation from both sides of chip
US9362203B2 (en) 2010-09-17 2016-06-07 Tessera, Inc. Staged via formation from both sides of chip
US9847277B2 (en) 2010-09-17 2017-12-19 Tessera, Inc. Staged via formation from both sides of chip
US9355948B2 (en) 2010-09-17 2016-05-31 Tessera, Inc. Multi-function and shielded 3D interconnects
US8610259B2 (en) 2010-09-17 2013-12-17 Tessera, Inc. Multi-function and shielded 3D interconnects
US8772908B2 (en) 2010-11-15 2014-07-08 Tessera, Inc. Conductive pads defined by embedded traces
US8432045B2 (en) 2010-11-15 2013-04-30 Tessera, Inc. Conductive pads defined by embedded traces
US8587126B2 (en) 2010-12-02 2013-11-19 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US9099296B2 (en) 2010-12-02 2015-08-04 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages with plural active chips
US9368476B2 (en) 2010-12-02 2016-06-14 Tessera, Inc. Stacked microelectronic assembly with TSVs formed in stages with plural active chips
US8637968B2 (en) 2010-12-02 2014-01-28 Tessera, Inc. Stacked microelectronic assembly having interposer connecting active chips
US9620437B2 (en) 2010-12-02 2017-04-11 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US9269692B2 (en) 2010-12-02 2016-02-23 Tessera, Inc. Stacked microelectronic assembly with TSVS formed in stages and carrier above chip
US8736066B2 (en) 2010-12-02 2014-05-27 Tessera, Inc. Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
US9224649B2 (en) 2010-12-08 2015-12-29 Tessera, Inc. Compliant interconnects in wafers
US8796828B2 (en) 2010-12-08 2014-08-05 Tessera, Inc. Compliant interconnects in wafers
US8610264B2 (en) 2010-12-08 2013-12-17 Tessera, Inc. Compliant interconnects in wafers
JP2016058535A (en) * 2014-09-09 2016-04-21 大日本印刷株式会社 Structure and method of manufacturing the same
US9881851B2 (en) * 2015-05-29 2018-01-30 Toshiba Memory Corporation Semiconductor device and method for producing semiconductor device
US20160351473A1 (en) * 2015-05-29 2016-12-01 Kabushiki Kaisha Toshiba Semiconductor device and method for producing semiconductor device

Also Published As

Publication number Publication date Type
US6903443B2 (en) 2005-06-07 grant
US6620731B1 (en) 2003-09-16 grant
US20030080408A1 (en) 2003-05-01 application
US20050101037A1 (en) 2005-05-12 application

Similar Documents

Publication Publication Date Title
US5801452A (en) Multi chip module including semiconductor wafer or dice, interconnect substrate, and alignment member
US5578934A (en) Method and apparatus for testing unpackaged semiconductor dice
US6246247B1 (en) Probe card assembly and kit, and methods of using same
US6242803B1 (en) Semiconductor devices with integral contact structures
US8373428B2 (en) Probe card assembly and kit, and methods of making same
US6624648B2 (en) Probe card assembly
US6046410A (en) Interface structures for electronic devices
US5810609A (en) Socket for engaging bump leads on a microelectronic device and methods therefor
US5982185A (en) Direct connect carrier for testing semiconductor dice and method of fabrication
US6881609B2 (en) Component connections using bumps and wells
US6943056B2 (en) Semiconductor device manufacturing method and electronic equipment using same
US6528984B2 (en) Integrated compliant probe for wafer level test and burn-in
US6741085B1 (en) Contact carriers (tiles) for populating larger substrates with spring contacts
US6420884B1 (en) Contact structure formed by photolithography process
US6882546B2 (en) Multiple die interconnect system
US6917102B2 (en) Contact structure and production method thereof and probe contact assembly using same
US6920689B2 (en) Method for making a socket to perform testing on integrated circuits
US5637925A (en) Uses of uniaxially electrically conductive articles
US7109068B2 (en) Through-substrate interconnect fabrication methods
US20030160325A1 (en) Semiconductor device substrate and manufacturing method thereof and semiconductor package
US6040239A (en) Non-oxidizing touch contact interconnect for semiconductor test systems and method of fabrication
US8213184B2 (en) Method of testing using a temporary chip attach carrier
US5946546A (en) Chip burn-in and test structure and method
US6215321B1 (en) Probe card for wafer-level measurement, multilayer ceramic wiring board, and fabricating methods therefor
US5786701A (en) Bare die testing