US20050213384A1 - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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Publication number
US20050213384A1
US20050213384A1 US11/135,775 US13577505A US2005213384A1 US 20050213384 A1 US20050213384 A1 US 20050213384A1 US 13577505 A US13577505 A US 13577505A US 2005213384 A1 US2005213384 A1 US 2005213384A1
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Prior art keywords
gate line
forming
layer
protecting
spacer
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Abandoned
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US11/135,775
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Ji-Young Kim
Sang-Yong Kim
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from US10/633,408 external-priority patent/US7309127B2/en
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Priority to US11/135,775 priority Critical patent/US20050213384A1/en
Publication of US20050213384A1 publication Critical patent/US20050213384A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This disclosure generally relates to a semiconductor device and a method of forming the same and in particular, to a structure of a semiconductor device that protects an end of a gate line and a method of forming the same.
  • FIG. 1A is a plan diagram illustrating a semiconductor device including a gate line in accordance with the conventional technology.
  • FIG. 1B contains cross-sectional diagrams taken along the line I-I′ and the line II-II′, respectively, of the semiconductor device of FIG. 1A .
  • the letter ‘aa’ indicates a region 1 that is a cross-sectional diagram taken along the I-I′ line of FIG. 1A
  • the letter ‘bb’ indicates a region 2 that is a cross-sectional diagram taken along the II-II′ line of FIG. 1A .
  • a field oxide (FOX) 3 is formed at a semiconductor substrate 1 to define an active region (AR).
  • a gate oxide layer 5 , a polysilicon layer 7 , a tungsten layer 9 , and a capping layer 11 are sequentially stacked on an entire surface of the semiconductor substrate 1 .
  • the layers 11 , 9 , 7 and 5 are sequentially patterned to form a gate line (GL).
  • end parts of a photo mask (M) are orthogonal.
  • a plan view of the end (E) of the gate line that is subsequently formed becomes rounded as illustrated in FIG. 1A and a side view thereof becomes gently sloped as illustrated in FIG. 1B .
  • a low-concentration impurity-doped region 4 is formed by using the gate line (GL) as an ion-implantation mask.
  • an insulation layer is stacked on an entire surface of the semiconductor substrate 1 and anisotropically etched to form a spacer 13 covering sidewalls of the gate line (GL).
  • a high concentration impurity-doped region 14 is formed by using the gate line (GL) and the spacer 13 as ion-implantation masks.
  • the side slope of the end (E) of the gate line (GL) is gentle, almost all of the insulation layer is removed to form a very thin and imperfect spacer 13 at the region 2 (bb).
  • Embodiments of the invention address these and other disadvantages of the prior art.
  • Embodiments of the invention provide structures of a semiconductor substrate that protect an end of a gate line in order to improve reliability of a semiconductor device. Embodiments of the invention also provide methods of forming the same structures.
  • FIG. 1A is a plan diagram illustrating a semiconductor device including a gate line in accordance with a conventional technology.
  • FIG. 1B contains two cross-sectional diagrams taken along the line I-I′ and the line II-II′, respectively, of the semiconductor device illustrated in FIG. 1A .
  • FIG. 2 is a plan diagram illustrating a semiconductor device in accordance with an embodiment of the invention.
  • FIG. 3 contains three cross-sectional diagrams of the semiconductor device shown in FIG. 2 , taken along the line III-III′, the line IV-IV′, and the line V-V′, respectively.
  • FIGS. 4A through 4C are cross-sectional diagrams illustrating a method of forming the structure of FIG. 3 .
  • FIG. 5 contains three cross-sectional diagrams of the semiconductor device shown in FIG. 2 , taken along the line III-III′, the line IV-IV′, and the line V-V′, respectively, but in accordance with another embodiment of the invention.
  • FIGS. 6A through 6C are cross-sectional diagrams illustrating a method of forming the structure of FIG. 5 .
  • relative terms such as “beneath”, may be used herein to describe one element's relationship to another elements as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in the Figures is turned over, elements described as “below” other elements would then be oriented “above” the other elements. The exemplary term “below”, can therefore, encompasses both an orientation of above and below.
  • first and second are used herein to describe various regions, layers and/or sections, these regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish one region, layer, or section from another region, layer, or section. Thus, a first region, layer or section discussed below could alternatively be termed a second region, layer or section, and similarly, a second region, layer, or section could be termed a first region, layer, or section without departing from the teachings of the invention.
  • Like numbers refer to like elements throughout.
  • the letter ‘a’ indicates a first region that is a cross-sectional diagram taken along the III-III′ line of FIG. 2
  • the letter ‘b’ indicates a second region that is a cross-sectional diagram taken along the IV-IV′ line thereof
  • the letter ‘c’ indicates a third region that is a cross-sectional diagram taken along the V-V′ line thereof.
  • FIG. 2 is a plan diagram illustrating a semiconductor device in accordance with an embodiment of the invention
  • FIG. 3 contains three cross-sectional diagrams of the semiconductor device shown in FIG. 2 , taken along the line III-III′, the line IV-IV′, and the line V-V′, respectively.
  • a field oxide (FOX) 102 is present at a semiconductor substrate 100 to define an active region (AR).
  • a gate line (GL) crosses over the active region (AR).
  • the gate line (GL) is composed of a gate oxide layer 104 , a polysilicon layer 106 , a tungsten layer 108 , and a capping layer pattern 110 that are sequentially stacked.
  • the gate oxide layer 104 may have a thickness of about 50 ⁇ 300 ⁇
  • the poly silicon layer 106 may have a thickness of about 700 ⁇ 900 ⁇ .
  • the thickness of the tungsten layer 108 may be about 400 ⁇ 600 ⁇
  • that of the capping layer 110 may be 1900 ⁇ 2100 ⁇ .
  • a spacer 114 a covers sidewalls of the gate line (GL).
  • the active region (AR) there is a low concentration impurity-doped region 112 to contact with side lower ends of the gate line (GL) and a high concentration impurity-doped region 115 to contact with those of the spacer 114 a .
  • the end (E) is located on the field oxide 102 and covered by a protecting pattern (S) 114 b .
  • the spacer 114 a and the protecting pattern (S) 114 b are formed of the same material and preferably of silicon nitride or silicon oxide.
  • the protecting pattern (S) 114 b may have a thickness of 400 ⁇ 600 ⁇ .
  • FIGS. 4A through 4C are cross-sectional diagrams illustrating a method of forming the structure of FIG. 3 .
  • a field oxide (FOX) 102 is formed on a semiconductor substrate 100 to define an active region (AR).
  • a gate oxide layer 104 , a polysilicon layer 106 , a tungsten layer 108 , and a capping layer 110 are sequentially stacked at an entire surface of the semiconductor substrate 100 .
  • the capping layer 110 may be formed of silicon nitride.
  • the layers 110 , 108 , 106 , and 104 are sequentially patterned to form a gate line (GL).
  • a low concentration impurity-doped region 112 is formed in the active region (AR) by using the gate line (GL) as an ion-implantation mask.
  • an insulation layer 114 is conformally stacked over an entire surface of the semiconductor substrate 100 .
  • the insulation layer 114 may be formed of silicon nitride or silicon oxide.
  • a photoresist pattern (PR 1 ) is formed to cover only the end (E) of the gate line (GL).
  • the insulation layer 114 is anisotropically etched by using the photoresist pattern (PR 1 ).
  • a spacer 114 a is formed to cover sidewalls of the gate line (GL) and, simultaneously, a protecting pattern (S) 114 b is formed to cover the end (E) of the gate line (GL).
  • the photoresist pattern (PR 1 ) is removed.
  • a high concentration impurity-doped region 115 is formed in the active region (AR) of the semiconductor substrate 100 by using the gate line (GL), the spacer 114 a and the protecting pattern 114 b as ion-implantation masks.
  • the protecting pattern (S) 114 b protects the end (E) of the gate line (GL), it is possible to prevent the tungsten from being damaged by a cleaning solution such as SC 1 .
  • FIG. 5 contains three cross-sectional diagrams of the semiconductor device shown in FIG. 2 , taken along the line III-III′, the line IV-IV′, and the line V-V′, respectively, but in accordance with another embodiment of the invention.
  • a semiconductor device includes a spacer 114 a covering sidewalls and ends (E) of a gate line (GL) and a protecting pattern (S) 116 b covering the ends (E) of the gate line (GL).
  • the spacer 114 a is interposed between the gate line (GL) and the protecting pattern (S) 116 b at the end (E) of the gate line (GL).
  • the protecting pattern (S) 116 b may be thinner than the protecting pattern (S) 114 b of the embodiment of FIG. 3 and preferably may have a thickness of that is about one fifth the thickness of the protecting pattern (S) 114 b .
  • the protecting pattern (S) 116 b may have a thickness of 80 ⁇ 120 ⁇ .
  • FIGS. 6A through 6C are cross-sectional diagrams illustrating a method of forming the structure of FIG. 5 .
  • an insulation layer 114 is entirely anisotropically etched at the state of FIG. 4B of the first embodiment, thereby forming a spacer 114 a covering sidewalls and ends (E) of the gate line (GL).
  • a high concentration impurity-doped region 115 is formed in an active region (AR) of the semiconductor substrate 100 by using the gate line (GL) and the spacer 114 a as ion-implantation masks.
  • a protecting layer 116 is stacked on an entire surface of the semiconductor substrate 100 . At this time, the protecting layer 116 may be formed of the same material with the insulation layer 114 .
  • the protecting layer 116 may be formed in a thickness that is approximately one fifth the thickness of the insulation layer 114 , and preferably is a thickness of 80 ⁇ 120 ⁇ .
  • a photoresist pattern (PR 2 ) is formed on the protecting layer 116 to cover the ends (E) of the gate line (GL).
  • An anisotropic etch process is performed with respect to the protecting layer 116 by using the photoresist pattern (PR 2 ) as an etch mask, thereby forming a protecting pattern (S) 116 b covering the ends (E) of the gate line (GL) but exposing the gate line (GL) on the active region (AR).
  • the photoresist pattern (PR 2 ) is removed. Except for the thickness of the protecting layer 116 , the process conditions and other layers are identical to the embodiment illustrated in FIG. 3 .
  • Embodiments of the invention may include a semiconductor substrate, a gate line crossing over the semiconductor substrate, and a protecting pattern covering ends of the gate line.
  • the protecting pattern may be formed of silicon nitride or silicon oxide.
  • Embodiments may further include a spacer covering sidewalls of the gate line and being interposed between the gate line and the protecting pattern at the ends of the gate line.
  • the spacer may be formed of silicon nitride or silicon oxide.
  • the gate line includes an oxide pattern and a conductive pattern that are sequentially stacked on the semiconductor substrate.
  • the conductive pattern is formed of a metal selected from a group consisting of tungsten, aluminum and aluminum.
  • the semiconductor device may be formed by the following method. First, a gate line is formed at a semiconductor substrate. A spacer is formed to cover sidewalls of the gate line. Next, a protecting pattern is formed to cover ends of the gate line.
  • the spacer and the protecting pattern may be simultaneously formed of the same material.
  • the material may be silicon nitride or silicon oxide.
  • the gate line may be formed by sequentially stacking an oxide layer and a conductive layer on a semiconductor substrate and sequentially patterning the conductive layer and the oxide layer.
  • the conductive layer may be formed of a metal selected from a group consisting of tungsten, copper, and aluminum.
  • the semiconductor substrate since the semiconductor substrate includes a protecting pattern covering ends of a gate line, the ends of the gate line are protected by the protecting pattern, thereby preventing gate electrodes from being damaged by a cleaning solution such as SC 1 in a subsequent process.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A semiconductor device protecting the ends of a gate line and a method of forming the same are disclosed. The semiconductor device includes a semiconductor substrate, a gate line crossing over the semiconductor substrate, and a protecting pattern covering ends of the gate line. According to the method, a gate line is formed at a semiconductor substrate. A spacer is formed to cover sidewalls of the gate line. A protecting pattern is formed to cover the ends of the gate line. The protecting pattern may be formed of silicon nitride or silicon oxide. Since the protecting pattern protects ends of a gate line, it is possible to prevent gate electrodes from being damaged by a cleaning solution such as SC1 in a subsequent process.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a Divisional of U.S. patent Ser. No. 10/633,408, filed on Jul. 31, 2003, now pending, which claims priority from Korean Patent Application No. 2002-59835, filed on Oct. 1, 2002, the contents of which are herein incorporated by reference in their entirety.
    • BACKGROUND OF THE INVENTION
  • 1. Technical Field of the Invention
  • This disclosure generally relates to a semiconductor device and a method of forming the same and in particular, to a structure of a semiconductor device that protects an end of a gate line and a method of forming the same.
  • 2. Background of the Invention
  • During a photo-lithography process, one of the many processes used to form a semiconductor device, the end parts of photoresist patterns become rounded due to proximity effects. As semiconductor devices become highly integrated, the pattern size is reduced and proximity effects become increasingly problematic.
  • FIG. 1A is a plan diagram illustrating a semiconductor device including a gate line in accordance with the conventional technology.
  • FIG. 1B contains cross-sectional diagrams taken along the line I-I′ and the line II-II′, respectively, of the semiconductor device of FIG. 1A. In FIG. 1B, the letter ‘aa’ indicates a region 1 that is a cross-sectional diagram taken along the I-I′ line of FIG. 1A, and the letter ‘bb’ indicates a region 2 that is a cross-sectional diagram taken along the II-II′ line of FIG. 1A.
  • Referring to FIGS. 1A and 1B, a field oxide (FOX) 3 is formed at a semiconductor substrate 1 to define an active region (AR). A gate oxide layer 5, a polysilicon layer 7, a tungsten layer 9, and a capping layer 11 are sequentially stacked on an entire surface of the semiconductor substrate 1. The layers 11, 9, 7 and 5 are sequentially patterned to form a gate line (GL). In a photolithography process prior to the patterning process, end parts of a photo mask (M) are orthogonal. However a plan view of the end (E) of the gate line that is subsequently formed becomes rounded as illustrated in FIG. 1A and a side view thereof becomes gently sloped as illustrated in FIG. 1B. A low-concentration impurity-doped region 4 is formed by using the gate line (GL) as an ion-implantation mask. In order to form an lightly doped drain, an insulation layer is stacked on an entire surface of the semiconductor substrate 1 and anisotropically etched to form a spacer 13 covering sidewalls of the gate line (GL). Next, a high concentration impurity-doped region 14 is formed by using the gate line (GL) and the spacer 13 as ion-implantation masks. At this time, since the side slope of the end (E) of the gate line (GL) is gentle, almost all of the insulation layer is removed to form a very thin and imperfect spacer 13 at the region 2 (bb). When a subsequent cleaning process is performed using an SC1 solution that is frequently used in a cleaning process and made of a mixture of NH4OH, H2O2 and deionized water, the SC1 penetrates the end (E) of the gate line (GL) that is weak with the thin spacer 13, thereby dissolving the tungsten layer 9. This results in reliability problems for the semiconductor device.
  • Embodiments of the invention address these and other disadvantages of the prior art.
    • SUMMARY OF THE INVENTION
  • Embodiments of the invention provide structures of a semiconductor substrate that protect an end of a gate line in order to improve reliability of a semiconductor device. Embodiments of the invention also provide methods of forming the same structures.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1A is a plan diagram illustrating a semiconductor device including a gate line in accordance with a conventional technology.
  • FIG. 1B contains two cross-sectional diagrams taken along the line I-I′ and the line II-II′, respectively, of the semiconductor device illustrated in FIG. 1A.
  • FIG. 2 is a plan diagram illustrating a semiconductor device in accordance with an embodiment of the invention.
  • FIG. 3 contains three cross-sectional diagrams of the semiconductor device shown in FIG. 2, taken along the line III-III′, the line IV-IV′, and the line V-V′, respectively.
  • FIGS. 4A through 4C are cross-sectional diagrams illustrating a method of forming the structure of FIG. 3.
  • FIG. 5 contains three cross-sectional diagrams of the semiconductor device shown in FIG. 2, taken along the line III-III′, the line IV-IV′, and the line V-V′, respectively, but in accordance with another embodiment of the invention.
  • FIGS. 6A through 6C are cross-sectional diagrams illustrating a method of forming the structure of FIG. 5.
    • DETAILED DESCRIPTION OF THE INVENTION
  • The invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
  • In the drawings, the thickness of layers and regions are exaggerated for clarity. It will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present.
  • Furthermore, relative terms, such as “beneath”, may be used herein to describe one element's relationship to another elements as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in the Figures is turned over, elements described as “below” other elements would then be oriented “above” the other elements. The exemplary term “below”, can therefore, encompasses both an orientation of above and below.
  • It will be understood that although the terms first and second are used herein to describe various regions, layers and/or sections, these regions, layers, and/or sections should not be limited by these terms. These terms are only used to distinguish one region, layer, or section from another region, layer, or section. Thus, a first region, layer or section discussed below could alternatively be termed a second region, layer or section, and similarly, a second region, layer, or section could be termed a first region, layer, or section without departing from the teachings of the invention. Like numbers refer to like elements throughout. In FIGS. 3, 4A-4C, 5 and 6A-6C, the letter ‘a’ indicates a first region that is a cross-sectional diagram taken along the III-III′ line of FIG. 2, the letter ‘b’ indicates a second region that is a cross-sectional diagram taken along the IV-IV′ line thereof, and the letter ‘c’ indicates a third region that is a cross-sectional diagram taken along the V-V′ line thereof.
  • FIG. 2 is a plan diagram illustrating a semiconductor device in accordance with an embodiment of the invention, while FIG. 3 contains three cross-sectional diagrams of the semiconductor device shown in FIG. 2, taken along the line III-III′, the line IV-IV′, and the line V-V′, respectively.
  • Referring to FIGS. 2 and 3, a field oxide (FOX) 102 is present at a semiconductor substrate 100 to define an active region (AR). A gate line (GL) crosses over the active region (AR). The gate line (GL) is composed of a gate oxide layer 104, a polysilicon layer 106, a tungsten layer 108, and a capping layer pattern 110 that are sequentially stacked. At this time, the gate oxide layer 104 may have a thickness of about 50˜300 Å, and the poly silicon layer 106 may have a thickness of about 700˜900 Å. The thickness of the tungsten layer 108 may be about 400˜600 Å, and that of the capping layer 110 may be 1900˜2100 Å. A spacer 114 a covers sidewalls of the gate line (GL). In the active region (AR), there is a low concentration impurity-doped region 112 to contact with side lower ends of the gate line (GL) and a high concentration impurity-doped region 115 to contact with those of the spacer 114 a. The end (E) is located on the field oxide 102 and covered by a protecting pattern (S) 114 b. The spacer 114 a and the protecting pattern (S) 114 b are formed of the same material and preferably of silicon nitride or silicon oxide. The protecting pattern (S) 114 b may have a thickness of 400˜600 Å.
  • FIGS. 4A through 4C are cross-sectional diagrams illustrating a method of forming the structure of FIG. 3.
  • Referring to FIG. 4A, a field oxide (FOX) 102 is formed on a semiconductor substrate 100 to define an active region (AR). A gate oxide layer 104, a polysilicon layer 106, a tungsten layer 108, and a capping layer 110 are sequentially stacked at an entire surface of the semiconductor substrate 100. The capping layer 110 may be formed of silicon nitride. The layers 110, 108, 106, and 104 are sequentially patterned to form a gate line (GL). A low concentration impurity-doped region 112 is formed in the active region (AR) by using the gate line (GL) as an ion-implantation mask.
  • Referring to FIGS. 4B and 4C, an insulation layer 114 is conformally stacked over an entire surface of the semiconductor substrate 100. The insulation layer 114 may be formed of silicon nitride or silicon oxide. A photoresist pattern (PR1) is formed to cover only the end (E) of the gate line (GL). The insulation layer 114 is anisotropically etched by using the photoresist pattern (PR1). Thus, as illustrated in FIG. 3, a spacer 114 a is formed to cover sidewalls of the gate line (GL) and, simultaneously, a protecting pattern (S) 114 b is formed to cover the end (E) of the gate line (GL). The photoresist pattern (PR1) is removed. A high concentration impurity-doped region 115 is formed in the active region (AR) of the semiconductor substrate 100 by using the gate line (GL), the spacer 114 a and the protecting pattern 114 b as ion-implantation masks.
  • According to this embodiment of the invention, since the protecting pattern (S) 114 b protects the end (E) of the gate line (GL), it is possible to prevent the tungsten from being damaged by a cleaning solution such as SC1.
  • FIG. 5 contains three cross-sectional diagrams of the semiconductor device shown in FIG. 2, taken along the line III-III′, the line IV-IV′, and the line V-V′, respectively, but in accordance with another embodiment of the invention.
  • Referring to FIGS. 2 and 5, a semiconductor device includes a spacer 114 a covering sidewalls and ends (E) of a gate line (GL) and a protecting pattern (S) 116 b covering the ends (E) of the gate line (GL). At this time, the spacer 114 a is interposed between the gate line (GL) and the protecting pattern (S) 116 b at the end (E) of the gate line (GL). The protecting pattern (S) 116 b may be thinner than the protecting pattern (S) 114 b of the embodiment of FIG. 3 and preferably may have a thickness of that is about one fifth the thickness of the protecting pattern (S) 114 b. The protecting pattern (S) 116 b may have a thickness of 80˜120 Å.
  • FIGS. 6A through 6C are cross-sectional diagrams illustrating a method of forming the structure of FIG. 5.
  • Referring to FIGS. 6A through 6C, an insulation layer 114 is entirely anisotropically etched at the state of FIG. 4B of the first embodiment, thereby forming a spacer 114 a covering sidewalls and ends (E) of the gate line (GL). A high concentration impurity-doped region 115 is formed in an active region (AR) of the semiconductor substrate 100 by using the gate line (GL) and the spacer 114 a as ion-implantation masks. A protecting layer 116 is stacked on an entire surface of the semiconductor substrate 100. At this time, the protecting layer 116 may be formed of the same material with the insulation layer 114. The protecting layer 116 may be formed in a thickness that is approximately one fifth the thickness of the insulation layer 114, and preferably is a thickness of 80˜120 Å. A photoresist pattern (PR2) is formed on the protecting layer 116 to cover the ends (E) of the gate line (GL). An anisotropic etch process is performed with respect to the protecting layer 116 by using the photoresist pattern (PR2) as an etch mask, thereby forming a protecting pattern (S) 116 b covering the ends (E) of the gate line (GL) but exposing the gate line (GL) on the active region (AR). The photoresist pattern (PR2) is removed. Except for the thickness of the protecting layer 116, the process conditions and other layers are identical to the embodiment illustrated in FIG. 3.
  • Embodiments of the invention will now be described in a non-limiting way.
  • Embodiments of the invention may include a semiconductor substrate, a gate line crossing over the semiconductor substrate, and a protecting pattern covering ends of the gate line. The protecting pattern may be formed of silicon nitride or silicon oxide.
  • Embodiments may further include a spacer covering sidewalls of the gate line and being interposed between the gate line and the protecting pattern at the ends of the gate line. The spacer may be formed of silicon nitride or silicon oxide. The gate line includes an oxide pattern and a conductive pattern that are sequentially stacked on the semiconductor substrate. The conductive pattern is formed of a metal selected from a group consisting of tungsten, aluminum and aluminum.
  • In accordance with an embodiment of the invention, the semiconductor device may be formed by the following method. First, a gate line is formed at a semiconductor substrate. A spacer is formed to cover sidewalls of the gate line. Next, a protecting pattern is formed to cover ends of the gate line.
  • In this method, the spacer and the protecting pattern may be simultaneously formed of the same material. The material may be silicon nitride or silicon oxide.
  • In this method, the gate line may be formed by sequentially stacking an oxide layer and a conductive layer on a semiconductor substrate and sequentially patterning the conductive layer and the oxide layer. The conductive layer may be formed of a metal selected from a group consisting of tungsten, copper, and aluminum.
  • According to embodiments of the invention, since the semiconductor substrate includes a protecting pattern covering ends of a gate line, the ends of the gate line are protected by the protecting pattern, thereby preventing gate electrodes from being damaged by a cleaning solution such as SC1 in a subsequent process.
  • Having described several exemplary embodiments of the invention, it is noted that various modifications may be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made to the particular embodiments of the invention disclosed above that are within the scope and the spirit of the invention as defined by the following appended claims.

Claims (5)

1. A method of forming a semiconductor device, comprising:
forming a gate line at a semiconductor substrate;
forming a spacer covering sidewalls of the gate line; and
forming a protecting pattern covering ends of the gate line.
2. The method of claim 1, wherein forming a spacer and forming a protecting pattern comprises forming the spacer and forming the protecting pattern simultaneously, wherein the spacer and the protecting pattern are formed of a same material.
3. The method of claim 2, wherein the same material is chosen from the group consisting of silicon nitride and silicon oxide.
4. The method of claim 1, wherein forming the gate line comprises:
sequentially stacking an oxide layer and a conductive layer on the semiconductor substrate; and
sequentially patterning the conductive layer and the oxide layer.
5. The method of claim 4, wherein the conductive layer is formed of a metal selected from the group consisting of tungsten, copper, and aluminum.
US11/135,775 2002-10-01 2005-05-23 Semiconductor device and method of forming the same Abandoned US20050213384A1 (en)

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US5695572A (en) * 1994-08-25 1997-12-09 Wacker Siltronic Gesellschaft Fur Halbleitermaterialien Aktiengesellschaft Cleaning agent and method for cleaning semiconductor wafers
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US6921919B2 (en) 2005-07-26

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