US20050112846A1 - Storage structure with cleaved layer - Google Patents
Storage structure with cleaved layer Download PDFInfo
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- US20050112846A1 US20050112846A1 US10/718,137 US71813703A US2005112846A1 US 20050112846 A1 US20050112846 A1 US 20050112846A1 US 71813703 A US71813703 A US 71813703A US 2005112846 A1 US2005112846 A1 US 2005112846A1
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- 238000003860 storage Methods 0.000 title claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000013078 crystal Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 8
- 239000004065 semiconductor Substances 0.000 claims description 7
- 230000005290 antiferromagnetic effect Effects 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 238000004891 communication Methods 0.000 claims description 3
- 230000005291 magnetic effect Effects 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims description 2
- 230000000873 masking effect Effects 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 54
- 235000012431 wafers Nutrition 0.000 description 44
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000003313 weakening effect Effects 0.000 description 2
- 230000002860 competitive effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000002939 deleterious effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021426 porous silicon Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Mram Or Spin Memory Techniques (AREA)
Abstract
Apparatus and method for making a multi-layered storage structure includes forming a device layer on a single-crystal wafer, cleaving the device layer from the wafer, repeating the forming and cleaving to provide a plurality of cleaved device layers, and bonding the cleaved device layers together to form the multi-layered storage structure.
Description
- The demand for semiconductor devices has increased dramatically over the years. Many frequently used electronic devices are made possible because of developments in semiconductor devices. As such devices become smaller, more sophisticated, and less expensive, the marketplace demands increasingly higher circuit densities, increased performance, and lower cost.
- Increasing the density of semiconductor devices has been accomplished by reducing associated component area. Photolithography is nearing X-ray energy levels, however, and is encountering limits in further size reductions. Three-dimensional semiconductor-based structures have provided additional opportunities to increase density, but error probabilities are multiplied as the number of stacked layers increases, and statistics of yield quickly become unsatisfactory.
- Crystal-based semiconductor devices generally provide better results than other devices, because regular arrays of atoms provide better electron movement than disordered arrays. At the same time, oxides are needed to keep electrons out of certain areas. Crystals cannot easily be stacked on top of amorphous or non-crystalline oxides, because crystal growth on top of a disordered substrate impedes proper registration of new atoms across the surface and often results in polycrystalline material. Additionally, once a device and a layer have been created, it is generally deleterious to subject them to further thermal input, as is often needed when a next layer is being formed. These and other challenges increase the difficulties and costs associated with stacked devices.
- Apparatus and method for making a multi-layered storage structure includes forming a device layer on a single-crystal wafer, cleaving the device layer from the wafer, repeating the forming and cleaving to provide a plurality of cleaved device layers, and bonding the cleaved device layers together to form the multi-layered storage structure.
-
FIG. 1 is a cross-sectional view of a silicon wafer with implanted and deposited devices, according to an embodiment of the invention. -
FIG. 2 is a cross-sectional view of theFIG. 1 wafer with a layer cleaved therefrom, according to an embodiment of the invention. -
FIG. 3 is a cross-sectional view of theFIG. 2 wafer and layer, with additional devices implanted and deposited on the wafer, according to an embodiment of the invention. -
FIG. 4 is a cross-sectional view of theFIG. 1 wafer with a second layer cleaved therefrom, according to an embodiment of the invention. -
FIG. 5 is a cross-sectional view of theFIG. 4 wafer and layers, with additional devices implanted and deposited on the wafer, according to an embodiment of the invention. -
FIG. 6 is a cross-sectional view of theFIG. 1 wafer with a third layer cleaved therefrom, according to an embodiment-of the invention. -
FIG. 7 is a cross-sectional view of three cleaved wafer layers bonded together, according to an embodiment of the invention. -
FIG. 8 is a cross-sectional view of a cleaved wafer applied to conductive traces, according to an embodiment of the invention. -
FIG. 9 is a cross-sectional view of diode pillars formed on conductive traces, according to an embodiment of the invention. -
FIG. 10 is a cross-sectional view of a metal layer applied to theFIG. 9 structure, according to an embodiment of the invention. -
FIG. 11 is a cross-sectional view of a cross-point array formed from theFIG. 10 structure, according to an embodiment of the invention. - A method of making a multi-layered memory or other electronic storage structure according to an embodiment of the invention includes forming
device layer 10 on single-crystal silicon wafer 15, as shown inFIG. 1 .Device layer 10 includes devices such as diodes, transistors, antifuses, tunnel junctions, etc., which are implanted, deposited, or otherwise formed or provided inlayer 10. Other examples of such devices include, but are not limited to, charge-coupled devices (CCDs), complementary metal oxide semiconductor (CMOS) imagers and other CMOS devices, tunnel diodes, charge pumps, and other devices. - As shown in
FIG. 2 , the method further includescleaving device layer 10 fromwafer 15.Cleaved portion 20 includesdevice layer 10 and cleavedwafer section 25. Ion-implantation induced layer splitting ofwafer 15, for example, using hydrogen or other light species, accomplishes the cleaving ofportion 20 fromwafer 15. The hydrogen or other ion penetrates to a desired depth and causes weakening at that depth upon heating. The weakening of the silicon layer causes cleavedwafer section 25 anddevice layer 10 to split or “peel” offwafer 15, allowing layer transfer to occur. According to another example, a layer of porous silicon is formed by anodic etching and annealing, to form the splitting layer. Other methods of cleavingportion 20 fromwafer 15 also are contemplated. - As shown in
FIG. 3 ,additional device layer 30 then is formed onwafer 15. As shown inFIG. 4 ,layer 30 and an associatedcleaved wafer section 35 together formcleaved wafer portion 40, which is cleaved fromwafer 15 in the same manner ascleaved wafer portion 20. The method thus includes repeating the forming and cleaving to provide a plurality of cleaved device layers originating from the same single-crystal silicon wafer 15.FIGS. 5-6 illustrate an additional repetition of the forming and cleaving, withadditional device layer 50 and associatedcleaved wafer section 55 forming anothercleaved wafer portion 60. - The method also includes, as shown in
FIG. 7 , bonding thecleaved device layers cleaved wafer sections sections wafer portions electronic storage structure 70, for example flash memory or other memory, a cross-point memory or other cross-point structure, one or more processors, etc.Structure 70 thus is a memory stack, for example, comprising a plurality ofbonded memory layers crystal silicon wafer 15.Structure 70 optionally is used in forming a three-dimensional cross-point array memory structure. -
FIGS. 8-11 illustrate a cross-point array structure having crystalline isolated diode pillars, using one or more cleaved wafers, and a method of making such a structure.Cleaved wafer portion 100 is provided from a wafer, such aswafer 15, in the manner described earlier. According to one example,wafer portion 100 is uniformly N-doped and/or forms N and P regions, as illustrated inFIG. 8 . Conductive traces, such asrow lines 105 formed of metal or silicide, for example, are provided on a base substrate or wafer (not shown).Cleaved portion 100 is placed over and bonded torow lines 105.Cleaved portion 100 includessacrificial wafer portion 110, which is removed by CMP or other process after bonding. - With reference to
FIG. 9 ,wafer portion 100 is lithographically etched to formvertical diodes 115. Viewed from the top,diodes 115 form a checkerboard pattern, according to one example. An interlayer dielectric (ILD) is applied, and a CMP process follows. Antiferromagnetic (AF)layer 120 then is applied, as shown inFIG. 10 .AF layer 120 is a stress-relieve-oxide (SRO)-type AF layer, according to one example, to provide thicker oxide and better manufacturing tolerance.Metal layer 125 then is deposited.FIG. 10 also illustratesoptional storage layer 130 applied betweenrow lines 105 anddiodes 115. - As shown in
FIG. 11 ,metal layer 125 then is etched to form columns orcolumn lines 135. ILD 140 then is deposited. CMP, application of additional layers, and/or other processing then occurs to form a complete cross-point structure. An insulating dielectric layer optionally is applied abovecolumn lines 135, for example, and then one or more additional complete sets ofrow lines 105,diodes 115,column lines 135 and/or other components added to form a stack of desired size, e.g. in the manner of layers orportions FIG. 7 . It should be noted that separate etching ofdiodes 115 as represented inFIG. 9 can be eliminated, andcolumn lines 135 instead used as a mask to creatediodes 115 inFIG. 11 . In either case, the resulting cross-point structure includesrow lines 105, crystallineisolated diode pillars 115crossing row lines 105,pillars 115 being formed from a cleaved wafer as described, andcolumn lines 135 crossingpillars 115 and row lines 105.Diode pillars 115 are together cleaved frome.g. wafer 15 in a layer orportion 100, which is applied above row lines 105.Diodes 115 are P-N diodes, as illustrated, but also optionally comprise Schottky diodes or PIN diodes if desired.Antiferromagnetic layer 120 is applied betweendiode pillars 115 andcolumn lines 135, andoptional storage layer 130 is applied betweenrow lines 105 anddiode pillars 115. The cross- point structure optionally comprises memory, such as magnetic memory or other nonvolatile memory. - According to additional embodiments, a method of making a cross-point array structure includes patterning and/or implanting a single-crystal silicon wafer such as
wafer 15, for example, with a pattern of squares generally in the manner of a checkerboard. A layer, such aslayer 100, is cleaved from the patterned wafer, and the cleaved layer is applied over conductive traces such as row lines 105. The cleaved layer optionally is a P-N layer or other layer, as mentioned previously.Layer 100 is etched to createvertical diodes 115 in communication withconductive traces 105. A secondconductive layer 125 is applied overlayer 100, and conductive traces such ascolumn lines 135 are patterned therefrom.Column lines 135 optionally are used in masking and patterning cleavedlayer 100. - Embodiments of the invention provide performance advantages associated with single-crystal silicon, e.g. for devices in the upper levels of the cross-point or other array or structure. Embodiments of the invention are used to produce memory, such as flash memory or other nonvolatile memory with ability to block erasure of stored information. Such nonvolatile memory is competitive in speed with dynamic RAM, or at least roughly comparable, and provides virtually instant-on capabilities even after a power-off condition. Embodiments of the invention also provide high density, and high performance with dynamic switching. Other aspects of the invention will be apparent to those of ordinary skill.
Claims (35)
1. A method of making a multi-layered storage structure, comprising:
forming a device layer on a single-crystal wafer;
cleaving the device layer from the wafer;
repeating the forming and cleaving to provide a plurality of cleaved device layers;
bonding the cleaved device layers together to form the multi-layered storage structure; and
forming a three-dimensional cross-point array memory structure using the bonded device layers.
2. The method of claim 1 , wherein the forming comprises implanting devices on the wafer.
3. The method of claim 1 , wherein the forming comprises forming a device layer comprising devices selected from the group consisting of diodes, transistors, antifuses, and tunnel junctions.
4. A method of making a multi-layered storage structure, comprising:
forming a device layer on a single-crystal wafer;
cleaving the device layer from the wafer;
repeating the forming and cleaving to provide a plurality of cleaved device layers; and
bonding the cleaved device layers together to form the multi-layered storage structure, wherein the forming comprises forming a device layer comprising vertical diodes; further wherein the storage structure is a vertical memory structure.
5. The method of claim 1 , wherein the repeating comprises forming the plurality of cleaved device layers from the same single-crystal wafer.
6. The method of claim 1 , wherein the bonding comprises plasma-activated bonding.
7. (canceled)
8. The method of claim 1 , wherein the cleaving comprises ion-implantation induced layer splitting of the wafer.
9. The method of claim 1 , wherein the cleaving comprises anodic etching and annealing of the wafer.
10. The method of claim 1 , wherein the storage structure comprises memory or a processor.
11. A cross-point memory structure, comprising:
crystalline isolated diode pillars formed from a cleaved wafer layer;
row lines crossing the crystalline isolated diode pillars; and
column lines crossing the crystalline isolated diode pillars and the row lines.
12. The structure of claim 11 , wherein the diode pillars are together cleaved from the wafer in a layer, the layer being applied next to the row lines.
13. The structure of claim 11 , wherein the diode pillars comprise Schottky diodes.
14. The structure of claim 11 , wherein the diode pillars comprise diodes selected from the group consisting of P-N diodes and PIN diodes.
15. The structure of claim 11 , further comprising an antiferromagnetic layer applied between the diode pillars and the column lines.
16. The structure of claim 11 , further comprising a storage layer applied between the row lines and the diode pillars.
17. The structure of claim 11 , wherein the memory structure comprises magnetic memory.
18. A method of making a cross-point array structure, comprising:
patterning a single-crystal silicon wafer;
cleaving a layer from the patterned wafer; and
applying the cleaved layer over conductive traces.
19. The method of claim 18 , wherein the layer is a P-N layer.
20. The method of claim 18 , further comprising etching the layer to create a plurality of vertical diodes in communication with the conductive traces.
21. The method of claim 18 , wherein the conductive traces are first conductive traces, the method further comprising forming second conductive traces over the cleaved layer.
22. The method of claim 21 , further comprising using the second conductive traces in masking and patterning the cleaved layer.
23. A memory stack comprising a plurality of bonded memory layers, each memory layer being cleaved from a single-crystal silicon wafer.
24. The memory stack of claim 23 , wherein the memory layers each comprise devices selected from the group consisting of diodes, transistors, antifuses, and tunnel junctions.
25. The memory stack of claim 23 , wherein the memory layers comprise vertical diodes.
26. Apparatus for making a cross-point array structure, comprising:
means for patterning a single-crystal silicon wafer;
means for cleaving a layer from the patterned wafer; and
means for applying the cleaved layer over conductive traces.
27. The apparatus of claim 26 , further comprising means for etching the layer to create a plurality of vertical diodes in communication with the conductive traces.
28. The apparatus of claim 26 , wherein the conductive traces are first conductive traces, the apparatus further comprising means for forming second conductive traces over the cleaved layer.
29. A method of making a multi-layered storage structure, comprising:
forming a first device layer on a semiconductor substrate;
cleaving, from the substrate, the first device layer and a first substrate section, the first substrate section being below the first device layer and including a first portion of the substrate;
forming a second device layer on the substrate;
cleaving, from the substrate, the second device layer and a second substrate section, the second substrate section being below the second device layer and including a second portion of the substrate; and
bonding the first and second device layers to form the multi-layered storage structure.
30. The method of claim 29 further comprising forming diodes on the first and second device layers.
31. The method of claim 29 further comprising forming a magnetic memory structure on the first and second device layers.
32. The method of claim 29 further comprising planarizing surfaces of the first and second substrate sections before bonding the first and second device layers.
33. The method of claim 29 further comprising polishing surfaces of the first and second substrate sections to define metal interconnection patterns before bonding the first and second device layers.
34. The method of claim 29 , wherein the multi-layered storage structure is a vertical memory structure.
35. The method of claim 29 further comprising forming a three-dimensional cross-point array memory structure with the first and second device layers.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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US10/718,137 US6967149B2 (en) | 2003-11-20 | 2003-11-20 | Storage structure with cleaved layer |
GB0425067A GB2409336A (en) | 2003-11-20 | 2004-11-12 | Multi-layered storage device with cleaved layers |
JP2004333976A JP2005159350A (en) | 2003-11-20 | 2004-11-18 | Method of fabricating multi-layered storage structure, cross-point memory structure and memory stack |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US10/718,137 US6967149B2 (en) | 2003-11-20 | 2003-11-20 | Storage structure with cleaved layer |
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US20050112846A1 true US20050112846A1 (en) | 2005-05-26 |
US6967149B2 US6967149B2 (en) | 2005-11-22 |
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US10/718,137 Expired - Fee Related US6967149B2 (en) | 2003-11-20 | 2003-11-20 | Storage structure with cleaved layer |
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JP (1) | JP2005159350A (en) |
GB (1) | GB2409336A (en) |
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US20080272363A1 (en) * | 2007-05-01 | 2008-11-06 | Chandra Mouli | Selectively Conducting Devices, Diode Constructions, Constructions, and Diode Forming Methods |
US20080273363A1 (en) * | 2007-05-01 | 2008-11-06 | Chandra Mouli | Semiconductor Constructions, Electronic Systems, And Methods of Forming Cross-Point Memory Arrays |
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US20090290407A1 (en) * | 2008-05-22 | 2009-11-26 | Chandra Mouli | Memory Cells, Memory Cell Constructions, and Memory Cell Programming Methods |
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Also Published As
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GB0425067D0 (en) | 2004-12-15 |
JP2005159350A (en) | 2005-06-16 |
GB2409336A (en) | 2005-06-22 |
US6967149B2 (en) | 2005-11-22 |
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