US20050104645A1 - Circuit for generating from low voltage edges higher voltage pulses having precise amplitudes and durations - Google Patents
Circuit for generating from low voltage edges higher voltage pulses having precise amplitudes and durations Download PDFInfo
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- US20050104645A1 US20050104645A1 US11/014,647 US1464704A US2005104645A1 US 20050104645 A1 US20050104645 A1 US 20050104645A1 US 1464704 A US1464704 A US 1464704A US 2005104645 A1 US2005104645 A1 US 2005104645A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6877—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the control circuit comprising active elements different from those used in the output circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
- H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
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- pulses having precisely defined widths are common in many types of electronic circuits. Such pulses can be created with digital logic. It often happens that such a pulse is required to define more than just a width in time; for example, when it is applied to an integrator that is also responsive to the amplitude of that pulse. A common instance of this is when a pulse of precision width and voltage drives an integrator input resistor. Such precision current pulses must have not only a precise duration, but also a precise amplitude, since the total amount of charge applied to the integrator is (for an ideally shaped pulse) a product of the two.
- Precise current pulses are often used in conjunction with integrators in such applications as DACs (Digital to Analog Converters), which in turn may be used in the precision ADCs (Analog to Digital Converters) that are found in laboratory quality digital multi-meters.
- DACs Digital to Analog Converters
- ADCs Analog to Digital Converters
- a third option is to use a modern low voltage high speed logic family for pulse-edge generation, and then apply that to a switching mechanism to shift its level to a suitably high voltage obtained from a stable reference voltage.
- a low voltage source of input edges for a current pulse of precision amplitude and duration is applied to an input buffer to provide a low impedance source whose output is AC coupled to a positive edge differentiator and also to a negative edge differentiator.
- Each differentiator briefly drives ON a corresponding normally OFF switch, the pair of which switches are in series between first power supplies of opposite polarity, and whose junction serves as an impulse driver and that may be clamped to symmetrical opposing reference voltages less than the voltages of the first power supplies.
- the clamped impulse driver may also be coupled to a bi-stable switch driver that responds to a positive impulse driver voltage by applying thereto through a coupling resistor a percentage of the negative first power supply voltage.
- the bi-stable switch driver responds to a negative impulse driver voltage by applying thereto through the coupling resistor a percentage of the positive first power supply voltage.
- the bi-stable switch driver changes state each time input edges of alternating polarity are applied to the input buffer.
- the impulse driver is also coupled to the gates of a complementary pair of MOSFET switches that are in series between precise reference voltages of opposing polarities, and whose common junction may be connected to a current determining resistance whose other end is connected to a using circuit, such as an integrator.
- the output of the MOSFET switches may be assisted by an auxiliary bi-stable output driver that reduces the amount of load current drawn from those MOSFETs, and thereby reduces errors arising from thermally induced variations in their ON resistance.
- the precise reference voltages may be the same as the symmetrical opposing references.
- FIG. 1 is a simplified block diagram of a voltage measurement architecture that provides an occasion for practicing the invention
- FIG. 2 is a simplified schematic portion of the DAC mechanism in FIG. 1 , wherein current pulses are generated from the low voltage edges of a pulse width modulated signal;
- FIG. 3 is a schematic portion of the DAC mechanism in FIG. 1 , and includes further improvements for greater accuracy and linearity.
- FIG. 1 wherein is shown a simplified block diagram representation 1 of a voltage measurement technique known as the ⁇ architecture.
- the ⁇ architecture itself may be used, for example, in digital multi-meters ranging from the mid-range of performance to equipment at the very top of the line (e.g., a multi-meter such as the Agilent 3458A).
- a voltage V IN 2 to be measured is applied to the +input of a SUMMING JUNCTION 3 , whose output is coupled to an INTEGRATOR 4 .
- a feed-back balancing voltage ( 9 ) will be developed whose average value is equal to minus V IN . This is applied to the other input of the SUMMING JUNCTION 3 , such that if this condition is maintained for a suitable period of time, the output of the SUMMING JUNCTION will be zero, and the output of the INTEGRATOR will effectively cease changing.
- the output of the TEGRATOR is applied to an ADC, and is a digital representation of V IN (again, assuming that balance has been achieved).
- That digital representation is applied to an output display mechanism (or perhaps put to some other use), and it is also applied to a DAC from which issues the feed back balancing voltage 9 .
- This has been a very simplified look at the ⁇ architecture, and we have ignored many topics important to an actual full scale implementation, such as input amplifiers and attenuators. Nevertheless, it will serve out purpose here.
- FIG. 1 Our interest in FIG. 1 is in what goes on inside the DAC 8 . It receives a collection of digital values, probably of many bits representing, say, four to eight decimal digits. It needs to turn that back into an analog voltage within some range, say, ⁇ 7V . . . +7V. Let us assume that, as is often done, the binary representation from the ADC 6 has been used to create pulses whose widths are precisely defined by low voltage edges of perhaps, three to five volts. These pulse width modulated input signals are too small to create average values up to seven volts that will cancel the applied input at the SUMMING JUNCTION.
- FIG. 2 wherein is shown a simplified schematic diagram 10 of a basic circuit for creating precision pulses from the edges of low-voltage pulse width modulated signals 11 .
- the low voltage edges 11 are applied to a DIFFERENTIATING IMPULSE DRIVER circuit that has two portions, one for each polarity transition in the low voltage edges 11 .
- Buffer 12 , capacitor 14 and transistor 16 respond to negative transitions, while buffer 13 , capacitor 15 and transistor 17 respond to positive transitions. Between transitions the transistors 16 and 17 are both normally OFF.
- Both capacitors will differentiate it, but only transistor 17 will respond, by turning ON very briefly, producing a negative impulse derived from the negative power supply 20 .
- the time constants are chosen so that the ON time is in the range of 2% to 5% of the maximum, or total, pulse width period. In a similar fashion, a negative transition will briefly turn transistor 160 N, producing a positive impulse derived from the positive power supply 19 .
- transistors 16 and 17 are mostly OFF, which is desirable for reduced power consumption and heating related behavior changes.
- ON time is a function of just time constants, and NOT a function of pulse width. If their ON times were a function of input pulse width, then an avenue for undesirable non-linear operation is opened.
- Capacitor 21 may be a discrete part, or be the gate capacitances of the MOSFETs 22 and 23 , or a combination of both.
- FIG. 3 is a more detailed schematic 28 for a more sophisticated application of the basic technique set out in FIG. 2 .
- the basic operation of the circuit 28 is the same, so we shall discuss only the incremental functionality provided by the additional components.
- the input buffers for the DIFFERENTIATING IMPULSE DRIVER 29 have been made quite robust by operating several parts in parallel ( 12 a - c and 13 a - c ). This is in keeping with the speeds being reasonably high and the impedance to be driven being fairly low.
- the range of pulse widths is 300 ns to 1,700 ns, with rise times in the low nanoseconds and a 500 KHz repetition rate.
- the next topic of interest is the addition of the BI-STABLE SWITCH DRIVER 30 .
- it is connected between ground and the junction node 18 of the two transistors 16 and 17 of the IMPULSE DRIVER 29 .
- Capacitor 21 is now absent, save for what unavoidable strays and device capacitances (for transistors 22 and 23 ) remain. In fact, rather than have a capacitance there to act as a voltage storage mechanism, we now prefer that there be as little capacitance from node 18 to ground as possible. But something has to perform the “store-and-hold” function that allows transient impulses from the IMPULSE DRIVER 29 to cause a steady pulse output from the MOSFET SWITCHES 22 and 23 .
- the BI-STABLE SWITCH DRIVER 30 does is drive node 18 with a positive or negative voltage that is larger than the plus and minus 7V CLAMP voltages, respectively.
- the BI-STABLE SWITCH DRIVER is triggered, or switched, from one state or the other by an impulse of the corresponding polarity from the IMPULSE DRIVER 29 . It then drives node 18 (i.e., one of the clamp diodes 32 and 33 ) through resistor 38 , which then maintains a steady drive to the MOSFET SWITCHES 35 until the next transition in the LOW VOLTAGE EDGES 11 .
- the reason for the 100 ⁇ resistor 34 is also now apparent: it is large enough to keep the rather gutsy transient from the IMPULSE DRIVER from frying the diodes 32 and 33 and glitching the associated power supplies, yet small enough to not interfere with the clamping action.
- the clamping action is important for error reduction, for the following reason. If the drive to the MOSFET SWITCHES 35 was not clamped, then it would in all likelihood exhibit droop or other non-constant behavior between transitions.
- the amount of droop will be a function of how long it is allowed to occur, which is to say, it will be a function of pulse duration. This is bad, because when a transition does occur after there has been some droop (or other drift), the further excursion in voltage needed to reach the threshold for switching the MOSFETs will be different from one instance to the next, according to the amount of droop. Since the slewing rates are finite, that translates into a pulse width dependent timing error in edge placement for the output pulse. Clamping fixes things so that any such effect of slewing rate/excursion to the threshold is constant for all pulses, which in essence, cancels the effect.
- AUXILIARY BI-STABLE OUTPUT DRIVER 31 Another element that has been added to FIG. 3 is the AUXILIARY BI-STABLE OUTPUT DRIVER 31 . It is another bi-stable voltage driven current source, built around amplifier 37 and coupled to a node (in this case line 26 ) through resistor 39 . That is, when MOSFET 22 is ON, a positive voltage (and its current) is supplied by AUXILIARY BI-STABLE OUTPUT DRIVER 31 , which is essentially an additional source in parallel with MOSFET 22 . A similar negative voltage (and its current) is supplied when MOSFET 23 is ON, instead.
- the MOSFET's 22 and 23 each have an ON resistance of about 10 ⁇ . It would not be so bad if that value were constant, but it unfortunately varies as a function of temperature, and produces performance variations that are detectable.
- the circuit 28 shown in FIG. 3 is capable of precision operation.
- the error in edge placement for the output pulses, relative to the input edges, can, with reasonable care, be made to be on the order of 2/10 ppm.
- appropriate care must be exercised with the various reference and supply voltages, as well as with component selection generally.
- FIG. 3 actual component values and device specifiers for an embodiment that meets the 2/10 ppm performance specification.
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Abstract
A low voltage source of input edges for a pulse of precision duration is applied to an input buffer to provide a low impedance source whose output is AC coupled to positive and negative edge differentiators. Each differentiator briefly drives ON a corresponding normally OFF switch, the pair of which switches serves as an impulse driver and that may be clamped to symmetrical opposing reference voltages. The clamped impulse driver may also be coupled to a bi-stable switch driver that responds to a particular polarity impulse driver voltage by applying thereto through a load resistor a percentage of a power supply voltage of opposite polarity. The bi-stable switch driver changes state each time input edges of alternating polarity are applied to the input buffer. The impulse driver is also coupled to the gates of a complementary pair of MOSFET switches that are in series between precise reference voltages of opposing polarities, and whose common junction may be connected to a current determining resistance whose other end is connected to a using circuit, such as an integrator. The output of the MOSFET switches may be assisted by an auxiliary bi-stable output driver that reduces the amount of load current drawn from those MOSFETs, and thereby reduces errors arising from thermally induced variations in their on resistance.
Description
- The use of pulses having precisely defined widths is common in many types of electronic circuits. Such pulses can be created with digital logic. It often happens that such a pulse is required to define more than just a width in time; for example, when it is applied to an integrator that is also responsive to the amplitude of that pulse. A common instance of this is when a pulse of precision width and voltage drives an integrator input resistor. Such precision current pulses must have not only a precise duration, but also a precise amplitude, since the total amount of charge applied to the integrator is (for an ideally shaped pulse) a product of the two. Precise current pulses are often used in conjunction with integrators in such applications as DACs (Digital to Analog Converters), which in turn may be used in the precision ADCs (Analog to Digital Converters) that are found in laboratory quality digital multi-meters.
- Two trends in current practices have introduced a difficulty in the design of a precision pulsed current source. The first is the trend to place ever more circuitry onto a single IC (Integrated Circuit). While this has many advantages in some respects, it does limit what mix of semiconductor processes is available, and places a premium of keeping power dissipation to a minimum. A second trend in response to the first is that the industry has developed low voltage high speed logic families that operate on 5V or less. It is possible to generate high speed precisely placed pulse edges with these low voltage logic families, but when converted to current pulses the low voltages involved give rise to undesirable reductions in signal to noise ratios. Very often, the designer would prefer to have a much higher voltage to work with, but is compelled to either use the low voltage associated with the newer logic family and suffer the loss in precision, or use an older (and perhaps less available) process with a higher voltage. A third option is to use a modern low voltage high speed logic family for pulse-edge generation, and then apply that to a switching mechanism to shift its level to a suitably high voltage obtained from a stable reference voltage. A number of challenges arise when this latter approach is used in a system that is expected to be extremely accurate, and just how to do it is a significant problem in its own right.
- A low voltage source of input edges for a current pulse of precision amplitude and duration is applied to an input buffer to provide a low impedance source whose output is AC coupled to a positive edge differentiator and also to a negative edge differentiator. Each differentiator briefly drives ON a corresponding normally OFF switch, the pair of which switches are in series between first power supplies of opposite polarity, and whose junction serves as an impulse driver and that may be clamped to symmetrical opposing reference voltages less than the voltages of the first power supplies. The clamped impulse driver may also be coupled to a bi-stable switch driver that responds to a positive impulse driver voltage by applying thereto through a coupling resistor a percentage of the negative first power supply voltage. The bi-stable switch driver responds to a negative impulse driver voltage by applying thereto through the coupling resistor a percentage of the positive first power supply voltage. The bi-stable switch driver changes state each time input edges of alternating polarity are applied to the input buffer. The impulse driver is also coupled to the gates of a complementary pair of MOSFET switches that are in series between precise reference voltages of opposing polarities, and whose common junction may be connected to a current determining resistance whose other end is connected to a using circuit, such as an integrator. The output of the MOSFET switches may be assisted by an auxiliary bi-stable output driver that reduces the amount of load current drawn from those MOSFETs, and thereby reduces errors arising from thermally induced variations in their ON resistance. The precise reference voltages may be the same as the symmetrical opposing references.
-
FIG. 1 is a simplified block diagram of a voltage measurement architecture that provides an occasion for practicing the invention; -
FIG. 2 is a simplified schematic portion of the DAC mechanism inFIG. 1 , wherein current pulses are generated from the low voltage edges of a pulse width modulated signal; and -
FIG. 3 is a schematic portion of the DAC mechanism inFIG. 1 , and includes further improvements for greater accuracy and linearity. - Refer now to
FIG. 1 , wherein is shown a simplifiedblock diagram representation 1 of a voltage measurement technique known as the ΔΣ architecture. We shall describe it briefly, as the subject matter we are interested in can be put to use in the ΔΣ architecture. The ΔΣ architecture itself may be used, for example, in digital multi-meters ranging from the mid-range of performance to equipment at the very top of the line (e.g., a multi-meter such as the Agilent 3458A). - A
voltage V IN 2 to be measured is applied to the +input of a SUMMING JUNCTION 3, whose output is coupled to anINTEGRATOR 4. When, in the course of events, the measurement is concluded, a feed-back balancing voltage (9) will be developed whose average value is equal to minus VIN. This is applied to the other input of the SUMMING JUNCTION 3, such that if this condition is maintained for a suitable period of time, the output of the SUMMING JUNCTION will be zero, and the output of the INTEGRATOR will effectively cease changing. The output of the TEGRATOR is applied to an ADC, and is a digital representation of VIN (again, assuming that balance has been achieved). That digital representation is applied to an output display mechanism (or perhaps put to some other use), and it is also applied to a DAC from which issues the feedback balancing voltage 9. This has been a very simplified look at the ΔΣ architecture, and we have ignored many topics important to an actual full scale implementation, such as input amplifiers and attenuators. Nevertheless, it will serve out purpose here. - Our interest in
FIG. 1 is in what goes on inside theDAC 8. It receives a collection of digital values, probably of many bits representing, say, four to eight decimal digits. It needs to turn that back into an analog voltage within some range, say, −7V . . . +7V. Let us assume that, as is often done, the binary representation from theADC 6 has been used to create pulses whose widths are precisely defined by low voltage edges of perhaps, three to five volts. These pulse width modulated input signals are too small to create average values up to seven volts that will cancel the applied input at the SUMMING JUNCTION. If we used the smaller amplitude pulse width modulated signals (say, 3-5 V) directly, we would have to scale VIN down in amplitude, and would incur an increased signal to noise ratio during operation. Thus, we are compelled to “stretch” the low voltage pulse width modulated signals vertically (in voltage) in order to proceed. How to do that is the subject matter ofFIGS. 2 and 3 . - Refer now to
FIG. 2 , wherein is shown a simplified schematic diagram 10 of a basic circuit for creating precision pulses from the edges of low-voltage pulse width modulatedsignals 11. Thelow voltage edges 11 are applied to a DIFFERENTIATING IMPULSE DRIVER circuit that has two portions, one for each polarity transition in thelow voltage edges 11.Buffer 12,capacitor 14 andtransistor 16 respond to negative transitions, whilebuffer 13,capacitor 15 andtransistor 17 respond to positive transitions. Between transitions thetransistors transistor 17 will respond, by turning ON very briefly, producing a negative impulse derived from thenegative power supply 20. The time constants are chosen so that the ON time is in the range of 2% to 5% of the maximum, or total, pulse width period. In a similar fashion, a negative transition will briefly turn transistor 160N, producing a positive impulse derived from thepositive power supply 19. - An advantage of the arrangement shown for
transistors - When
transistor 17 turns ON, a brief negative spike, or voltage impulse, appears atnode 18 and is applied to, and charges,capacitor 21. This negative voltage will turn MOSFET switch 220N, while turningMOSFET switch 23 OFF. Thus, a positive transition in thelow voltage edges 11 will result in the positivepower supply voltage 24 being the source for an output pulse onoutput line 26 that is applied to resistor 27 (to make it a current pulse for an integrator that is not shown). The positive voltage atoutput 26 will remain until a subsequent negative transition in thelow voltage edges 11 produces a positive impulse fromtransistor 16 that dischargescapacitor 21 from its previous negative value and charges it to the new positive one. That causesMOSFET switch 23 to turn ON, andMOSFET switch 22 to turn OFF. The result is that thepulse output line 26 is pulled to the value ofpower supply voltage 25.Capacitor 21 may be a discrete part, or be the gate capacitances of theMOSFETs - It will be noted that when a steady sequence of alternating polarity low voltage edges 11 is applied, the two
MOSFET switches MOSFETs - Refer now to
FIG. 3 , which is a more detailed schematic 28 for a more sophisticated application of the basic technique set out inFIG. 2 . We have kept the reference numerals the same in locations where the parts are in good correspondence, and have added new ones elsewhere. The basic operation of thecircuit 28 is the same, so we shall discuss only the incremental functionality provided by the additional components. - It will be noted that the input buffers for the DIFFERENTIATING
IMPULSE DRIVER 29 have been made quite robust by operating several parts in parallel (12 a-c and 13 a-c). This is in keeping with the speeds being reasonably high and the impedance to be driven being fairly low. For example, in one embodiment the range of pulse widths is 300 ns to 1,700 ns, with rise times in the low nanoseconds and a 500 KHz repetition rate. - The next topic of interest is the addition of the
BI-STABLE SWITCH DRIVER 30. First, it is connected between ground and thejunction node 18 of the twotransistors IMPULSE DRIVER 29.Capacitor 21 is now absent, save for what unavoidable strays and device capacitances (fortransistors 22 and 23) remain. In fact, rather than have a capacitance there to act as a voltage storage mechanism, we now prefer that there be as little capacitance fromnode 18 to ground as possible. But something has to perform the “store-and-hold” function that allows transient impulses from theIMPULSE DRIVER 29 to cause a steady pulse output from the MOSFET SWITCHES 22 and 23. That something is theBI-STABLE SWITCH DRIVER 30, which is an active network built aroundamplifier 36. In addition, the voltage swing atnode 18 has been clamped through resistor 34 (a save-the-diodes current limit) bydiode 32 to a +7V CLAMP voltage, and bydiode 33 to a −7V CLAMP voltage. - What the
BI-STABLE SWITCH DRIVER 30 does is drivenode 18 with a positive or negative voltage that is larger than the plus and minus 7V CLAMP voltages, respectively. The BI-STABLE SWITCH DRIVER is triggered, or switched, from one state or the other by an impulse of the corresponding polarity from theIMPULSE DRIVER 29. It then drives node 18 (i.e., one of theclamp diodes 32 and 33) throughresistor 38, which then maintains a steady drive to the MOSFET SWITCHES 35 until the next transition in the LOW VOLTAGE EDGES 11. - Another way to think of the
BI-STABLE SWITCH DRIVER 30 is as a voltage driven current source. It “follows” the brief but powerful transient provided by the IMPULSE DRIVER, and once perturbed has a source voltage higher than the associated CLAMP voltage. The clamping action wins, however, and the clamped voltage substitutes for the now absent transient impulse drive. Butthe voltage responsive current source behavior remains, now in response to the clamping of its own output. The action is rather like a latch. - The reason for the 100
Ω resistor 34 is also now apparent: it is large enough to keep the rather gutsy transient from the IMPULSE DRIVER from frying thediodes - The clamping action is important for error reduction, for the following reason. If the drive to the MOSFET SWITCHES 35 was not clamped, then it would in all likelihood exhibit droop or other non-constant behavior between transitions. The amount of droop will be a function of how long it is allowed to occur, which is to say, it will be a function of pulse duration. This is bad, because when a transition does occur after there has been some droop (or other drift), the further excursion in voltage needed to reach the threshold for switching the MOSFETs will be different from one instance to the next, according to the amount of droop. Since the slewing rates are finite, that translates into a pulse width dependent timing error in edge placement for the output pulse. Clamping fixes things so that any such effect of slewing rate/excursion to the threshold is constant for all pulses, which in essence, cancels the effect.
- Another element that has been added to
FIG. 3 is the AUXILIARYBI-STABLE OUTPUT DRIVER 31. It is another bi-stable voltage driven current source, built aroundamplifier 37 and coupled to a node (in this case line 26) throughresistor 39. That is, whenMOSFET 22 is ON, a positive voltage (and its current) is supplied by AUXILIARYBI-STABLE OUTPUT DRIVER 31, which is essentially an additional source in parallel withMOSFET 22. A similar negative voltage (and its current) is supplied whenMOSFET 23 is ON, instead. When one of the MOSFET SWITCHES is ON, (producing a known ±7V) the associated output voltage would source or sink a particular current through resistor 27 (its other end being a virtual ground provided by the integrator). The component values chosen for the AUXILIARYBI-STABLE OUTPUT DRIVER 31 are such that IT supplies almost all of that current, leaving only a very little to be supplied by the MOSFET SWITCHES themselves. The reason for having the AUXILIARYBI-STABLE OUTPUT DRIVER 31 is as follows. - The MOSFET's 22 and 23 each have an ON resistance of about 10 Ω. It would not be so bad if that value were constant, but it unfortunately varies as a function of temperature, and produces performance variations that are detectable. By providing the extra drive from the AUXILIARY BI-STABLE OUTPUT DRIVER 31 (most of the current through the
integrator load resistor 27 actually is due to sourcing and sinking by the AUXILIARY BI-STABLE OUTPUT DRIVER) those temperature induced variations are swamped out. That is, the voltage drop across that temperature variable ON resistance is made very low, since almost no current flows through it. - The
circuit 28 shown inFIG. 3 is capable of precision operation. The error in edge placement for the output pulses, relative to the input edges, can, with reasonable care, be made to be on the order of 2/10 ppm. For the integrated output to have that kind of accuracy, appropriate care must be exercised with the various reference and supply voltages, as well as with component selection generally. And although there may be many combinations of passive component values and choices for active devices, in the interest of complete disclosure we have included inFIG. 3 actual component values and device specifiers for an embodiment that meets the 2/10 ppm performance specification. - Lastly, we note that in some applications it may be desirable for the pulse generation circuits shown to operate in an unbalanced configuration, say, between ground and a thirty-six volt supply. This may be readily accomplished an appropriate shift in the various other voltages. Also, it will be discovered by those who try it that the generation of pulses of much higher voltage is possible, too.
Claims (10)
1. A method of producing pulses from a sequence of input signal edges that alternate in polarity, the method comprising the steps of:
(a) differentiating positive transitions of the input signal edges;
(b) amplifying the differentiated positive transition of step (a);
(c) differentiating negative transitions of the input signal edges;
(d) amplifying the differentiated negative transition of step (c);
(e) alternately charging a capacitance with the amplified differentiated transitions of step (b) and with the amplified differentiated transitions of step (d);
(f) driving a load to a positive power supply voltage with a switched ON first FET when the capacitance is charged to a first polarity;
(e) driving the load to a negative power supply voltage with a switched ON second FET when the capacitance is charged to a second polarity; and
(f) one of the first and second FETs being an N-type FET and the other being a P-type FET.
2. A method as in claim 1 wherein the first and second FETs are in series and the polarities of the FETs are chosen to create make-before-break operation.
3. A method as in claim 1 wherein the first and second FETs are in series and the polarities of the FETs are chosen to create break-before-make operation.
4. A method as in claim 1 wherein the load is a resistor coupled to the input of an integrator and further comprising the step of integrating current pulses formed by the switching of the first and second FETs.
5. Pulse production apparatus comprising:
an impulse driver having an input for receiving a sequence of input signal edges that alternate in polarity, that differentiates the input signal edges into positive and negative impulse transients, and that separately amplifies the positive and the negative impulse transients and presents the amplifications at a common output of the impulse driver;
a capacitance coupled between the common output of the impulse driver and an AC ground;
a complementary pair of FET switches in series with each other, the complementary pair in parallel with a supply voltage, and the gates of the complementary pair of FET switches each being connected to the common output of the impulse driver; and
the junction of the complementary pair of FET switches in series being a pulse output coupled to supply an output pulse.
6. Apparatus as in claim 5 wherein the order of the complementary pair of FET switches as they are in parallel with the supply voltage produces make-before-break operation.
7. Apparatus as in claim 5 wherein the order of the complementary pair of FET switches as they are in parallel with the supply voltage produces break-before-make operation.
8. Apparatus as in claim 5 further comprising a integrator having an input and also further comprising an integrator input resistor coupled between the pulse output and the input of the integrator.
9. Apparatus as in claim 5 wherein the peak-to-peak voltage of the output pulse is greater than the peak-to-peak voltage of the input signal edges that alternate in polarity.
10-20. (canceled)
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---|---|---|---|
US10/631,703 Expired - Lifetime US6876241B2 (en) | 2003-07-31 | 2003-07-31 | Circuit for generating from low voltage edges higher voltage pulses having precise amplitudes and durations |
US11/014,647 Abandoned US20050104645A1 (en) | 2003-07-31 | 2004-12-16 | Circuit for generating from low voltage edges higher voltage pulses having precise amplitudes and durations |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/631,703 Expired - Lifetime US6876241B2 (en) | 2003-07-31 | 2003-07-31 | Circuit for generating from low voltage edges higher voltage pulses having precise amplitudes and durations |
Country Status (2)
Country | Link |
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US (2) | US6876241B2 (en) |
JP (1) | JP2005057739A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI742257B (en) * | 2018-03-16 | 2021-10-11 | 力智電子股份有限公司 | Pulse-width modulation controller and tri-state voltage generation method |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7565463B2 (en) * | 2005-04-22 | 2009-07-21 | Sun Microsystems, Inc. | Scalable routing and addressing |
US7176819B1 (en) * | 2005-09-08 | 2007-02-13 | Agilent Technologies, Inc. | Precision low noise-delta-sigma ADC with AC feed forward and merged coarse and fine results |
US7521969B2 (en) * | 2006-07-28 | 2009-04-21 | Lattice Semiconductor Corporation | Switch sequencing circuit systems and methods |
PL3294653T3 (en) * | 2015-05-14 | 2022-07-18 | SVEJKOVSKY, Karen Sue | In-line adjustable gate |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3160766A (en) * | 1962-11-28 | 1964-12-08 | Rca Corp | Switching circuit with a capacitor directly connected between the bases of opposite conductivity transistors |
US3621141A (en) * | 1964-12-17 | 1971-11-16 | Xerox Corp | Dicode decoder |
US3751682A (en) * | 1971-12-17 | 1973-08-07 | Sperry Rand Corp | Pulsed voltage driver for capacitive load |
US4808845A (en) * | 1985-12-02 | 1989-02-28 | Hitachi, Ltd. | High voltage pulse generating semiconductor circuit with improved driving arrangement |
US5677647A (en) * | 1995-10-20 | 1997-10-14 | Tektronix, Inc. | High power pulse waveform generator |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62199118A (en) * | 1986-02-27 | 1987-09-02 | Toshiba Corp | Interface circuit between analog logics |
JP2963192B2 (en) * | 1990-11-27 | 1999-10-12 | 日本電信電話株式会社 | Level conversion circuit |
JPH06314772A (en) * | 1993-04-28 | 1994-11-08 | Fuji Electric Co Ltd | Semiconductor integrated circuit device |
JP3728046B2 (en) * | 1996-06-26 | 2005-12-21 | 沖電気工業株式会社 | Polarity reversal detection circuit |
US6040707A (en) * | 1997-09-15 | 2000-03-21 | Intersil Corporation | Constant slew rate amplifier |
-
2003
- 2003-07-31 US US10/631,703 patent/US6876241B2/en not_active Expired - Lifetime
-
2004
- 2004-07-12 JP JP2004204861A patent/JP2005057739A/en not_active Ceased
- 2004-12-16 US US11/014,647 patent/US20050104645A1/en not_active Abandoned
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3160766A (en) * | 1962-11-28 | 1964-12-08 | Rca Corp | Switching circuit with a capacitor directly connected between the bases of opposite conductivity transistors |
US3621141A (en) * | 1964-12-17 | 1971-11-16 | Xerox Corp | Dicode decoder |
US3751682A (en) * | 1971-12-17 | 1973-08-07 | Sperry Rand Corp | Pulsed voltage driver for capacitive load |
US4808845A (en) * | 1985-12-02 | 1989-02-28 | Hitachi, Ltd. | High voltage pulse generating semiconductor circuit with improved driving arrangement |
US5677647A (en) * | 1995-10-20 | 1997-10-14 | Tektronix, Inc. | High power pulse waveform generator |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI742257B (en) * | 2018-03-16 | 2021-10-11 | 力智電子股份有限公司 | Pulse-width modulation controller and tri-state voltage generation method |
Also Published As
Publication number | Publication date |
---|---|
US6876241B2 (en) | 2005-04-05 |
JP2005057739A (en) | 2005-03-03 |
US20050024119A1 (en) | 2005-02-03 |
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Legal Events
Date | Code | Title | Description |
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STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |