JP2963192B2 - Level conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a digital circuit which outputs a signal (for example, a CMOS level of 0 V to +5 V) whose logic level is higher than a voltage source VSS (for example, 0 V). The high level of the logic level
The present invention relates to a level conversion circuit for converting a signal lower than VSS (for example, an ECL level of -0.8 V to -1.6 V).

[Conventional technology]

Fig. 14 shows a TTL level (+ 0.4V to + 2.4V) signal
FIG. 15 is a circuit diagram of a conventional example for converting a signal into a signal of a level (-0.8 V to -1.6 V) (JP-A-2-1610, FIG. 2), and FIG. 15 is a block diagram thereof. TTL input buffer powered by high potential voltage source VCC (+ 5V) and first low potential voltage source VSS (0V)
11 and a second low-potential voltage source VEE lower in potential than VSS (−5.
2V) and VCC as power supplies, and VSS and
It comprises a switch circuit 13 powered by VEE and a signal amplitude regulator 14. The buffer 11 has a voltage VSS ≦ V _L <V _H ≦ VCC corresponding to the input high-level voltage V _IH and low-level voltage V _IL.
Is a circuit that generates a high-level voltage _VH and a low-level voltage _VL that satisfy the following conditions. The level shift circuit 12 corresponds to _VH and _{VL.
V H '= V H -ΔV,} V L' = V L -ΔV, (VEE <V L '<V REF <VS
S) to the switch circuit, and the switch circuit 13 is an emitter-coupled current switching circuit.
The signal amplitude regulator 14 is a circuit that amplifies an output signal of the switch circuit 13 to a logical amplitude of ECL and transmits the signal to a driver circuit.

[Problems to be solved by the invention]

In the circuit of the conventional example, there is a problem that the power consumption increases because the switch circuit 13 and the signal amplitude regulator 14 always consume current. Also, since the switch circuit 13 is connected between the signal amplitude regulator 14 and VEE, the level difference from the amplitude center of the output signal of the buffer 11 receiving the TTL input to the amplitude center of the input signal of the switch circuit 13 is large,
The level shift amount of the signal was large. Therefore, there is a problem that not only the number of elements of the level shift circuit 12 is large and the occupied area is large, but also the parasitic capacitance is increased and the propagation delay time is increased by using many diodes.

An object of the present invention is to solve the above problems in the prior art,
It is an object of the present invention to provide a level conversion circuit for converting from a CMOS level to an ECL level which is high speed, consumes little power, and occupies a small area.

[Means for solving the problem]

In order to achieve the above object, in claim 1 of the present invention,
(A) a switch circuit that turns on when the input signal is at a low level and turns off when the input signal is at a high level;
When the input signal is at a high level, it is almost VSS, and when it is at a low level, a signal amplitude regulator that is higher than VSS by a certain voltage is connected in series between the high-potential voltage source VCC and the above voltage source VSS. (C) VCC and potential are VSS
The output terminal of the signal amplitude regulator is connected to the input side of a level shift circuit that is arranged between the lower second low-potential voltage source VEE and shifts the signal level by a constant voltage value. The output of the level shift circuit is input to a driver circuit, and the output is extracted from the driver circuit.

According to a second aspect of the present invention, a bias current limiting circuit including a resistor or a constant current circuit is connected between the VCC and the switch circuit or between the switch circuit and the signal amplitude regulator.

[Action]

Since the current flowing to the signal amplitude regulator is turned on / off via a switch circuit that turns on / off according to the high level and the low level of the input signal, power consumption is reduced. The power consumption is further reduced by limiting the current flowing to the signal amplitude regulator by the bias current limiting circuit. Switch circuit that switches on / off according to input signal and VS
Since the signal amplitude regulator is connected between S and
The level shift amount is small, the level shift circuit can be configured with a small number of elements, the occupied area is small, the parasitic capacitance is small, and the propagation delay time is short.

〔Example〕

FIG. 1 is a diagram showing a first embodiment of a level conversion circuit according to claim 1 of the present invention, and FIG. 2 is a block diagram thereof. This circuit converts a CMOS level signal to an ECL level. The p-channel type MOS FET (abbreviated was less pMOS) source terminal of M ₁ is connected to the high potential voltage source VCC, n-channel type M
(Hereinafter referred to as nMOS) OS FET the source terminal of M ₂ is connected to the first low-potential voltage source VSS, a drain terminal connected P ₂ of M ₂ to the drain terminal of M _1. And P ₁ are connected in common gate terminal of M ₁ and M _2, giving a CMOS level input signal to the terminal P _1. Connect the negative node of the diode D ₁ to VSS, it connects the positive node of D ₁ to P _2. The connect the collector terminal of the npn-type transistors Q ₁ to VCC base terminal connected to the P _2, potential than VSS is connected to a lower second low potential voltage source VEE and emitter terminals P ₃ via a resistor R ₁ . Connect the collector terminal of the npn transistor Q ₂ to VSS, connects the base terminal to P _3. Q
_Second emitter terminal P ₄ is an output terminal of the level conversion circuit. M ₁ constitutes a switch circuit 1, M ₂ and D ₁ constitute a signal amplitude regulator 2, Q ₁ and R ₁ constitute a level shift circuit 3, and Q ₂ constitutes an output driver circuit 4.

The operation of the circuit of this embodiment will be described with reference to FIG. input signal Since There M ₁ when the low-level CMOS turns on M ₂ is turned off, VC
There is a current path from C through M ₁ and D ₁ to VSS. In this case, D ₁ is because it takes a forward voltage of the P ₂ potential It is, VSS a forward voltage of the diodes as V _AC (approximately 0.8 V)
+ V _AC . A forward base-emitter voltage of Q ₁ Then, in general So, the potential of the emitter terminal P ₃ of Q ₁ Becomes Thus, the emitter terminal or the output terminal P ₄ potential Q ₂ ' Is, the forward base-emitter voltage of Q ₂ Then It becomes a high level of ECL. input signal There at high levels of CMOS, M ₁ no current flows from VCC to VSS so off. On the other hand, the base terminal for Q ₁ for M ₂ is turned on, is short-circuited to VSS, the potential becomes equal to VSS (= 0V).
At this time, the potential of the emitter terminal P ₃ of Q ₁ Becomes Therefore, the potential that is, the output voltage of the emitter terminal P ₄ Q ₂ ' And the ECL is at a low level. The level conversion circuit of the present embodiment uses a diode-based clamp circuit to control ECL.
Is obtained. In this circuit, the current flows from VCC to VSS only when outputting a high level, so the ratio of the bias current of the clamp circuit to I ₁ and the time to output the high level to the time to output the low level is σ: 1 −σ (0 ≦ σ ≦
Assuming 1), the power consumption W1 is σ × I ₁ × (VCC−VSS). When the signal amplitude regulator constituting a differential amplifier circuit in place of the clamp circuit, the power consumption when the constant current is I ₀
W ₀ is I ₀ × (VCC−VSS). If I ₁ = I ₀ , W ₁ becomes σ times W ₀ and becomes about 1/2 when the duty ratio is 50% (σ = 0.5).
Is characterized in that the power consumption can be reduced. Further, since the signal amplitude regulator is connected between the switch circuit and the VSS, the level shift amount of the signal is small, and the level shift circuit can be configured with a small number of elements. At the same time, the capacitance associated with the signal path is reduced, which has the effect of reducing the propagation delay time.

FIG. 4 shows a second embodiment of the present invention. This circuit is a circuit obtained by replacing the constant current circuit a resistor R ₁ and the npn transistor Q ₃ by the resistance R ₃ of the level shift circuit At a circuit of FIG. 1. In FIG. ₁ , the forward voltage between the base and the emitter of Q1 is Base voltage When the current flowing through R ₁ Becomes In contrast, the base-emitter forward voltage of Q ₃ are in the circuit of Figure 4 When the base voltage is V _CS , the current flowing through R ₃ Becomes By reducing V _CS , Can be smaller than Therefore, to reduce power consumption R ₃ can be smaller than R ₁ . Q ₂ by reducing R ₃
Since the time constant of the resistance around the base and the parasitic capacitance of the base can be reduced, there is an effect that higher-speed operation is possible.

FIG. 5 is a diagram of a first embodiment according to claim 2 of the present invention, and FIG. 6 is a block diagram thereof. This circuit is
Fourth At a circuit diagram of a circuit connected to the resistor R ₂ between the drain terminals of the P ₂ and M ₁ of M _2. M ₁ constitutes a switch circuit, R ₂ constitutes a bias current limiting circuit,
M ₂ and D ₁ constitute a signal amplitude regulator, Q ₁ , Q ₃ and R ₃ constitute a level shift circuit, and Q ₂ constitutes an output driver circuit.

input signal Since There M ₁ when the low-level CMOS turns on M ₂ is turned off, VC
There is a current path from C through M ₁ , R ₂ , D ₁ to VSS. M ₁
The on-resistance of When the forward voltage of V is V _AC , the current flowing through D ₁ Becomes Current when R ₂ is not connected Has the effect of reducing power consumption compared to the circuit of FIG.

FIG. 7 is a diagram showing a second embodiment according to claim 2 of the present invention, and FIG. 8 is a block diagram thereof. This circuit is
PMOS between the source terminal VCC and M ₁ At a circuit of FIG. 4,
A current mirror type constant current circuit constituted by M ₃ and M ₄ and a constant current source I _CSO is connected. The current mirror type constant current circuit, as well as in R ₂ in FIG. 5, there is an effect of reducing power consumption by limiting the bias current. M ₁
Constitutes a switch circuit, M ₂ and D ₁ constitute a signal amplitude regulator, Q ₁ , Q ₃ and R ₃ constitute a level shift circuit, and Q ₂
Constitutes an output driver circuit. input signal Since There M ₁ when the low-level CMOS turns on M ₂ is turned off, VC
A current path is formed from C to VSS through M ₃ , M ₁ , and D _1, and the potential at the positive node of D ₁ is about 0.8 V. input signal There Since M ₁ is turned off when a high level of CMOS level, VSS no current flows from VCC, M ₂ is a positive node is shorted to the VSS potential of turns D ₁ becomes 0V. In this way, the potential of the base terminal for Q ₁ connected to the positive node of D ₁ is determined. In the circuit of FIG. 5, but to reduce the power consumption by connecting the R _2, which hinders high-speed operation for the time constant increases in the base of the parasitic capacitance and R ₂ in Q _1. In the circuit of FIG.
Resistance around the base for Q ₁ while limiting the current, M ₃ and
An on resistance or on-resistance of the M ₂ of M _1, which can reduce the time constant around the base for Q ₁ is smaller as compared with R _2,
There is an effect that it is possible to achieve both low power and high speed.

FIG. 9 shows a third embodiment according to claim 2 of the present invention. This circuit, instead of the clamping diode D ₁ At a circuit of FIG. 7 and a fourth npn-type transistor Q ₄ fourth and fifth resistors resistor R _4, a constant-voltage circuit according to R ₅ P ₂ and VSS It is connected between. The base-emitter forward voltage of Q ₄ Then the input signal There M ₁ when the low-level CMOS can _{M 3, M 1, R 4} , R 5 and a current path leading to VSS through Q ₄ from turned VCC. Potential of base terminal P ₅ of Q ₄ So, the current flowing through R ₅ And the potential of the collector terminal P ₂ of Q ₄ become. input signal There Since M ₁ is turned off when the high level of CMOS, VSS no current flows from VCC, the potential collector terminal P ₂ of M ₂ is turned on Q ₄ are shorted to VSS becomes 0V. In this way, Sadamari potential of the base terminal for Q ₁ connected to the collector terminal of Q _5, the voltage amplitude thereof The amplitude equal to is level-shifted and appears at the output terminal.
That is, the circuit of FIG. 9 has an effect that the output amplitude can be set to an arbitrary value equal to or higher than the base emitter forward voltage by changing the ratio of R ₄ / R ₅ .

FIG. 10 shows a fourth embodiment according to claim 2 of the present invention. The circuit, p parallel to the Q _3, R ₃ in the circuit of Figure 5
This circuit connects an active load consisting of a MOS and a resistor to achieve high-speed output pull-down. Connect the source terminal of pMOSM ₆ to Q ₂
Connected to the base terminal P _3, via a resistor R ₆ to the drain terminal of M ₆ is connected to VEE. Connect the collector terminal of the npn transistor Q ₅ to the high potential voltage source VCC, the emitter terminal of Q ₅ through the level shift is connected to a gate terminal P ₆ of M _6. Q ₅
The base terminal of is connected to a resistor R ₁ and the connection point P ₅ and R ₁ '.

The operation of the circuit in FIG. 10 will be described with reference to FIG. Input terminal P ₁ When a signal such as is input, the respective voltage waveforms of P ₂ , P ₃ , and P ₄ are the same as in the circuit of FIG. become that way. Now, the ratio of _{R 1, R 1 '1-} δ: When [delta], the potential of the P ₅ is Will be represented by That is, when the low level of the CMOS is applied to P _1, M ₁ is turned on, M ₂ is turned off, Becomes If the threshold voltage of M ₆ is V _th6 , If M ₆ is turned off, the path of the current flowing to VEE through a collector terminal for Q ₁ from the VCC is only R _1. Therefore, it is possible to reduce the current flowing by increasing the R _1, power consumption can be reduced. When the P ₁ higher levels of CMOS is applied, M ₁ is turned off, since M ₂ is turned on And the output voltage is the same as in the circuit of FIG. Goes low on ECL. Since R ₁ : R ₁ ′ = 1−δ: δ, Next, the amount of change in potential of the P ₆ Is Becomes The potential of the terminal P ₆ of the level shift circuit The waveform of Is level-shifted.

Δ can be determined so that M ₆ is turned on when the meet. When the M ₆ is turned on, VE from P ₃
Path of the current flowing in the E becomes parallel R ₆ and R _3, a pull-down output for the impedance around the base terminal Q ₂ 'is reduced there is an effect to be performed at high speed.

FIG. 12 is a first embodiment according to claim 3 of the present invention. This circuit is an amplifier circuit according to a resistor R ₄₀ in place of the clamping diode D ₁ At a circuit of Figure 7 is connected between the P ₂ and VSS. input signal VS but M ₁ when the low-level CMOS from turns VCC through R ₄₀
A current path to S is created. Current through R ₄₀ Is approximately equal to the current I _CS determined by the current limit circuit, and Q
₁ Collector terminal P ₂ potential become. input signal There Since M ₁ is turned off when the high level of CMOS, VSS no current flows from VCC, M ₂ is the collector terminal P ₂ is short-circuited to the VSS potential of turns Q ₁ is becomes 0V. In this way, Sadamari the potential of the base terminal of Q ₂ to which is connected to the collector terminal of Q _3, appears at the output terminal an amplitude equal to its voltage amplitude R ₄₀ × I _CS is level shifted. That is, in the circuit of FIG. 12, R ₄₀ and I _CS
By adjusting one or both of the above, the output amplitude can be set to an arbitrary value equal to or less than the power supply voltage (VCC-VSS).

FIG. 13 shows a second embodiment according to claim 3 of the present invention. This circuit is a resistor R ₄₀ in place of the clamping diode D ₁ At a circuit of Figure 5 is connected between the P ₂ and VSS. input signal There M ₁ when the low-level CMOS can M _1, R _2, a current path leading to via R ₄₀ VSS from turns VCC. M ₁ ON resistance Then the current flowing through R ₄₀ And the potential of the collector terminal P ₂ of Q ₁ Becomes input signal There Since M ₁ is turned off when the high level of CMOS, VSS no current flows from VCC, M ₂ is the collector terminal P ₂ is short-circuited to the VSS potential of turns Q ₁ is becomes 0V. In this way, Sadamari the potential of the base terminal of Q ₂ to which is connected to the collector terminal of Q _3, the voltage amplitude thereof The amplitude equal to is level-shifted and appears at the output terminal.
That is, in the circuit of FIG. By changing the ratio, the output amplitude can be set to an arbitrary value smaller than VCC.

〔The invention's effect〕

According to the present invention, the following effects can be exerted.

(1) Since the current flowing through the signal amplitude regulator is turned on / off by the switch circuit, power consumption is small.

(2) Since the current flowing through the signal amplitude regulator is limited by the bias current limiting circuit, power consumption is small.

(3) The occupied area is small because the signal amplitude regulator for generating the ECL output amplitude is constituted by a diode clamp circuit.

(4) The occupied area is small because the signal amplitude regulator that generates the ECL output amplitude is composed of an amplifier circuit using resistors.
In addition, a necessary and sufficient output amplitude can be secured by making the current flowing through the signal amplitude regulator constant by the bias current limiting circuit.

(5) Since the signal amplitude regulator for generating the ECL output amplitude is constituted by a constant voltage circuit using bipolar transistors and resistors, a necessary and sufficient output amplitude can be secured.

(6) Since the signal amplitude regulator is connected between the switch circuit and the VSS, the level shift amount is small, and the level shift circuit can be configured with a small number of elements. Therefore, the occupied area is small, the parasitic capacitance is small, and the propagation delay is small. This has the effect of reducing time.

(7) By connecting an active load in parallel with the load resistance of the level shift circuit, high-speed output pull-down becomes possible.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a block diagram thereof, FIG.
FIG. 4 is a circuit diagram of a second embodiment of claim 1, FIG. 5 is a circuit diagram of a first embodiment of the present invention, FIG. 6 is a block diagram thereof, and FIG. FIG. 8 is a block diagram thereof, FIG. 9 is a circuit diagram of a third embodiment of claim 2, FIG. 10 is a circuit diagram of a fourth embodiment of claim 2, FIG. FIGS. 12 and 13 are circuit diagrams of the first and second embodiments of the present invention, FIG. 14 is a circuit diagram of a conventional example, and FIG. 15 is a block diagram thereof. It is. [Explanation of Symbols] 1,13 Switch circuit 2,14 Signal amplitude regulator 3,12 Level shift circuit 4 Output driver circuit 5 Bias current limiting circuit 11 Buffer receiving TTL input

Claims (3)

(57) [Claims] 1. A binary logic signal having a low-level potential higher than a first low-potential voltage source VSS at its input and a high-level potential lower than the voltage source VSS. A level conversion circuit for converting the input signal into a digital signal having the following.
(B) A signal amplitude regulator in which the voltage at both ends becomes almost VSS when the input signal is at a high level and becomes higher by a certain voltage than VSS when the input signal is at a low level, in series,
Connected between the high potential voltage source VCC and the voltage source VSS,
(C) an input side of a level shift circuit that is arranged between the voltage source VCC and a second low-potential voltage source VEE whose potential is lower than the voltage source VSS and shifts the level of a signal by a constant voltage value; An output terminal of the signal amplitude regulator, and (d) an output of the level shift circuit is input to a driver circuit, and an output is taken out from the driver circuit. 2. A bias current limiting circuit comprising a resistor or a constant current circuit is connected between the high potential voltage source VCC according to claim 1 and a switch circuit or between the switch circuit and a signal amplitude regulator. A level conversion circuit characterized in that: 3. A level conversion circuit, wherein the signal amplitude regulator according to claim 2 is replaced by a resistor.