JPS62157419A - Level converting circuit - Google Patents

Abstract

PURPOSE:To attain circuit integration and high speed operation by operating a switching element impresses a high voltage in response to the operation of an additional switching element operated at a low voltage level of the logic circuit operation being the result of differentiation of an on/off input signal via an RC differentiation circuit. CONSTITUTION:A resistor 42 and a capacitor 41 of a level conversion circuit 4 differentiate an input signal S2. When a gate voltage of a transistor (TR) 43 exceeds its threshold value, the TR 43 is turned on. A high voltage VH to be level-converted is divided by resistors 44, 45 and a bias voltage is fed to a TR 46. A bias voltage is changed by the on/off operation of the TR 43 and when the gate voltage of the TR 46 is lowered than its threshold voltage, the TR 46 is turned on. When the TR 26 of push-pull connection is turned on and a TR 3 is turned off, an output Sout reaches a high voltage VH and other levels are zero V. Since no high voltage VH is impressed to a capacitor 41, no high dielectric strength is required and then circuit integration is facilitated. Since the TR 46 is operated by the TR 43, high speed operation is attained.

Description

[Detailed Description of the Invention] [Summary] Accepts low voltage level on/off input signals and performs on/off input signals.
In a level conversion circuit that obtains a high voltage level output that changes on and off in response to an off input signal, a switching element to which a high voltage is applied is differentiated by an on and off input signal via an RCi dividing circuit. This level conversion circuit operates in response to the switching operation of an additional switching element that operates at a low voltage level for logic circuit operation.

[Industrial application field]

The present invention relates to a level conversion circuit that outputs a high voltage level signal in response to an on/off change of a low voltage level on/off input signal.

The level conversion circuit of the present invention is suitable for devices that receive low voltage level input signals and supply high voltage drive voltages, such as electrode drive circuits in plasma displays (FDP) and electroluminescent (EL) display devices. used.

[Conventional technology]

For example, in an FDP display device, when receiving display output data from a host computer etc. and performing a display according to the display output data, the signal level of the logic circuit operation output from the host computer, for example, 5■ is displayed. output data for high voltage to drive the POP electrodes,
For example, a level conversion circuit for converting to 100 to 200V is required.

FIG. 4 shows a pulse amplification circuit combined with a conventional level conversion circuit 4a. The level conversion circuit 4a includes a time constant circuit including a capacitor 41a and a resistor 44a connected in series, a resistor 45, and a p-channel MOS transistor 46.
a are connected as shown in the figure. FIG. 4 shows an amplifier l receiving an input signal SIN, and the p-channel MOs
It includes an n-channel MO3) transistor 3 connected in a push-pull manner to a transistor 46a, and constitutes a pulse amplification circuit.

The operation timing of the circuit of FIG. 4 is shown in FIGS. 5(a) to (fl).

Depending on whether the input signal SIN is turned on or off (Fig. 5(a))
, the same voltage is applied to the gate of transistor 3 (fifth
Figure (bl, gate signal 33G” of transistor 3),
Transistor (Qd) 3 turns on and off (Fig. 5 (
C)). On the other hand, the rising and falling edges of the input signal SIN are differentiated by a time constant circuit consisting of a resistor 44a and a capacitor 41a, and the gate voltage 546aa of the transistor 46 becomes as shown in FIG.
When G is less than the threshold value V, the transistor (Qu)
46a turns on (Fig. 5 (el)), the source of the transistor 46a is connected to a high voltage ■H1, for example 100V, and the output signal S at the point where the transistors 46a and 3 are connected in push-pull.U□ is When the transistor 46a is on and the transistor 3 is off, the level is high, and in the opposite case, the level is zero (FIG. 5(f)).In this way, the output signal is at a high level in response to the input signal SIN at a low voltage level. 5OIf can be extracted.

FIG. 6 shows a level converter circuit 44b similar to the above, which includes a reverse blocking circuit 5, a Darlington circuit 6, a Zener diode 7,
An example is shown in which the circuit is connected to an amplifier circuit connected by diodes 8 to 1o.

[Problem that the invention seeks to solve]

4 and 6, a transistor 46a to which a high voltage vH is applied is connected to a capacitor 41a1 and a resistor 44a.
It is directly driven by a time constant circuit. That is, the source of the transistor 3 is grounded and can be directly controlled by the input signal SIN, but since the high voltage vH is applied to the source of the transistor 46a, it cannot be easily controlled. While cutting off the high voltage component with the capacitor and applying a bias voltage to the gate of the transistor 46a through the resistance division of the resistors 44a and 45a, the differential signal of the time constant circuit is applied to the transistor 46a.
A negative bias is applied to the gate voltage seen from the source of transistor 46a to turn on transistor 46a.

According to this circuit configuration, the capacitor 41a is required to have a high withstand voltage. If the capacitor is made to withstand high voltage, it becomes expensive.

Further, it is difficult to implement the level conversion circuit into an IC, and it is difficult to realize the desire to implement the level conversion circuit into an IC.

Furthermore, since the charging/discharging circuit of the capacitor 41a and the resistor 44a and 745a is used to supply the bias voltage of the transistor 46a, in order to extend the duration of the bias voltage, increase these values and set the time constant. needs to be made larger. However, as mentioned above, the capacitor 41a is required to have a high withstand voltage, and cannot have a large capacity in an IC circuit.
It is possible to make a and 45a a large resistance value, but
For example, if the resistance value of the resistor 45a is increased, the on-time of the transistor 46a becomes excessively long, and when high-speed operation is required, a problem arises in that the response is insufficient.

[Means for Solving the Problems] In view of the above problems, the present invention provides a level conversion circuit that can be integrated into an IC without requiring a capacitor to have high voltage resistance, and can operate at high speed. With the goal.

The above object of the present invention is to provide a time constant circuit comprising a capacitor and a resistor that receives an input signal that turns on and off at the signal level of logic circuit operation, and a time constant circuit that turns on and off the input signal applied to the time constant circuit. a first switching element that operates at a signal level for logic circuit operation in response to a change in one of the switching elements; 2
This is realized by a level conversion circuit including a switching element.

〔Example〕

FIG. 1 shows a circuit diagram of a level conversion circuit and a pulse amplification circuit as an embodiment of the present invention.

In FIG. 1, the level conversion circuit 4 includes a capacitor 41
．． Resistor 42, n-channel MOS transistor (Qa)
43, resistors 44 and 45, and a p-channel MOS transistor (Qu) 46 are connected as shown.

Also, in FIG. 1, amplifier l, inverter 2 and n
Channel MO3) transistor (Qd) 3 is connected as shown.

The amplifier l has a signal level for logic circuit operation, e.g. 1SV
The input signal 5IN(
The signal level shown in FIG. 2(a) is accepted and the signal level of the in-phase and predetermined logic circuit operation is set, in this embodiment, the TTL level. amplify the signal. The inverter 2 inverts the amplified input signal SIN'' and applies it to the level conversion circuit 4 as an inverted input signal S2 (FIG. 2(d)). The amplified TTL level input signal St,' (Fig. 2 (bl) is applied to the gate and directly turns on and off (Fig. 2 (C)). In other words, the source (S ) is grounded,
Even if the voltage difference between the source and the gate (G) is at the TTL level, the transistor 3 operates stably.

In the level conversion circuit 4, a time constant circuit is configured with a resistor 42 and a capacitor 41, and the amplified and inverted input signal S2 is differentiated, and this differentiated signal and the bias voltage between the source and gate of the transistor 43 are The voltage 543c applied to the gate of the transistor 43 is the sum of
(Fig. 2 (e)) exceeds the threshold value vT of the transistor 43, the transistor 43 turns on (Fig. 2 [fl), ) The source (S) of the transistor 46 has a high voltage to be converted in level. A voltage vH1, for example, 100 VDC is applied, and due to the resistive voltage division of resistors 44 and 45,
A bias voltage is applied between the gate and source of the transistor 46. Due to the above-mentioned on/off operation of the transistor 43, the bias voltage changes, and the transistor 4
When the voltage S 46c applied to the gate of the transistor 6 falls below the threshold value of the transistor 46 (FIG. 2 (phantom)), the transistor 46 turns on (FIG. 2 (h)).

When the push-pull connected transistor 46 is on and the transistor 3 is off, the output 5O1jT taken out between both transistors becomes a high voltage vH, and the others are O
It is v. This output 5OIIT is in phase with the input signal SIN. As a result, the level of the input signal SIN of the logic circuit operation signal level is converted to the high voltage output 5oul.

In the level conversion circuit 4 shown in FIG. 1, the capacitor 41 constituting the time constant circuit does not directly drive the transistor 46 (it drives the transistor 46 by the switching operation of the transistor 43 via the transistor 43). , unlike the conventional case, high voltage vH is not applied. Therefore, the capacitor 41 does not require a high withstand voltage, and a low withstand voltage for the signal level of the logic circuit operation is sufficient.The same applies to the resistor 42. Therefore, the capacitor 41 is constructed using a depletion layer and the IC
This makes it easy to increase the capacity and increase the capacity.

Further, the transistor 3 is operable in response to the operation of the input signal SIN, and the transistor 46 is operable in response to the operation of the input signal SIN.
Since it operates with a switching operation of 1, high-speed operation is possible.

FIG. 3 shows a pulse amplification circuit in which the circuit of FIG. 1 is applied to the circuit corresponding to FIG. 6.

The level conversion circuit 4'' in FIG. 3 is different from the level conversion circuit 4 in FIG. 1 by adding a resistor 47 in parallel with a transistor 46. In addition, push-pull connected transistor 4
A reverse blocking circuit 5 consisting of a resistor 51 and a diode 52 connected in series is provided between the two. The reverse blocking circuit 5 is provided so that the level-converted signal output can be used even in a floating state.

The high voltage VH2 applied to the transistor 46 of the level conversion circuit 4° and the high voltage V) I applied to the Darlington-connected transistors 61 and 62 in the pulse amplification circuit.
t, there is a constant voltage difference ΔV, for example VH2=1
20V, V)! 1=100V1. ', AV=20V
has been established. This is to maintain the bias voltage between the source and gate of the transistor 61 when the transistor 62 is turned on and the transistor 46 is turned on. Level-converted high voltage VHI output signal S.

l, , are output.

〔Effect of the invention〕

As described above, according to the present invention, a level conversion circuit suitable for IC implementation can be obtained.

Further, according to the present invention, a level conversion circuit capable of high-speed operation is obtained.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a level conversion circuit and a pulse amplification circuit according to an embodiment of the present invention, FIG. 2 (al to (1) is an operation timing diagram of the circuit in FIG. A circuit diagram of an example level conversion circuit and a pulse amplification circuit, FIG. 4 is a conventional circuit diagram corresponding to FIG. 1, and FIG. 5(a)
~(fl is an operation timing diagram of the circuit in FIG. 4, and FIG. 6 is a conventional circuit diagram corresponding to FIG. 3. (Explanation of symbols) 1... Amplifier, 2... TTL inverter, 3 ... output transistor, 4 ... level conversion circuit, 41 ... capacitor, 42 ... resistor, 43 ... first transistor, 44, 45 ... resistor, 46 ... th 2 transistor, 47...resistor, 5...reverse blocking circuit, 6...darlington circuit, 7...-Zener diode, 8-10...diode.

Claims (1)

[Claims] 1. A time constant circuit consisting of a capacitor and a resistor that receives an input signal that turns on and off at the signal level of logic circuit operation, and whether the input signal applied to the time constant circuit is turned on or off. a first switching element that operates at a signal level for logic circuit operation in response to a change in one of the switching elements; and a first switching element to which a high voltage is applied and operates in response to the operation of the first switching element to output the high voltage A level conversion circuit comprising: a second switching element.