US20050042820A1 - Method for fabricating a metal-insulator-metal capacitor in a semiconductor device - Google Patents
Method for fabricating a metal-insulator-metal capacitor in a semiconductor device Download PDFInfo
- Publication number
- US20050042820A1 US20050042820A1 US10/758,150 US75815004A US2005042820A1 US 20050042820 A1 US20050042820 A1 US 20050042820A1 US 75815004 A US75815004 A US 75815004A US 2005042820 A1 US2005042820 A1 US 2005042820A1
- Authority
- US
- United States
- Prior art keywords
- layer
- metal
- metal layer
- mim capacitor
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
Definitions
- the present disclosure relates generally to semiconductor devices and, more particularly, to a method of fabricating a metal-insulator-metal capacitor in a semiconductor device.
- a capacitor In fabricating highly-integrated memory devices, a capacitor has to provide a relatively high capacitance in a small area.
- capacitance can be increased by forming a capacitor using a dielectric layer with a large dielectric constant, forming a thin dielectric layer, and/or increasing a cross-sectional area of a capacitor.
- Dielectric materials including SiO 2 /Si 3 N 4 are used as commonly used as a dielectric layer of a capacitor.
- a polysilicon-insulator-polysilicon (PIP) capacitor structure or a metal-insulator-metal (MIM) capacitor structure may be employed.
- Thin film capacitors such as PIP capacitors and MIM capacitors are used in analog semiconductor devices requiring precise capacitance values because, in contrast to MOS capacitors and junction capacitors, these capacitors are independent of bias.
- the MIM capacitor has a disadvantage because it has smaller capacitance per unit area than that of the PIP capacitor, the former has better VCC (voltage coefficient for capacitance) and TCC (temperature coefficient for capacitance) according to voltage and temperature as compared to the PIP capacitor.
- FIGS. 1 a through 1 f illustrate, in cross-sectional views, the process steps of a known capacitor-fabricating method.
- a dielectric layer 3 is deposited on a lower metal layer 2 and a substrate 1 with at least a predetermined structure, and an upper metal layer 4 is deposited on the dielectric layer.
- a MIM capacitor 5 is formed by etching simultaneously the dielectric layer and the upper metal layer using a mask (not shown).
- an interlayer dielectric 6 is formed on all of the area of the substrate with the MIM capacitor. Referring to FIG.
- the interlayer dielectric is etched to form a via hole that connects the upper metal layer and the lower metal layer, respectively, with an uppermost metal layer, and a barrier metal layer 7 is deposited on the via hole.
- the via hole is filled with a metal plug 8 and flattened to complete the contact via hole.
- a metal layer is deposited on the metal plug 8 and patterned to form an uppermost metal layer 9 , thereby completing a MIM capacitor.
- Korean Patent Publication No. 10-2003-0058317 discloses a MIM capacitor fabricating method that forms an etch stopping layer to prevent the interlayer dielectric from being attacked by etching solution and eliminating an oxide supporting a lower electrode.
- Another Korean Patent Publication No. 10-2002-0073822 discloses a method of fabricating a MIM capacitor that provides good step coverage and a uniform dielectric layer and forms spacers on lateral walls of a lower electrode.
- FIGS. 1 a through 1 f illustrate, in cross-sectional views, known the processing steps.
- FIGS. 2 a through 2 f illustrate, in cross-sectional views, an example method for fabricating an MIM capacitor.
- the example method described below in connection with FIGS. 2 a through 2 f uses a sacrificial layer of silicon oxide to protect the lower metal layer despite over-etching.
- An example method for fabricating an MIM capacitor of semiconductor device deposits a metal layer to be used as a lower electrode of the MIM capacitor, deposits a sacrificial layer on the metal layer, removes some area of the sacrificial layer to form an MIM capacitor thereon, deposits a dielectric layer and an upper metal layer, and forms an MIM capacitor by patterning the dielectric layer and the upper metal layer.
- a metal layer to be used as a lower electrode of an MIM capacitor is deposited on a substrate 10 with a predetermined structure.
- the metal layer is patterned to form a lower metal layer 11 .
- a sacrificial layer 12 is deposited by chemical vapor deposition.
- the sacrificial layer is used as an etch stopping layer in etching an interlayer dielectric.
- the sacrificial layer is silicon oxide or silicon nitride and has a thickness of 100-200 ⁇ .
- the sacrificial layer is patterned using a photoresist process, and some area on which an MIM capacitor is formed is removed by dry-etch or wet-etch. Then, an upper metal layer 14 and a dielectric layer 15 are deposited in sequence.
- the dielectric layer is formed by chemical vapor deposition or atomic layer deposition using a material such as SiN, SiO 2 , Al 2 O 3 , TaON, TiO 2 , Ta 2 O 5 , ZrO 2 , (Ba,Sr)TiO 3 (hereinafter referred to as “BST”), (Pb,Zr)TiO 3 (hereinafter referred to as “PZT”), or (Pb,La)(Zr,Ti)O 3 (hereinafter referred to as “PLZT”).
- BST SiN, SiO 2 , Al 2 O 3 , TaON, TiO 2 , Ta 2 O 5 , ZrO 2 , (Ba,Sr)TiO 3
- BST Ba,Sr)TiO 3
- PZT Pb,ZrT
- Pb,La Pb,La)(Zr,Ti)O 3
- an MIM capacitor 16 is formed through patterning and etching the dielectric layer and the lower metal layer and, then, an interlayer dielectric 17 is deposited.
- the interlayer dielectric may be silicon oxide complex, and is used as an etch stopping layer in etching the dielectric layer and the lower metal layer.
- a via hole 18 is formed.
- the sacrificial layer on the lower metal layer is etched during the formation of the via hole.
- the via hole of which a barrier metal layer 19 is deposited on the bottom and the lateral walls is filled with a metal plug 20 and flattened to form a contact via hole.
- the metal plug is made from a metal selected from the group of tungsten, copper family elements, and platinum family metals.
- the barrier metal layer is made of a high fusion point metal or nitride thereof, for example, TaN, Ta/TaN, TiN, or Ti/TiN, and is a single layer or multi-layer.
- the high fusion point metal means a metal having a higher fusion point than that of iron (Fe), 1,535° C.
- a metal layer is deposited and patterned to form an uppermost metal layer 21 and, finally, the contact is completed.
- the metal layers of the MIM capacitor are made of aluminum, a transition element, or an alloy consisting of aluminum and a transition element.
- the above-described example method for fabricating an MIM capacitor can prevent increase in leakage current due to redeposition because a sacrificial layer is used to protect a lower metal layer in spite of over-etching.
Abstract
Description
- The present disclosure relates generally to semiconductor devices and, more particularly, to a method of fabricating a metal-insulator-metal capacitor in a semiconductor device.
- In fabricating highly-integrated memory devices, a capacitor has to provide a relatively high capacitance in a small area. Conventionally, capacitance can be increased by forming a capacitor using a dielectric layer with a large dielectric constant, forming a thin dielectric layer, and/or increasing a cross-sectional area of a capacitor.
- Known multi-layered capacitors or trench-type capacitors have been used to increase a cross-sectional area of a capacitor. A half-spherical polysilicon layer has also been used to that end. However, these known technologies tend to complicate a capacitor structure, reduce process yield, and increase manufacturing cost.
- Dielectric materials including SiO2/Si3N4 are used as commonly used as a dielectric layer of a capacitor. Based on the material used for a capacitor electrode, a polysilicon-insulator-polysilicon (PIP) capacitor structure or a metal-insulator-metal (MIM) capacitor structure may be employed. Thin film capacitors such as PIP capacitors and MIM capacitors are used in analog semiconductor devices requiring precise capacitance values because, in contrast to MOS capacitors and junction capacitors, these capacitors are independent of bias.
- In addition, although the MIM capacitor has a disadvantage because it has smaller capacitance per unit area than that of the PIP capacitor, the former has better VCC (voltage coefficient for capacitance) and TCC (temperature coefficient for capacitance) according to voltage and temperature as compared to the PIP capacitor.
-
FIGS. 1 a through 1 f illustrate, in cross-sectional views, the process steps of a known capacitor-fabricating method. Referring toFIG. 1 a, adielectric layer 3 is deposited on alower metal layer 2 and asubstrate 1 with at least a predetermined structure, and anupper metal layer 4 is deposited on the dielectric layer. Referring toFIG. 1 b, aMIM capacitor 5 is formed by etching simultaneously the dielectric layer and the upper metal layer using a mask (not shown). Referring toFIG. 1 c, an interlayer dielectric 6 is formed on all of the area of the substrate with the MIM capacitor. Referring toFIG. 1 d, the interlayer dielectric is etched to form a via hole that connects the upper metal layer and the lower metal layer, respectively, with an uppermost metal layer, and abarrier metal layer 7 is deposited on the via hole. Referring toFIG. 1 e, the via hole is filled with ametal plug 8 and flattened to complete the contact via hole. Referring toFIG. 1 f, a metal layer is deposited on themetal plug 8 and patterned to form anuppermost metal layer 9, thereby completing a MIM capacitor. - Korean Patent Publication No. 10-2003-0058317 discloses a MIM capacitor fabricating method that forms an etch stopping layer to prevent the interlayer dielectric from being attacked by etching solution and eliminating an oxide supporting a lower electrode. Another Korean Patent Publication No. 10-2002-0073822 discloses a method of fabricating a MIM capacitor that provides good step coverage and a uniform dielectric layer and forms spacers on lateral walls of a lower electrode.
- However, in these conventional methods the process of forming an MIM capacitor by etching simultaneously an upper metal layer and a dielectric layer, causes a fringing effect at the edge of the MIM capacitor, and is accompanied by bridge, which increases leakage current. The bridge is generated by redeposition of metal etched from the lower metal layer during over-etching necessary for etching a dielectric layer of MIM capacitor. To obviate these problems, the formation of spacers on a lower electrode has been proposed, but such spacers do not completely prevent the bridge due to the difficulty in controlling the process and, in some cases, may significantly complicate processing.
-
FIGS. 1 a through 1 f illustrate, in cross-sectional views, known the processing steps. -
FIGS. 2 a through 2 f illustrate, in cross-sectional views, an example method for fabricating an MIM capacitor. - As described above, known methods of fabricating an MIM capacitor etch an upper metal layer and a dielectric layer simultaneously using an etch stopping layer formed on a lower metal layer. In addition, these known methods use over-etching to remove the remaining dielectric layer on the lower metal layer. The metal generated by etching of the lower metal layer is redeposited to induce a bridge between the upper and the lower metal layers, which leads to an increase in the leakage current.
- In contrast, the example method described below in connection with
FIGS. 2 a through 2 f, uses a sacrificial layer of silicon oxide to protect the lower metal layer despite over-etching. - An example method for fabricating an MIM capacitor of semiconductor device deposits a metal layer to be used as a lower electrode of the MIM capacitor, deposits a sacrificial layer on the metal layer, removes some area of the sacrificial layer to form an MIM capacitor thereon, deposits a dielectric layer and an upper metal layer, and forms an MIM capacitor by patterning the dielectric layer and the upper metal layer.
- Referring to
FIG. 2 a, a metal layer to be used as a lower electrode of an MIM capacitor is deposited on asubstrate 10 with a predetermined structure. The metal layer is patterned to form alower metal layer 11. Then, asacrificial layer 12 is deposited by chemical vapor deposition. The sacrificial layer is used as an etch stopping layer in etching an interlayer dielectric. The sacrificial layer is silicon oxide or silicon nitride and has a thickness of 100-200 Å. - Referring to
FIG. 2 b, the sacrificial layer is patterned using a photoresist process, and some area on which an MIM capacitor is formed is removed by dry-etch or wet-etch. Then, anupper metal layer 14 and adielectric layer 15 are deposited in sequence. The dielectric layer is formed by chemical vapor deposition or atomic layer deposition using a material such as SiN, SiO2, Al2O3, TaON, TiO2, Ta2O5, ZrO2, (Ba,Sr)TiO3 (hereinafter referred to as “BST”), (Pb,Zr)TiO3 (hereinafter referred to as “PZT”), or (Pb,La)(Zr,Ti)O3 (hereinafter referred to as “PLZT”). The dielectric layer is a single layer or multi-layer with a thickness of 200-1000 Å. - Referring to
FIG. 2 c, anMIM capacitor 16 is formed through patterning and etching the dielectric layer and the lower metal layer and, then, an interlayer dielectric 17 is deposited. The interlayer dielectric may be silicon oxide complex, and is used as an etch stopping layer in etching the dielectric layer and the lower metal layer. - Referring to
FIG. 2 d, avia hole 18 is formed. The sacrificial layer on the lower metal layer is etched during the formation of the via hole. Then, as shown inFIG. 2 e, the via hole of which abarrier metal layer 19 is deposited on the bottom and the lateral walls is filled with ametal plug 20 and flattened to form a contact via hole. The metal plug is made from a metal selected from the group of tungsten, copper family elements, and platinum family metals. The barrier metal layer is made of a high fusion point metal or nitride thereof, for example, TaN, Ta/TaN, TiN, or Ti/TiN, and is a single layer or multi-layer. The high fusion point metal means a metal having a higher fusion point than that of iron (Fe), 1,535° C. - Referring to
FIG. 2 f, a metal layer is deposited and patterned to form anuppermost metal layer 21 and, finally, the contact is completed. - In the above-mentioned processes, the metal layers of the MIM capacitor are made of aluminum, a transition element, or an alloy consisting of aluminum and a transition element.
- The above-described example method for fabricating an MIM capacitor can prevent increase in leakage current due to redeposition because a sacrificial layer is used to protect a lower metal layer in spite of over-etching.
- Although certain methods and apparatus have been described herein, the scope of coverage of this patent is not limited thereto. To the contrary, this patent covers all embodiments fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.
Claims (10)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-00056827 | 2003-08-18 | ||
KR1020030056827A KR100556535B1 (en) | 2003-08-18 | 2003-08-18 | Method for manufacturing capacitor of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
US20050042820A1 true US20050042820A1 (en) | 2005-02-24 |
US7067921B2 US7067921B2 (en) | 2006-06-27 |
Family
ID=34192102
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/758,150 Expired - Fee Related US7067921B2 (en) | 2003-08-18 | 2004-01-15 | Method for fabricating a metal-insulator-metal capacitor in a semiconductor device |
Country Status (2)
Country | Link |
---|---|
US (1) | US7067921B2 (en) |
KR (1) | KR100556535B1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080048225A1 (en) * | 2006-08-25 | 2008-02-28 | Micron Technology, Inc. | Atomic layer deposited barium strontium titanium oxide films |
US20130106875A1 (en) * | 2011-11-02 | 2013-05-02 | Qualcomm Mems Technologies, Inc. | Method of improving thin-film encapsulation for an electromechanical systems assembly |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100774816B1 (en) * | 2006-11-21 | 2007-11-07 | 동부일렉트로닉스 주식회사 | Metal-insulator-metal capacitor forming method for semiconductor device and structure thereof |
US8310807B2 (en) * | 2009-06-12 | 2012-11-13 | Micron Technology, Inc. | Capacitors having dielectric regions that include multiple metal oxide-comprising materials |
US8236372B2 (en) | 2009-06-12 | 2012-08-07 | Micron Technology, Inc. | Methods of forming capacitors having dielectric regions that include multiple metal oxide-comprising materials |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5351163A (en) * | 1992-12-30 | 1994-09-27 | Westinghouse Electric Corporation | High Q monolithic MIM capacitor |
US6387750B1 (en) * | 2001-07-02 | 2002-05-14 | Macronix International Co., Ltd. | Method of forming MIM capacitor |
US20040137693A1 (en) * | 2002-07-25 | 2004-07-15 | Dongbu Electronics Co., Ltd. | Method for forming an MIM capacitor |
US20040152256A1 (en) * | 2003-01-08 | 2004-08-05 | Renesas Technology Corp. | Semiconductor device manufacturing method |
US6784069B1 (en) * | 2003-08-29 | 2004-08-31 | Micron Technology, Inc. | Permeable capacitor electrode |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR19980034728A (en) | 1996-11-08 | 1998-08-05 | 김영환 | Speed Control Method of Semiconductor Memory Device |
US5972722A (en) * | 1998-04-14 | 1999-10-26 | Texas Instruments Incorporated | Adhesion promoting sacrificial etch stop layer in advanced capacitor structures |
KR100312755B1 (en) | 1999-06-03 | 2001-11-03 | 윤종용 | A liquid crystal display device and a display device for multisync and each driving apparatus thereof |
KR20010088733A (en) | 2001-08-28 | 2001-09-28 | 전호민 | Method for internet ear-training |
-
2003
- 2003-08-18 KR KR1020030056827A patent/KR100556535B1/en not_active IP Right Cessation
-
2004
- 2004-01-15 US US10/758,150 patent/US7067921B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5351163A (en) * | 1992-12-30 | 1994-09-27 | Westinghouse Electric Corporation | High Q monolithic MIM capacitor |
US6387750B1 (en) * | 2001-07-02 | 2002-05-14 | Macronix International Co., Ltd. | Method of forming MIM capacitor |
US20040137693A1 (en) * | 2002-07-25 | 2004-07-15 | Dongbu Electronics Co., Ltd. | Method for forming an MIM capacitor |
US20040152256A1 (en) * | 2003-01-08 | 2004-08-05 | Renesas Technology Corp. | Semiconductor device manufacturing method |
US6784069B1 (en) * | 2003-08-29 | 2004-08-31 | Micron Technology, Inc. | Permeable capacitor electrode |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080048225A1 (en) * | 2006-08-25 | 2008-02-28 | Micron Technology, Inc. | Atomic layer deposited barium strontium titanium oxide films |
US20090315089A1 (en) * | 2006-08-25 | 2009-12-24 | Ahn Kie Y | Atomic layer deposited barium strontium titanium oxide films |
US8581352B2 (en) | 2006-08-25 | 2013-11-12 | Micron Technology, Inc. | Electronic devices including barium strontium titanium oxide films |
US9202686B2 (en) | 2006-08-25 | 2015-12-01 | Micron Technology, Inc. | Electronic devices including barium strontium titanium oxide films |
US20130106875A1 (en) * | 2011-11-02 | 2013-05-02 | Qualcomm Mems Technologies, Inc. | Method of improving thin-film encapsulation for an electromechanical systems assembly |
Also Published As
Publication number | Publication date |
---|---|
US7067921B2 (en) | 2006-06-27 |
KR20050019200A (en) | 2005-03-03 |
KR100556535B1 (en) | 2006-03-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6831323B2 (en) | Semiconductor device and method for fabricating the same | |
US7897454B2 (en) | Metal-insulator-metal capacitor and fabrication method thereof | |
US6537912B1 (en) | Method of forming an encapsulated conductive pillar | |
US5840200A (en) | Method of manufacturing semiconductor devices | |
US8148764B2 (en) | Semiconductor device having a high aspect cylindrical capacitor and method for fabricating the same | |
US7056787B2 (en) | Method of manufacturing semiconductor device | |
US7888231B2 (en) | Method for fabricating a three-dimensional capacitor | |
US8723244B2 (en) | Semiconductor device having storage electrode and manufacturing method thereof | |
US7407897B2 (en) | Capacitor of analog semiconductor device having multi-layer dielectric film and method of manufacturing the same | |
US7557003B2 (en) | MIM capacitor manufacturing method | |
US8692305B2 (en) | Semiconductor devices and structures including at least partially formed container capacitors | |
US20040115881A1 (en) | Method for fabricating capacitor of semiconductor device | |
US20060024883A1 (en) | Method for fabricating semiconductor memory device having cylinder type storage node | |
US7508020B2 (en) | Semiconductor device and method of manufacturing the same | |
US7067921B2 (en) | Method for fabricating a metal-insulator-metal capacitor in a semiconductor device | |
US6884673B2 (en) | Methods of forming integrated circuit devices having metal-insulator-metal (MIM) capacitor | |
KR100632526B1 (en) | Method of Making a Structured Material Layer | |
US6440869B1 (en) | Method of forming the capacitor with HSG in DRAM | |
JP2004282041A (en) | Manufacturing method for semiconductor device | |
KR0151058B1 (en) | Ferroelectric capacitor and its fabrication method | |
KR100528072B1 (en) | Method for manufacturing capacitor | |
KR100532851B1 (en) | Method for fabricating capacitor of semiconductor device | |
KR20050071012A (en) | Method for fabricating mim capacitor of semiconductor device | |
US7364979B2 (en) | Capcitor with single crystal tantalum oxide layer and method for fabricating the same | |
KR20060095322A (en) | Method for forming capacitor of semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: DONGBU ELECTRONICS CO., LTD., KOREA, REPUBLIC OF Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHOI, CHEE HONG;REEL/FRAME:014959/0179 Effective date: 20040113 |
|
AS | Assignment |
Owner name: DONGBUANAM SEMICONDUCTOR, INC., KOREA, REPUBLIC OF Free format text: MERGER;ASSIGNOR:DONGBU SEMICONDUCTOR INC.;REEL/FRAME:016593/0667 Effective date: 20041221 |
|
FEPP | Fee payment procedure |
Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: DONGBU ELECTRONICS CO., LTD., KOREA, REPUBLIC OF Free format text: CHANGE OF NAME;ASSIGNOR:DONGBU ANAM SEMICONDUCTORS, INC;REEL/FRAME:017718/0964 Effective date: 20060410 |
|
FEPP | Fee payment procedure |
Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
REMI | Maintenance fee reminder mailed | ||
AS | Assignment |
Owner name: DSS TECHNOLOGY MANAGEMENT, INC., VIRGINIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:DONGBU HITEK CO., LTD.;REEL/FRAME:033035/0680 Effective date: 20140522 |
|
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20140627 |