US20040239469A1

US20040239469A1 - Embedded 3D coil inductors in a low temperature, co-fired ceramic substrate

Info

Publication number: US20040239469A1
Application number: US10/884,597
Authority: US
Inventors: Shaul Branchevsky
Original assignee: National Semiconductor Corp
Current assignee: National Semiconductor Corp
Priority date: 1999-09-15
Filing date: 2004-07-02
Publication date: 2004-12-02
Also published as: US6778058B1; US6470545B1

Abstract

A method for forming an embedded three-dimensional inductor is provided. Generally, a first coil winding is formed. A first dielectric layer is placed on the first coil winding. At least part of second coil winding is formed on the first dielectric layer and part of the first coil winding to create an electrical contact between the first coil winding and the second coil winding. A first tape layer with a cavity is provided, where the first coil winding, the first dielectric layer, and the second coil winding are within the cavity of the first tape layer.

Description

RELATED APPLICATIONS

This application is a continuation-in-part of U.S. application Ser. No. 09/632,361, filed on Aug. 3, 2000, which is a continuation-in-part of U.S. Pat. No. 6,252,761 issued on Jun. 26, 2001, which are incorporated by reference.[0001]

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to the field of inductors, and more particularly to embedded multi-layer inductors formed in a low temperature, co-fired ceramic (LTCC) substrate.

2. Description of the Related Art

Conventionally, electronic circuit components, including silicon chips, have been mounted on printed circuit boards. More recently, in order to reduce the size associated with conventional printed circuit boards, low temperature, co-fired ceramic (LTCC) substrates have been used.

A typical LTCC configuration comprises multiple layers of ceramic “tape” which are used to provide the base structure upon which to form various electronic components and electrical connections. The tape is formed from a powdered ceramic, mixed with a binder. For example, one type of ceramic tape available from Dupont is known as “Green Tape 951.” The electronic components that can be formed include resistors, capacitors, inductors, and the like. The electrical connections, formed through each tape layer, are known as “vias.” The components are formed by punching holes/vias in the tape as appropriate, and layering on metal, dielectrics, insulators, etc. Several layers of tape may be used in order to form the desired circuitry. The tape layers are then pressed together and fired in an oven to remove the binder and to sinter the ceramic powder. Components which are too large or too difficult to form within the ceramic tape layers, such as silicon capacitors, resistors, inductors, and chips, may be surface mounted on the hardened substrate. The resulting substrate is usually less than 1″×1″, thus providing a compact circuit package.

FIG. 1 shows an example of the structure of a

basic capacitor

10 formed within an LTCC substrate. A standard process to form this structure will now be described, with reference to FIG. 1. First, a hole is punched in a first tape layer 12 to form an opening. A silver, silver palladium, or similar paste is wiped across the hole to form a via 16, which is used as one terminal connection for the capacitor 10. Next, a first electrode 18 may be formed on top of the via 16 using silver, silver palladium or other similar electrode paste. After the electrode 18 has dried, a dielectric 20 is formed on top of the electrode 18. A dielectric paste is usually used, which when hardened, provides the desired dielectric properties. A second electrode 22 is then formed on top of the dielectric layer 20. These various component layers are commonly formed using a screen printing process. A second ceramic tape layer 14 having a via 24 is then pressed on top of the first layer 12. The second via 24 provides a second terminal for the capacitor 10. After the substrate is fired at 750-950° C., a capacitor structure 30 is formed as shown in FIG. 2. A top view of the capacitor structure 30 is shown in FIG. 3. The vias can have cross-sectional shapes of circles, squares, or rectangles.

This procedure forms what is known in the art as a single layer ceramic capacitor (SLCC), also known as a mono-layer capacitor. Another embodiment of an SLCC is shown in FIG. 4. Specifically, the

vias

42, 44 may be formed on the side of the

electrodes

46, 48, or with one via 42 in the middle of one electrode 46, and one via 44 on the side of the other electrode 48. The electrodes and dielectrics may also be formed as circles, squares or rectangles as shown in FIGS. 5(A)-5(C).

For standard capacitor configurations, the capacitance of a structure is determined according to the following formula:

C=(kA)/t, where k is the dielectric constant of the dielectric material, A is the overlapping area between the electrodes, and t is the thickness of the dielectric, as shown in FIG. 7. Note that in FIG. 7, the dielectric area A and the electrode area A are presumed to be the same, but in practice the dielectric is usually made larger to ensure that the electrode layers do not touch. Thus, by changing the dielectric material, the capacitance value may be changed. FIG. 6 illustrates an SLCC in which a different dielectric is used, in order to change the capacitance. Instead of using a dielectric paste, the dielectric may be formed from a high firing temperature ceramic tape (1100-1400° C.). The

high temperature tape

66 is fired separately, and then placed on the first electrode 72. The dielectric constant of the high temperature tape 66 is several orders of magnitude greater (k=20-20,000) than the dielectric constant of the standard tape (k=7-8) used to form the

layers

62, 64.

Standard tape

68,70 may be used around the dielectric to provide a constant thickness between the

main layers

62, 64.

Two articles which discuss LTCC technology include “Characterization and Performance Prediction for Integral Capacitors in Low Temperature Co-Fired Ceramic Technology,” Delaney et al., IEEE Transactions on Advanced Packaging, Vol. 22, No. 1, February 1999, pgs. 68-77; and “Characteristics of the Electrical Performance of Buried Capacitors and Resistors in Low Temperature Co-Fired (LTCC) Ceramic,” Delaney et al., 1998 Electronic Components and Technology Conference, pgs. 900-908, the disclosures of which are herein incorporated by reference. While these articles seek to address the problem of providing capacitors with increased capacitance, the capacitors are still confined to being formed within a single layer of ceramic tape. The disclosed processes cannot make high capacitance capacitors and they require numerous types of dielectric materials in order to create different capacitances.

Since there is a practical limit to the dielectric constant that can be achieved, single layer capacitors do not provide sufficient capacitance within a reasonable area, for many applications. Thus, for high value capacitances, external capacitors are often surface mounted on the ceramic substrate. An example of one type of capacitor 8000 used for this purpose is shown in FIG. 8. Multiple layers of electrodes are formed in a discrete ceramic capacitor, and are used in order to increase the capacitance, while still providing a relatively small component. Adding external components, however, increases the costs associated with the LTCC circuit.

The articles “Manufacture of Embedded Integrated Passive Components into Low Temperature Co-Fired Ceramic Systems,” Scrantom et al., 1998 International Symposium on Microelectronics 1998, pp. 459-466, “3 D-Integration of Passive RF-Components in LTCC,” Muller et al., (DO YOU KNOW WHERE AND WHEN THIS WAS PUBLISHED?), and “Integrated Passive Components Using Low Temperature Cofired Ceramics,” Wersing et al., 1998 International Symposium on Microelectronics, 1998, pp. 193-199, discuss the embedding inductors in co-fired ceramics.

FIG. 18 is an end view of an LTCC planar inductor that may be used in the prior art. In this example,

planar inductor

1804 is placed between a first tape layer 1808 and a second tape layer 1812. FIG. 19 is a cross-sectional view of FIG. 18 along cut lines 19-19. The planar inductor 1804 is in a single plane, but has a serpentine or meandering shape, as shown. The serpentine shape provides a low inductance inductor in a single plane.

FIG. 20 is a side view of an LTCC three dimensional inductor that may be used in the prior art. In this example, a first

ceramic tape layer

2004, a second ceramic tape layer 2008, a third ceramic tape layer 2012, and a fourth ceramic tape layer 2016 are provided. Between the first and

second tape layers

2004, 2008, a first inductor ring 2020 is provided. A second inductor ring 2024 may be placed between the second and

third tape layers

2008, 2012. A third inductor ring 2028 may be placed between the third and fourth tape layers 2012, 2016. The first, second, and third inductor rings 2020, 2024, 2028 are embedded and therefore are shown with broken lines. FIG. 21 is a cross-sectional view of the LTCC three-dimensional inductor shown in FIG. 20 along cut lines 21-21, which shows a cross-sectional view of the second tape layer 2008 and the second inductor ring 2024. The second inductor ring 2024 forms an almost complete ring with a first end and a second end. A first via pad 2104 is at a first end of the second inductor ring 2024. A second via pad 2108 is at a second end of the second inductor ring 2024. Similarly, the first inductor ring 2020 and the third inductor ring 2028 may have first and second ends. A first electrode 2032 may be electrically connected to the first end of the first inductor ring 2020. A first via 2036 may be electrically connected between the second end of the first inductor ring 2020 and a first via pad 2104. A second via 2040 may be electrically connected between the second via pad 2108 and the first end of the third inductor ring 2028. A second electrode 2044 may be electrically connected to the second end of the third inductor ring 2028. As can be seen in FIG. 21, the second electrode 2044 passes through the hole in the second inductor ring 2024. The resulting inductor provides about three turns over about three or four ceramic tape layers.

Higher, more compact inductors may be surface mounted on the ceramic substrate.

It would thus be desirable to have a 3-D embedded inductor that is thinner than the prior art. Such thinner inductors are more compact, taking up less landscape and may provide higher inductance.

SUMMARY OF THE INVENTION

To achieve the foregoing and other objects and in accordance with the purpose of the present invention, a variety of techniques for forming an embedded three-dimensional inductor is provided. Generally, a first coil winding is formed. A first dielectric layer is placed on the first coil winding. At least part of second coil winding is formed on the first dielectric layer and part of the first coil winding to create an electrical contact between the first coil winding and the second coil winding. A first tape layer with a cavity is provided, where the first coil winding, the first dielectric layer, and the second coil winding are within the cavity of the first tape layer.

In addition, an embedded three-dimensional inductor in a low temperature, co-fired ceramic (LTCC) substrate is provided. Generally, a tape layer with a cavity is provided. An inductor coil is within the cavity, where the inductor coil comprises a first winding and at least part of a second winding spaced vertically apart from the first winding. A dielectric layer is within the cavity between the first winding and the at least part of the second winding.

Thus, the present invention is not limited to any specific configuration or geometry of openings or vias, but the teachings encompass any structure having exposed vias connected to the edges of alternating layers of electrodes, in order to provide electrical connectivity.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements, and in which: [0021]
FIG. 1 is diagram of a prior art single layer ceramic capacitor (SLCC). [0022]
FIG. 2 is a diagram of the SLCC of FIG. 1 after the ceramic tape has been pressed and fired. [0023]
FIG. 3 is a top view of the capacitor of FIG. 2. [0024]
FIG. 4 is a diagram of an alternative embodiment of an SLCC according to the prior art. [0025]
FIGS. [0026] 5(A)-5(C) are diagrams of different configurations of the electrodes and dielectric layers of an SLCC according to the prior art.
FIG. 6 is a diagram of an SLCC according to the prior art having a high temperature ceramic tape used as a dielectric. [0027]
FIG. 7 is a diagram illustrating the area and thickness variables as used in the standard capacitance formula. [0028]
FIG. 8 is a diagram of a prior art discrete ceramic multi-layer capacitor suitable for surface mounting on an LTCC substrate. [0029]
FIG. 9 is a diagram illustrating an embedded multi-layer LTCC formed according to a preferred embodiment of the present invention. [0030]
FIG. 10 is a diagram illustrating an opening in a tape layer suitable for use with the present invention. [0031]
FIG. 11 is a top view of the capacitor of FIG. 9. [0032]
FIG. 12 is a side view of the capacitor of FIG. 9, after firing. [0033]
FIGS. [0034] 13(A)-13(J) illustrate top views of various alternative embodiments of the vias and openings for a capacitor according to the present invention.
FIG. 14 is a diagram of two capacitors formed within a single opening. [0035]
FIG. 15 is a diagram of two capacitors formed within a single opening, with each electrode having a different surface area. [0036]
FIG. 16 is a diagram of a cross-section of a tape layer showing the bisected, exposed vias. [0037]
FIG. 17 is a diagram illustrating an embodiment of the present invention in which the electrodes and dielectric layers are round. [0038]
FIG. 18 is an end view of an LTCC planar inductor that may be used in the prior art. [0039]
FIG. 19 is a cross-sectional view of FIG. 18 along cut lines [0040] 19-19.
FIG. 20 is a side view of an LTCC three-dimensional inductor that may be used in the prior art. [0041]
FIG. 21 is a cross-sectional view of the LTCC three-dimensional inductor shown in FIG. 20 along cut lines [0042] 21-21.
FIG. 22 is a flow chart of a method of making an inventive 3D inductor. [0043]
FIG. 23 is a cross-sectional view of a first ceramic tape layer. [0044]
FIG. 24 is a cross-sectional view of a second tape layer with a cavity. [0045]
FIG. 25 is a more detailed flow chart of an embodiment of providing a 3D inductor according to the invention. [0046]
FIG. 26 is a cross-sectional view of a first part of an inductor coil printed on a first ceramic tape layer. [0047]
FIG. 27 is a top view of the first part of the inductor coil printed on the first ceramic tape layer. [0048]
FIG. 28 is a top view of a first dielectric sheet laminated over part of the first part of the inductor coil. [0049]
FIG. 29 is a top view of a second part of the inductor coil printed over the first dielectric sheet and the first part of the inductor coil. [0050]
FIG. 30 is a top view of a second dielectric sheet laminated over part of the first part of the inductor coil and part of a second part of the inductor coil. [0051]
FIG. 31 is a top view of a third dielectric sheet laminated over part of a third part of the inductor coil and part of the second part of the inductor coil. [0052]
FIG. 32 is a top view of a fourth dielectric sheet laminated over part of a fourth part of the inductor coil and part of a third part of the inductor coil. [0053]
FIG. 33 is a schematic illustration of a cross-sectional view of FIG. 32, along cut lines [0054] 33-33. FIG. 34 is an exploded cross-sectional view of the first tape layer with an inductor formed thereon, the second tape layer with the cavity, and a third tape layer with a via.
FIG. 35 is a cross-sectional view of the assembled first tape layer with an inductor formed thereon, the second tape layer with the cavity, and a third tape layer with a via. [0055]
FIG. 36 is a top view of part of an incomplete rectangular shaped inductor coil on a first tape layer.[0056]

DETAILED DESCRIPTION OF THE INVENTION

The following description is provided to enable any person skilled in the art to make and use the invention and sets forth the best modes contemplated by the inventor for carrying out the invention. Various modifications, however, will remain readily apparent to those skilled in the art, since the basic principles of the present invention have been defined herein specifically to provide an embedded [0057] 3D inductor in a low temperature, co-fired ceramic (LTCC) substrate.
A preferred embodiment of forming a multi-layer capacitor is illustrated in FIG. 9. An embedded multi-layer [0058] ceramic capacitor 100 is formed using three ceramic tape layers 102, 104, 106. In a standard LTCC substrate, additional layers are used to form additional circuitry. These additional layers are omitted from the discussion herein for clarity. The first tape layer 102 is formed with a via 108 in the conventional manner. The second layer 104, however, is first formed with appropriately spaced vias 128, 130, which are then punched through to expose a cross-section thereof. FIG. 10 shows a top view of one embodiment of the second layer 104 that may be used for the multi-layer ceramic capacitor structure 100. Note that in FIG. 10 the cylindrical vias 128, 130 are bisected by an opening 140 created in the tape layer 104. Many other configurations are easily envisioned and are within the scope of the present invention. For example, the vias may be formed as rectangular blocks, with the opening exposing a side surface of each via, without necessarily bisecting the blocks. Also, in the preferred embodiment, two vias are bisected on each side of the opening 140, though only one via per side may be used.
The [0059] opening 140 in the second layer 104 provides a cavity in which to build the multiple electrode and dielectric layers needed to form a multi-layer capacitor. Specifically, as shown in FIG. 9, a first electrode layer 110 is formed on top of the first tape layer 102, overlapping the via 108. Alternating layers of dielectric material 112, 116, 120, 124 and electrodes 114, 118, 122, 126 are then formed on top of the first electrode layer 110. The electrode layers 114, 118, 122, 126 are formed so that each successive layer corresponds to an alternate terminal. In other words, layers 110, 118 and 126 form a first set of electrodes, which connect to the via 108 in the first tape layer 102. The remaining electrode layers 114 and 122 form a second set of electrodes, which connect to the via 134 in the third tape layer 106. The two vias 108, 134 thus correspond to the standard two terminals of a standard capacitor.
An [0060] individual electrode layer 114 is formed such that one end is exposed past the underlying dielectric layer 112 to connect to the adjacent exposed via 130, while the other end of the electrode 114 is formed to ensure that it does not connect to the adjacent exposed via 128. By alternating the just described electrode configuration, each electrode layer is electrically connected to an alternating exposed via. An electrical connection is formed on top of the second tape layer 104 to connect to the via 134 in the third tape layer 106. The exposed vias 128, 130 thus provide electrical connections for alternating sets of electrodes, allowing multi-layer ceramic capacitors to be formed within an LTCC substrate. When the tape layers 102, 104, 106 (and any additional LTCC layers) are pressed together and oven-fired, the silver paste (or other similar material) used to form the exposed vias 128, 130 and electrode layers 110, 114, 118, 122, 126 flows and joins together forming a permanent electrical connection. FIG. 11 illustrates a top view of the capacitor structure 100 illustrated in FIG. 9. FIG. 12 is a side view of the capacitor of FIG. 9, showing the structure after it has been pressed and fired. Notice that the dielectric material 1001 is now disposed between and around the electrodes such that the opening 140 no longer exists.
Although the preferred embodiment has been described with reference to four layers, a capacitor may be formed having greater or fewer layers. Additional tape layers may also be added between the first [0061] 102 and third 106 tape layers to provide more volume in which to build the capacitor layers. These additional tape layers are basically formed as duplicates of the second tape layer 104, with an opening punched exposing vias on the side, in which the vias provide electrical connections for the alternating layers of electrodes, and with the other tape layer(s).
In the preferred embodiment, the [0062] opening 140 in the second tape layer is formed using a mechanical punch to remove the ceramic tape and expose the vias. A cross-section of one end of an opening is illustrated in FIG. 16 showing the exposed bisected vias 128, 129. Any other methods known to those skilled in the art to remove the ceramic tape may also be used. Additionally, for capacitors having many layers, a standard screen printing process may damage the structure as the layers are being built. To overcome this problem, sidewalls formed from ceramic tape may be used to facilitate the construction of the capacitor. The sidewalls are then removed before adding the second and third tape layers.
In the preferred embodiment, the dielectric layers are formed using a standard dielectric paste. There is no requirement that the same dielectric material be used for each layer, or even that the dielectric layers have the same thickness. In fact, the electrodes themselves may have different sizes, thickness, or have a different alternating pattern than those specifically described herein. [0063]
As mentioned above, in the preferred embodiment the vias in the [0064] second tape layer 104 are formed as cylinders and are bisected with a square opening 140. As shown in FIGS. 13(A)-13(J) (top views), however, numerous alternate embodiments may also be configured. Specifically, FIGS. 13(A)-13(C) illustrate that one, two or three cylindrical vias may be used on each side of the opening. FIG. 13(I) illustrates an embodiment wherein the opening is round instead of square, with the associated electrode and dielectric layers formed as circles to fit within the rounded opening. FIGS. 13(E) and 13(H) illustrate embodiments in which the vias are wider, providing greater surface area to contact the electrodes.
These embodiments illustrate that the vias are generally bisected, but more or less of the via may be removed by the punching process without departing from the scope of the present invention. In fact, in a configuration in which the vias have a flat-facing surface (as viewed from the opening), only enough of the ceramic tape needs to be removed as will expose the surface of the vias. Thus, the present invention is not limited to any specific configuration or geometry of openings or vias, but is deemed to encompass any structure having exposed vias connected to the edges of alternating layers of electrodes, in order to provide electrical connectivity. [0065]
FIGS. [0066] 13(D), 13(F), 13(G), and 13(J) illustrate several possible configurations for creating two different capacitors within the same opening, by using vias on each side of the opening. These configurations will now be explained further with reference to FIGS. 14 and 15. In FIG. 14, corresponding to the via structure of FIG. 13(F), two separate capacitors are formed within the same opening. By orienting the capacitors' electrodes 1400 90° to each other, the configuration provides better performance at high frequencies for certain design applications. Also, the effective surface area for one capacitor structure may be different than the area for the second structure. This allows two capacitors to be formed in a single opening, providing a significant size advantage as compared to the SLCC designs of the prior art.
FIG. 15, corresponding to the via structure of FIG. 13(D), illustrates that four different electrode sizes may be interleaved as desired to provide two different capacitances within a [0067] single opening 152. Specifically, two sets of electrodes 156, 158 may be formed at right angles corresponding to a first capacitor. Two additional sets of electrodes 160, 162 are also formed in the same opening 152. Dielectric layers 154 are inter-spaced between the electrode layers. Each set of electrodes has a corresponding set of vias. This structure provides significant space savings over the previously utilized SLCC. Those skilled in the art will appreciate that many other configurations other than those specifically described herein may be formed utilizing the basic teachings of the present invention. For example, the electrodes and dielectrics may be shaped as necessary to fit any desired shape of opening such as a circle. A circular embodiment using a circular opening 1704, a first circular electrode 1708, and a second circular electrode 1712 is illustrated in FIG. 17.
FIG. 22 is a flow chart of a method of making an inventive [0068] 3D inductor. A first ceramic tape layer is provided (step 2204). FIG. 23 is a cross-sectional view of a first ceramic tape layer 2304. In this embodiment, the first tape layer 2304 has a via 2308, which will be used to provide an electrical connection. A second tape layer is provided with a cavity (step 2208). FIG. 24 is a cross-sectional view of a second tape layer 2404 with a cavity 2408. The cavity 2408 is a hole, which in this embodiment passes entirely through the second tape layer 2404. A 3D inductor is provided in the cavity 2408 of the second tape layer 2404 (step 2212). A third tape layer may be provided over the cavity (step 2216).
FIG. 25 is a more detailed flow chart of an embodiment of providing a 3D inductor according to the invention. A first part of an inductor coil is printed on the first tape layer (step [0069] 2504). FIG. 26 is a cross-sectional view of a first part of an inductor coil 2604 printed on the first ceramic tape layer 2304. FIG. 27 is a top view of the first part of the inductor coil 2604 printed on the first ceramic tape layer 2304. In this embodiment, the first part of the inductor coil 2604 forms a via pad 2704, which is electrically connected to the via 2308 in the first ceramic tape layer 2304, and part of a loop 2708 which forms part of a three-dimensional coil. A first dielectric sheet is laminated over part of the first part of the inductor coil (step 2508). FIG. 28 is a top view of a first dielectric sheet 2804 laminated over part of the first part of the inductor coil 2604. A second part of the inductor coil 2904 is printed over the first dielectric sheet and the first part of the inductor coil (step 2512), as shown in FIG. 29. The part of the second part of the inductor coil 2904 printed on part of the first part of the inductor coil 2604 forms an electrical connection between the first part of the inductor coil 2604 and the second part of the inductor coil 2904. A second dielectric sheet 3004 is laminated over part of the first part of the inductor coil 2604 and part of the second part of the inductor coil 2904 (step 2516), as shown in FIG. 30. A third part of the inductor coil 3008 is printed over the second dielectric sheet and part of the second part of the inductor coil (step 2520). A third dielectric sheet 3104 is laminated over part of the third part of the inductor coil 3008 and part of the second part of the inductor coil 2904 so that all of the second part of the inductor coil 2904 is covered, as shown in FIG. 31 (step 2524). The third dielectric sheet 3104 is also placed over the first dielectric sheet 2804. A fourth part of the inductor coil 3108 is printed over part of the third part of the inductor coil 3008 and the third dielectric sheet 3104 (step 2528). A fourth dielectric sheet 3204 is laminated over part of the fourth part of the inductor coil 3108 and part of the third part of the inductor coil 3008 so that all of the third part of the inductor coil 3008 is covered, as shown in FIG. 32 (step 2532). An electrode, which forms a fifth part of the inductor coil 3208 is printed over part of the fourth part of the inductor coil 3108 and the fourth dielectric sheet 3204 (step 2536).
FIG. 33 is a schematic illustration of a cross-sectional view of FIG. 32, along cut lines [0070] 33-33. The resulting three-dimensional LTCC inductor 3304 is formed on the first tape layer 2304. FIG. 34 is an exploded cross-sectional view of the first tape layer 2304 with the inductor 3304 formed thereon, the second tape layer 2404 with the cavity 2408, and a third tape layer 3404 with a via 3408. The second tape layer 2404 is placed on top of the first tape layer 2304 so that the inductor 3304 is in the cavity 2408 (step 2212), as shown in FIG. 35. The third tape layer 3404 is placed on top of the second tape layer 2404, so that the third tape layer 3404 covers the cavity 2408 in the second tape layer 2404 (step 2216). The via 3408 in the third tape layer 3404 makes electrical contact with the fifth part of the inductor coil 3208. The first, second, and third tape layers 2304, 2404, 3404, and the inductor 3304 may all be fired together. A judicious selection of materials allows these components to shrink in about the same proportions.
Printing may be by any method that provides a layer of a conductive material on a substrate, such as a screen printing process. Laminating may be any method that provides a sheet, such as a layer of a dielectric material on a substrate. The laminating of a dielectric sheet may be accomplished by placing a sheet of dielectric paste over part of the inductor coil. There is no requirement that the same dielectric material be used for each layer, or even that the dielectric layers have the same thickness. [0071]
In this embodiment, the [0072] first part 2604 and the second part 2904 of the inductor coil form a first coil winding. The third inductor part 3008 and the fourth inductor part 3108 form a second coil winding. The first, second, third, and fourth dielectric sheets 2804, 3004, 3104, 3204 provide an electrical insulation and separation between coil windings. The second and third dielectric sheets form a dielectric layer that separates the first coil winding from the second coil winding. The dielectric layer has about the same thickness as the dielectric sheets which form it, so that the second ceramic tape layer is several times the thickness of the dielectric layer. The fifth inductor part 3208 may form part of a third coil winding, with the fourth dielectric sheet 3204 forming a second dielectric layer which separates the second coil winding from the part of the third coil winding. The first coil winding and the second coil winding are vertically displaced along a direction “V”, which is generally along the thickness “T” of the second tape layer 2404, as shown in FIG. 35. In this embodiment, the second coil winding has the same shape and location as the first coil winding, except that the second coil winding is vertically displaced from the first coil winding, so that both the first coil winding and the second coil winding have centers that form a vertical line. Generally, the inductor coil comprises a first winding and at least part of a second winding, where part of the second winding overlaps the first winding and where a dielectric layer is used to provide insulation between the first winding and the second winding. The cavity may only be partly through the thickness of the second tape layer.
In other embodiments, other numbers of turns may be used to form the inductor coil. Fractions of turns may be used. Other shapes of the inductor coil may also be used. For example, the inductor coil may have a square shape, a rectangular shape, or an oval shape. FIG. 36 is a top view of part of an incomplete rectangular [0073] shaped inductor coil 3604 on a first tape layer 3608. Different via configurations in ceramic tape layers may be used to provide electrical connections to the inductor. Other embodiments may use segmented dielectric sheets, where a single dielectric sheet may comprise one or more separate dielectric sheets, which may be spaced apart, adjacent to each other, or may overlap each other. In addition, each part of the inductor coil may comprise smaller parts that are printed separately.
Those skilled in the art will appreciate that various adaptations, modifications, permutations, and substitute equivalents of the just-described preferred embodiments can be configured without departing from the scope and spirit of the invention. The present invention, in general, is an apparatus and method for forming a three-dimensional inductor in an LTCC substrate. Therefore, it is to be understood that, within the scope of the appended claims, the invention may be practiced other than as specifically described herein. [0074]

Claims

1-10. (Canceled)

11. A method of forming an embedded three-dimensional inductor, comprising:

forming a first coil winding;

placing a first dielectric layer on the first coil winding;

forming at least part of second coil winding on the first dielectric layer and part of the first coil winding to create an electrical contact between the first coil winding and the second coil winding; and

providing a first tape layer with a cavity, wherein the first coil winding, the first dielectric layer, and the second coil winding are within the cavity of the first tape layer.

12. The method, as recited in claim 11, wherein the forming of the second coil winding comprises printing the second coil winding on the first dielectric layer and part of the first coil winding.

13. The method, as recited in claim 12, further comprising a second tape layer, wherein the forming of the first coil winding comprises printing the first coil winding on the second tape layer.

14. The method, as recited in claim 13, wherein forming the at least part of the second coil winding comprises forming a complete second coil winding, and further comprising:

placing a second dielectric layer on the second coil winding; and

forming a third coil winding on the second dielectric layer.

15. The method, as recited in claim 14, further comprising firing the first tape layer, the second tape layer, the first, second, and third coil windings, and the first and second dielectric layers together.

16. The method, as recited in claim 15, further comprising the step of creating an electrical connection between the first coil winding and a via in the second tape layer.

17. The method, as recited in claim 16, wherein the placement of the second dielectric layer comprises:

placing a first dielectric sheet; and

placing a second dielectric sheet.

18. The method, as recited in claim 11, further comprising firing the first tape layer, the first and second coil windings, and the first dielectric layer together.