JP2001085231A - Laminated inductor - Google Patents

Laminated inductor

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Publication number
JP2001085231A
JP2001085231A JP26337899A JP26337899A JP2001085231A JP 2001085231 A JP2001085231 A JP 2001085231A JP 26337899 A JP26337899 A JP 26337899A JP 26337899 A JP26337899 A JP 26337899A JP 2001085231 A JP2001085231 A JP 2001085231A
Authority
JP
Japan
Prior art keywords
laminated
conductive pattern
magnetic
magnetic material
magnetic plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26337899A
Other languages
Japanese (ja)
Inventor
Takeo Uegaki
武男 上柿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokin Corp
Original Assignee
Tokin Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokin Corp filed Critical Tokin Corp
Priority to JP26337899A priority Critical patent/JP2001085231A/en
Publication of JP2001085231A publication Critical patent/JP2001085231A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To obtain a laminated inductor with which the size and pitch of electronic equipment can be reduced and the density of the equipment can be increased more easily than the conventional manufacturing method. SOLUTION: A laminated inductor has first and second magnetic material layers 1 and 1', four magnetic material layers 3 having notched windows 4 formed at prescribed portions of the surfaces of the layers 3 between the magnetic material plates 1 and 1', and a conductive pattern 2 laminated upon the first magnetic material plate 1 by printing. The inductor is formed in such a way that the printed layers 3 are laminated upon another by a printing method so that the notched windows 4 may become coincident with the terminating end section 2b of the pattern 2, and a conductive pattern 5 is laminated upon one magnetic layer 5 so that its starting end section 5a may be connected to the terminating end section 2b through the notched window 4. After the magnetic material layers 3 are successively laminated upon another by the above-mentioned method and a conductive pattern 8 is finally laminated upon the uppermost magnetic material layer 3, a small element 22 is formed by press-fixing the magnetic material plate 1' to the pattern 8 and a plurality of small elements 11 thus formed are laminated upon another.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、磁性体層と導電パ
ターンとを積層し、プリント配線板に実装される多ライ
ンを1素子で作用させるインダクタ素子、インピーダン
ス素子とする高帯域周波数用の積層型インダクタに関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency band lamination in which a magnetic layer and a conductive pattern are laminated, and a multi-line mounted on a printed wiring board acts as a single element as an inductor element and an impedance element. It relates to a type inductor.

【0002】[0002]

【従来の技術】プリント配線板などに実装される積層型
インダクタはフェライトなどの強磁性材を加工してなる
磁性体生シートを所望の寸法に加工した複数個の磁性体
板と、それらの間に交互に差し込まれた複数個の導電パ
ターンとを積層し、二次元的空間での複数個を1個の素
子として形成されるものである。
2. Description of the Related Art A multilayer inductor mounted on a printed wiring board or the like has a plurality of magnetic plates formed by processing a raw magnetic sheet formed of a ferromagnetic material such as ferrite into a desired size, and a plurality of magnetic plates between them. And a plurality of conductive patterns alternately inserted in a two-dimensional space are formed as one element.

【0003】[0003]

【発明が解決しようとする課題】しかしながら、近年の
電子機器における小型化、低ピッチ化、高密度化の要求
はめざましく、上記した従来技術では、小素子を形成す
る面槓には限界があり、小型化対応には困難であった。
However, in recent years, there has been a remarkable demand for downsizing, lower pitch, and higher density in electronic devices, and the conventional technology described above has a limit on the surface kong for forming a small element. It was difficult to cope with miniaturization.

【0004】例えば、長さ3.2mm、幅1.6mm、
高さ1.6mmの4ラインアレイを形成しようとした場
合、一つの小素子は、長さ×幅を0.6mm×1.6m
mにしなくてはならない。本考案では、1つの小素子が
1.6mmx1.6mmの小素子を形成すれば良く、小
型化対応に優位であると共に、磁気回路を有効にするこ
とができる。
For example, a length of 3.2 mm, a width of 1.6 mm,
When a four-line array having a height of 1.6 mm is to be formed, one small element has a length × width of 0.6 mm × 1.6 m.
m. In the present invention, one small element only needs to form a small element of 1.6 mm × 1.6 mm, which is advantageous in miniaturization and enables the magnetic circuit to be effective.

【0005】本発明の課題は上記問題点を解消する積層
型インダクタを提供することである。
An object of the present invention is to provide a multilayer inductor that solves the above problems.

【0006】[0006]

【課題を解決するための手段】本発明によれば、一対の
第1の磁性体板及び第2の磁性体板と、これらの間に面
の所定部分に切り欠き窓が形成されたN(Nは1以上の
整数)個の磁性体層を有し、最下層の前記磁性体板上に
渦帯状の第1の導電パターンを印刷法により積層し、前
記渦帯状の導電パターンの終端部分に前記切り欠き窓を
一致させるように第1番目の前記磁性体層を印刷法によ
り積層し、その上から第2の渦帯状の導電パターンを、
その始端部分が前記切り欠き窓を介して前記終端部分に
接続されるように、印刷法により前記第1番目の磁性体
層に積層し、以後上記した方法により順々に積層してい
き、第N番目の磁性体層上に第(N+1)の渦帯状の導
電パターンを積層した後、前記第2の磁性体板を圧着し
て小素子を形成し、該小素子を複数個積層して形成され
たことを特徴とする積層型インダクタが得られる。
According to the present invention, a pair of a first magnetic plate and a second magnetic plate, and a notch window formed between the pair of first and second magnetic plates at a predetermined portion of the surface. N is an integer of 1 or more) magnetic material layers, and a spiral-shaped first conductive pattern is laminated on the lowermost magnetic material plate by a printing method, and is provided at an end portion of the spiral-shaped conductive pattern. The first magnetic layer is laminated by a printing method so that the cutout windows coincide with each other, and a second spiral conductive pattern is formed thereon from above.
The first magnetic layer is laminated on the first magnetic layer by a printing method so that the start end portion is connected to the end portion through the cutout window, and then sequentially laminated by the above-described method. After laminating the (N + 1) th spiral conductive pattern on the Nth magnetic layer, the second magnetic plate is pressed to form small elements, and a plurality of such small elements are laminated. Thus, a multilayer inductor is obtained.

【0007】さらに、本発明によれば、前記第1の磁性
体板と密着する導電パターンの始端部分と前記第2の磁
性体板に密着する導電パターンの終端部分とがともに前
記磁性体板の縁辺に露出するように形成され、該露出部
分が外部電極に接続されていることを特徴とする積層型
インダクタが得られる。
Further, according to the present invention, both the start end portion of the conductive pattern that is in close contact with the first magnetic plate and the end portion of the conductive pattern that is in close contact with the second magnetic plate are formed on the magnetic plate. The multilayer inductor is formed so as to be exposed at the edge, and the exposed portion is connected to the external electrode.

【0008】[0008]

【発明の実施の形態】以下、本発明の一実施の形態につ
いて図面を参照して詳細に説明する。図1は本発明の一
実施の形態のアレイ型積層チップインダクタの分解斜視
図である。図2は図1のアレイ型積層チップインダクタ
の外観斜視図を示す。まず、絶縁性磁性粉末に対してバ
インダ樹脂(PVB樹脂)5wt%、有機系溶剤(エチ
レングリコールエーテル系)60wt%等を添加し、混
合を行い、スラリー化する。このスラリーをドクターブ
レード法を用いて膜厚200〜600μmの長尺な絶縁
性磁性体板をつくる。
Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is an exploded perspective view of an array type multilayer chip inductor according to an embodiment of the present invention. FIG. 2 is an external perspective view of the array-type multilayer chip inductor of FIG. First, 5 wt% of a binder resin (PVB resin) and 60 wt% of an organic solvent (ethylene glycol ether) are added to the insulating magnetic powder, mixed, and slurried. This slurry is used to form a long insulating magnetic plate having a thickness of 200 to 600 μm by using a doctor blade method.

【0009】図1に示すように、得られた磁性体板上
に、複数個連続して生成されるチップ1個分において、
その縁辺にそって最初の始端部分2aを突出させて渦帯
状の第1の導電パターン2をAgペースト等にてスクリ
ーン印刷法により印刷し、加熱により乾燥する。この第
1の導電パターン2上にその終端部分2bが露出するよ
うな位置に切り欠き窓4が形成(刻設)された薄い磁性
体層3を、絶縁性非磁性粉末に対してバインダ樹脂(P
VB樹脂)5wt%、有機系溶剤(エチレングリコール
エーテル系)60wt%等を添加し、混合を行ったスラ
リーでスクリーン印刷法により印刷し、加熱により乾燥
させる。さらに、磁性体層3の上に、その切り欠き窓4
内に露出している第1の導電パターン2の終端部分2b
と第2の導電パターン5の始端部分5aが電気的に接続
されるように、第1の導電パターン2とライン幅の異な
る第2の導電パターン5を前記と同様に形成する。以
下、同様に、第2の導電パターン5の終端部分5bを切
り欠き窓4が設けられた磁性体層3を介して第3の導電
パターン6の始端部分6aに接続していく。
As shown in FIG. 1, on a magnetic plate obtained, one chip continuously generated
The first starting end portion 2a is projected along the edge, and the first conductive pattern 2 in the form of a swirl is printed by a screen printing method using an Ag paste or the like, and dried by heating. A thin magnetic layer 3 in which a cutout window 4 is formed (engraved) at a position where the terminal end portion 2b is exposed on the first conductive pattern 2 is bonded to the insulating nonmagnetic powder with a binder resin ( P
VB resin), 5 wt% of an organic solvent (ethylene glycol ether), etc. are added, and the mixture is printed by a screen printing method using a mixed slurry, and dried by heating. Further, the cutout window 4 is formed on the magnetic layer 3.
Terminal portion 2b of first conductive pattern 2 exposed inside
The second conductive pattern 5 having a line width different from that of the first conductive pattern 2 is formed in the same manner as described above so that the start end portion 5a of the second conductive pattern 5 is electrically connected to the first conductive pattern 5. Hereinafter, similarly, the end portion 5b of the second conductive pattern 5 is connected to the start end portion 6a of the third conductive pattern 6 via the magnetic layer 3 provided with the cutout window 4.

【0010】このように複数個分の素子の上、図面上で
は第5の導電パターン8上に上部絶縁性磁性層としての
磁性体板1′をホットプレスにより圧着し未焼成シート
を形成する。次に、上記したように積層印刷された小素
子11を複数個形成し、これらを複数位置決め重畳し、
所望のライン数に対応したアレイ型積層インダクタ素子
を形成する。この組み立て後のアレイ型積層インダクタ
素子を図2に示す。
As described above, the magnetic plate 1 'as an upper insulating magnetic layer is press-bonded on the plurality of elements, in the drawing, on the fifth conductive pattern 8 by hot pressing to form an unfired sheet. Next, as described above, a plurality of the small elements 11 printed by lamination are formed, and a plurality of the small elements 11 are positioned and overlapped.
An array type multilayer inductor element corresponding to a desired number of lines is formed. FIG. 2 shows the array-type laminated inductor element after the assembly.

【0011】この未焼成シートを所定の大きさに切断
し、個々の未焼成のチップを形成する。これらの未焼成
のチップを大気雰囲気中で脱バインダーした後に、大気
焼成による一体焼成を行い、チップの面取りのためバレ
ル研磨を行い、前記コイルの両端の外部に露出した内部
電極と接続するようにして、チップ側面にAgペースト
等をディップにより塗布し、所定の温度と時間で乾燥さ
せた後、約600゜Cの温度で大気雰囲気により焼き付
けし、電極端子を形成する。
The unsintered sheet is cut into a predetermined size to form individual unsintered chips. After debinding these unfired chips in an air atmosphere, integrated firing by air firing is performed, barrel polishing is performed for chamfering of the chips, and connected to the internal electrodes exposed to the outside at both ends of the coil. Then, an Ag paste or the like is applied to the side surface of the chip by dip, dried at a predetermined temperature and time, and baked at a temperature of about 600 ° C. in an air atmosphere to form electrode terminals.

【0012】次に、得られた電極端子に電解めっきによ
りニッケルめっき層を介してはんだめっきにより外装さ
れることでアレイ型積層チップインダクタが得られる。
Next, the obtained electrode terminals are packaged by solder plating via a nickel plating layer by electrolytic plating to obtain an array type multilayer chip inductor.

【0013】上記した方法により得られたアレイ型積層
チップインダクタによれば、長さ3.2mm、幅1.6
mm、高さ1.6mmの4ラインアレイを形成しようと
した場合、一つの小素子が1.6mm×1.6mmの小
素子を形成すれば良く、小型化対応に優位であると共
に、磁気回路を有効にすることができる。
According to the array type multilayer chip inductor obtained by the above method, the length is 3.2 mm and the width is 1.6.
In order to form a four-line array having a height of 1.6 mm and a height of 1.6 mm, it is sufficient that one small element forms a small element of 1.6 mm × 1.6 mm, which is advantageous for miniaturization and has a magnetic circuit. Can be enabled.

【0014】尚、1つの小素子を形成する場合、切り欠
き窓を設けた磁性体シートに所定の導電パターンを印刷
し、積層しても良い。
When one small element is formed, a predetermined conductive pattern may be printed and laminated on a magnetic sheet provided with a cutout window.

【0015】[0015]

【発明の効果】以上説明した通り、本発明によれば、小
素子上にそれと同一構造の小素子複数個を位置決め重畳
して3次元的に形成することにより、1素子の形成する
面積を確保しつつ、多ライン対応のアレイ型積層インダ
クタが得られ、磁気回路を有効にすることができるとと
もに、近年の電子機器における小型化、低ピッチ化、高
密度化の要求が従来の製造方法より容易に対応できる。
As described above, according to the present invention, a plurality of small elements having the same structure are positioned and overlapped on a small element to form a three-dimensional structure, thereby securing an area for forming one element. In addition to this, an array-type multilayer inductor for multiple lines can be obtained, a magnetic circuit can be made effective, and the demand for miniaturization, low pitch, and high density in electronic devices in recent years is easier than conventional manufacturing methods. Can respond to.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1実施例によるアレイ型積層チップ
インダクタ分解斜視図である。
FIG. 1 is an exploded perspective view of an array type multilayer chip inductor according to a first embodiment of the present invention.

【図2】図1のアレイ型積層チップインダクタの外観斜
視図である。
FIG. 2 is an external perspective view of the array-type multilayer chip inductor of FIG.

【符号の説明】[Explanation of symbols]

1,1′磁性体板 2,5,6,7,8 導電パターン 2a,5a,6a,7a,8a 始端部分 2b,5b,6b,7b,8b 終端部分 2c,8c 導電パターン露出部分 3 磁性体層 4 切り欠き窓 9 外部端子 10 インダクタ素子 11 小素子 1,1 'magnetic plate 2,5,6,7,8 conductive pattern 2a, 5a, 6a, 7a, 8a start end 2b, 5b, 6b, 7b, 8b end 2c, 8c conductive pattern exposed portion 3 magnetic material Layer 4 Notch window 9 External terminal 10 Inductor element 11 Small element

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 一対の第1の磁性体板及び第2の磁性体
板と、これらの間に面の所定部分に切り欠き窓が形成さ
れたN(Nは1以上の整数)個の磁性体層を有し、最下
層の前記磁性体板上に渦帯状の第1の導電パターンを印
刷法により積層し、前記渦帯状の導電パターンの終端部
分に前記切り欠き窓を一致させるように第1番目の前記
磁性体層を印刷法により積層し、その上から第2の渦帯
状の導電パターンを、その始端部分が前記切り欠き窓を
介して前記終端部分に接続されるように、印刷法により
前記第1番目の磁性体層に積層し、以後上記した方法に
より順々に積層していき、第N番目の磁性体層上に第
(N+1)の渦帯状の導電パターンを積層した後、前記
第2の磁性体板を圧着して小素子を形成し、該小素子を
複数個積層して形成されたことを特徴とする積層型イン
ダクタ。
An N number (N is an integer of 1 or more) of a pair of a first magnetic plate and a second magnetic plate, and a cutout window formed in a predetermined portion of a surface between the first magnetic plate and the second magnetic plate. A first conductive pattern in the form of a spiral band is laminated on the lowermost magnetic plate by a printing method, and the cutout window is aligned with the terminal portion of the conductive pattern in the spiral band. A first magnetic material layer is laminated by a printing method, and a second spiral conductive pattern is formed on the first magnetic material layer by a printing method so that a start end portion is connected to the end portion through the cutout window. After that, after laminating on the first magnetic layer, and sequentially laminating by the above-mentioned method, after laminating the (N + 1) th spiral band conductive pattern on the Nth magnetic layer, A small element is formed by pressing the second magnetic plate, and a plurality of the small elements are laminated. A multilayer inductor characterized by the following.
【請求項2】 前記第1の磁性体板と密着する導電パタ
ーンの始端部分と前記第2の磁性体板に密着する導電パ
ターンの終端部分とがともに前記磁性体板の縁辺に露出
するように形成され、該露出部分が外部電極に接続され
ていることを特徴とする請求項1記載の積層型インダク
タ。
2. A method according to claim 1, wherein a starting portion of the conductive pattern that is in close contact with the first magnetic plate and an ending portion of the conductive pattern that is in close contact with the second magnetic plate are both exposed to the edge of the magnetic plate. The multilayer inductor according to claim 1, wherein the exposed portion is formed and connected to an external electrode.
JP26337899A 1999-09-17 1999-09-17 Laminated inductor Pending JP2001085231A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26337899A JP2001085231A (en) 1999-09-17 1999-09-17 Laminated inductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26337899A JP2001085231A (en) 1999-09-17 1999-09-17 Laminated inductor

Publications (1)

Publication Number Publication Date
JP2001085231A true JP2001085231A (en) 2001-03-30

Family

ID=17388667

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26337899A Pending JP2001085231A (en) 1999-09-17 1999-09-17 Laminated inductor

Country Status (1)

Country Link
JP (1) JP2001085231A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1307662C (en) * 2002-10-01 2007-03-28 株式会社Ceratech Stach coil device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1307662C (en) * 2002-10-01 2007-03-28 株式会社Ceratech Stach coil device and manufacturing method thereof

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