US20040187303A1 - Selective plating using dual lift-off mask - Google Patents
Selective plating using dual lift-off mask Download PDFInfo
- Publication number
- US20040187303A1 US20040187303A1 US10/249,305 US24930503A US2004187303A1 US 20040187303 A1 US20040187303 A1 US 20040187303A1 US 24930503 A US24930503 A US 24930503A US 2004187303 A1 US2004187303 A1 US 2004187303A1
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- path
- tape
- layer
- seeded
- plating
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- 238000007747 plating Methods 0.000 title claims abstract description 58
- 230000009977 dual effect Effects 0.000 title description 3
- 239000000758 substrate Substances 0.000 claims abstract description 116
- 238000000034 method Methods 0.000 claims abstract description 44
- 238000001465 metallisation Methods 0.000 claims abstract description 18
- 230000008439 repair process Effects 0.000 claims description 80
- 230000002950 deficient Effects 0.000 claims description 27
- 239000002253 acid Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 239000000853 adhesive Substances 0.000 claims description 5
- 230000001070 adhesive effect Effects 0.000 claims description 5
- 229920006267 polyester film Polymers 0.000 claims description 4
- 239000011800 void material Substances 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 2
- 238000011049 filling Methods 0.000 claims description 2
- 239000011810 insulating material Substances 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims description 2
- 230000008020 evaporation Effects 0.000 claims 1
- 238000001704 evaporation Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 69
- 238000005272 metallurgy Methods 0.000 description 28
- 239000004020 conductor Substances 0.000 description 18
- 239000002184 metal Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 230000008569 process Effects 0.000 description 10
- 239000000919 ceramic Substances 0.000 description 9
- 230000001681 protective effect Effects 0.000 description 8
- 239000010409 thin film Substances 0.000 description 7
- 238000009713 electroplating Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000011065 in-situ storage Methods 0.000 description 4
- 238000000608 laser ablation Methods 0.000 description 4
- 238000010899 nucleation Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004100 electronic packaging Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002537 cosmetic Substances 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 239000012153 distilled water Substances 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011152 fibreglass Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 210000000707 wrist Anatomy 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
- H05K3/242—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/225—Correcting or repairing of printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0191—Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0264—Peeling insulating layer, e.g. foil, or separating mask
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0562—Details of resist
- H05K2203/0574—Stacked resist layers used for different processes
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
- H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
- H05K3/046—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer
- H05K3/048—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer using a lift-off resist pattern or a release layer pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
- H05K3/182—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method
- H05K3/184—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating characterised by the patterning method using masks
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49158—Manufacturing circuit on or in base with molding of insulated base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49163—Manufacturing circuit on or in base with sintering of base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
- Y10T29/49171—Assembling electrical component directly to terminal or elongated conductor with encapsulating
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
- Y10T29/49171—Assembling electrical component directly to terminal or elongated conductor with encapsulating
- Y10T29/49172—Assembling electrical component directly to terminal or elongated conductor with encapsulating by molding of insulating material
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49718—Repairing
- Y10T29/49721—Repairing with disassembling
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49718—Repairing
- Y10T29/49732—Repairing by attaching repair preform, e.g., remaking, restoring, or patching
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49718—Repairing
- Y10T29/49732—Repairing by attaching repair preform, e.g., remaking, restoring, or patching
- Y10T29/49734—Repairing by attaching repair preform, e.g., remaking, restoring, or patching and removing damaged material
- Y10T29/49737—Metallurgically attaching preform
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49718—Repairing
- Y10T29/49746—Repairing by applying fluent material, e.g., coating, casting
Definitions
- the present invention is directed to electronic packaging in general, and specifically, a method to form additional surface plating metallization on post-fired MLC substrates.
- the present invention has been developed as an alternative to current thin-films repair approaches currently used in the electronic packaging industry.
- the present invention is also an alternative to the related application referenced above, where a laser beam is used to form a trench on a lapped substrate defining the path of a desired repair conductor from an isolated defective net via to an alternate repair net via.
- a seed layer is sputtered or evaporated, covering at least a portion of the surface of the substrate and subsequently the bottom and sides of the laser formed trench.
- the trench is then completely filled by either continued sputtering of the desired metallurgy, or alternately, electroplated.
- the substrate is then lapped and polished to remove the metallurgy on the surface of the substrate exposing just the repair conductor metallurgy in the now filled trench.
- a requirement of the related process is that the substrate must be planarized.
- the present invention addresses a means to repair an electrical conductor on a non-planar substrate without the above difficulties.
- a dual in-situ lift-off mask is disclosed as a means to post-fire personalize Multi-Layer Ceramic (MLC) substrates.
- the disclosed method can be used as a means to form additional Top Surface Metallization (TSM) wiring used for Engineering Changes (EC's) or repair of internal wiring defects on planar and non-planar substrates.
- TSM Top Surface Metallization
- EC's Engineering Changes
- This process has been developed as an alternative to the thin-film repair approach currently used in the manufacture of MLC substrates.
- a method to form surface plating metallization on a substrate comprising the steps of: providing a substrate having a top surface and a bottom surface and a plurality of conductive vias providing electrical connections between the top and bottom surface and between top surface vias; applying a first layer of tape on the top surface; applying a second layer of tape on the first layer of tape; creating a first path through both the first layer of tape and the second layer of tape, to expose a portion of the top surface, the first path contacting at least one conductive via on the top surface; creating a second path through the second layer of tape to expose a portion of the first layer of tape and intersecting with the first path wherein the second path is connected from the first path to an edge of the substrate; depositing a seed layer over the surface of the second layer of tape to create a seeded plating path in the first path and a sacrificial seeded conduction path in the second path intersecting with the seeded plating path;
- the method may further comprise the steps of: applying a third layer of tape over the sacrificial seeded conduction path prior to plating such that only the ends of said sacrificial seeded conduction path are exposed to prevent the bulk of the sacrificial seeded conduction path from plating.
- the first and second paths are formed by laser ablation.
- the laser power may also be increased such that the laser ablation also forms a trench in the top surface of the substrate coinciding with the first path.
- the present invention also provides a method to repair a defective electrical connection in a substrate comprising the steps of: providing a substrate having a top surface and a bottom surface and a plurality of conductive vias providing electrical connections between the top and bottom surface; applying a first layer of tape on the top surface; applying a second layer of tape on the first layer of tape; laser ablating an opening in both the first and second tape layers over a defective via; etching the defective via to create a void to a desired depth; filling the void with an insulating material to electrically isolate the defective via; laser ablating a first path through both the first layer of tape and the second layer of tape to expose a portion of the top surface, the first path connecting the isolated defective via to a repair via on the top surface; laser ablating a second path through the second layer of tape to expose a portion of the first layer of tape and intersecting with the first path wherein the second path is routed from the first path to an edge of the substrate; depositing a seed layer over the surface
- the present invention also provides a surface plating metallization structure comprising:substrate having a top surface and a bottom surface and a plurality of conductive vias providing electrical connections between said top and bottom surface; a first layer of tape on the top surface; a second layer of tape on the first layer of tape; a first path through both the first layer of tape and the second layer of tape exposing a portion of the top surface, the first path contacting at least one conductive via on the top surface; a second path through the second layer of tape exposing a portion of the first layer of tape and intersecting with the first path wherein the second path is connected from the first path to an edge of the substrate; and a seeded plating path in the first path and a sacrificial seeded conduction path in the second path and on the surface of the first layer of tape.
- the surface plating metallization structure may further comprise a third layer of tape over the sacrificial seeded conduction path such that only the ends of the sacrificial seeded conduction path are exposed to prevent the bulk of the sacrificial seeded conduction path from plating.
- FIG. 1 is an enlarge, partial cross-sectional view of a substrate illustrating laser ablation of a repair path.
- FIG. 2 is an enlarged, partial cross-sectional view of a substrate illustrating the deposition of a seed layer in the repair path.
- FIG. 3 is an enlarged, partial cross-sectional view of a substrate illustrating the deposition of conductive metal in the repair path.
- FIG. 4 is an enlarged, partial cross-sectional view of a substrate illustrating the removal of excess metal from the polished surface of the substrate.
- FIG. 5 is an enlarged, partial cross-sectional view of a substrate illustrating the deposition of conductive metal through a lift-off mask on the surface of the substrate.
- FIG. 6 is an enlarged, partial cross-sectional view of a substrate illustrating the application of a bottom and top lift-off mask on the surface of the substrate.
- FIG. 7 is an enlarged, partial cross-sectional view of a substrate illustrating laser ablation over a defective net via.
- FIG. 8 is an enlarged, partial cross-sectional view of a substrate illustrating via passivation.
- FIG. 9 is an enlarged, partial cross-sectional view of a substrate illustrating a repair path.
- FIG. 10 is an exploded isometric view illustrating the formation of a second path in the top lift-off mask.
- FIG. 11 is an exploded isometric view illustrating the deposition of seed metallurgy.
- FIG. 12 is an exploded isometric view illustrating the removal of the of the top lift-off mask.
- Typical MLC substrates contain electrical wiring which interconnection the top and bottom of the substrate as well as providing electrical interconnections between top surface vias.
- This electrical interconnection typically consists of vertical columns of conductive metal commonly referred to as “vias”. Horizontal conductive lines or nets in turn connect to the vias.
- the disclosed method can be used as a means to aid in the formation of additional top surface metal “TSM” wiring or engineering changes “EC's” or repair of internal wiring on both planar and non-planar substrates.
- the present invention is a low-cost alternative method to form repair or EC structures on a substrate using a pattern formed by a laser in at least two removable and disposable tape masks.
- a pattern formed by a laser in at least two removable and disposable tape masks.
- the tape mask serves to protect the substrate surface during handling and processing resulting in reduced risk of damage.
- a first embodiment of the current invention is applicable where it is desired to repair a defective net on a substrate.
- Two layers of commercially available protective tape are applied over the entire top surface of the substrate.
- the tape used is a transparent polyester film with a rubber adhesive having a total thickness of 0.0014 inches (#336 manufactured by 3M).
- This tape is water resistant and is also resistant to a variety of chemicals such as nitric acid.
- the tape has a very low-tack adhesive and has a high temperature stability. It can also be cleanly and completely ablated by a laser beam, making it ideally suited to this application.
- the tape currently used is a transparent polyester film with a rubber adhesive of total thickness of 0.0014 inch (#336 manufactured by 3M), any suitable tape or removable coating may be used.
- a tightly focused UV laser beam is first used to ablate both layers of tape over the via connected to the defective net.
- the fourth harmonic of a Nd-YAG laser with a wavelength of 0.266 ⁇ m was used.
- the fluence of the laser is adjusted so that it ablates the tape but does not affect the underlying ceramic substrate or metallurgy.
- An acid solution is subsequently applied to the ablated area over the via, dissolving a portion of the metallurgy to below the surface.
- An electrically insulating material may then be applied to the removed via to ensure electrical isolation of the defective net if desired.
- the laser beam is then again used to ablate a path completely through both of the tape layers from this now isolated via to a good repair net via through which metal can be deposited.
- the laser fluence is then reduced such that it takes several passes to ablate fully through a layer of tape.
- a second path is then formed in only the top layer of tape so that it is fully removed and only partially formed in the lower layer. This path is routed from an arbitrary point along the repair path to a portion of the edge of the substrate. Seed metallurgy is then sputtered or evaporated over the surface of the top mask and into the openings formed by the laser.
- the upper layer of tape is now removed resulting in a seeded repair path and a sacrificial seeded conduction path which is used for connecting the repair path to the electroplating potential. If desired, an additional new piece of tape can be applied over this sacrificial line leaving just its ends exposed, preventing the bulk of the line length from plating-up.
- the substrate is now electroplated by connecting the end of the sacrificial conductor, routed to the edge of the substrate, to the plating potential, immersing the substrate in a plating solution, and applying current through the sacrificial seeded conduction path. The current, typically micro-amps, is conducted through this path through the sputtered seed layer to the repair path wherein only the repair path will plate-up.
- the second path is formed only on the surface of the first layer of tape and could be of very thin dimensions, and may optionally be covered by an additional layer of tape to prevent plating, only a small area of this line will plate up.
- This allows the first layer of tape to easily be removed, along with the sacrificial conductor, without pulling the desired repair metallurgy off of the repair site.
- the resulting repair conductor can then be further processed (i.e., electrical passivation or gold plated) as desired to complete the repair.
- a second embodiment of the present invention involves the above process without the acid etching of vias to form an EC wire.
- a third embodiment of the present invention involves the above process where after acid etching of the defective net via, the laser fluence is increased so that as the tape is ablated over the desired path, a portion of the underlying ceramic is also removed to form a trench in the ceramic substrate surface.
- Metallization and tape mask removal can then be done in the same manner as in the first embodiment.
- Forming a trench in the surface of the substrate allows the new metallization to be thicker without increasing its height above the surface of the substrate, ensuring adequate conductance of the metal line while maintaining low line height.
- Forming a trench also allows for planarization of the substrate following metallization if desired whereby the upper surface of the metal conductor after planarization is flush with the substrate surface.
- the sacrificial conductor line is connected to a repair net via and after seeding, is completely over-coated with an additional layer of protective tape.
- the repair net via would then be connected to the plating potential through the preexisting internal wiring within the substrate to provide a conductive path during plate-up. This would prevent any portion of the sacrificial conductor line to plate-up at the repair site, reducing even further any likelihood of the repair conductor being pulled out of the repair site during tape lift-off.
- a laser beam 10 is used to form a trench 20 on the surface 25 of a substrate 30 .
- This trench 20 defines the path of a desired repair conductor from a defective net 40 and defective net via 45 to an alternate repair net 46 and repair net via 47 .
- the trench is approximately 40 ⁇ m in width and approximately 18 ⁇ m in depth.
- a seed layer 50 shown in FIG. 2, is evaporated or preferably sputtered, covering at least a portion of the surface of the substrate and subsequently the bottom and sides of the laser formed trench 20 .
- This seed layer provides adhesion of the repair metallurgy to the repair path side-walls as well as an electrically conductive path to the edge of the substrate 30 for connection to the plating potential required for subsequent electroplating steps.
- the trench 20 is then completely filled by either continued sputtering of the desired metallurgy, or preferably, electroplated as shown in FIG. 3.
- the added metallurgy 60 is formed on at least a portion of the surface of the substrate 30 as well as in the laser formed trench 20 , at the full thickness required to fill the trench, thus, the substrate 30 must be lapped and polished to remove the undesired metallurgy residing on the surface of the polished substrate 26 to expose and isolate just the repair conductor metallurgy 65 in the now filled trench as shown in FIG. 4.
- the requirement, however, that the substrate be planarized (lapped and/or polished) presents several required, but potentially damaging and costly process steps, and introduces other defects on the surface of the substrate which must be addressed.
- FIG. 5 An example is illustrated in FIG. 5.
- a lift-off mask 70 consisting of a protective adhesive tape is placed on the surface of the substrate 30 .
- a laser beam is used to form an opening through the lift-off mask and a corresponding trench 20 on the surface 25 of the substrate 30 .
- the trench 20 through the protective tape 70 and into the surface of the substrate, defines the path of a desired repair conductor from an isolated defective net via 45 to an alternate repair net via 47 .
- the lift-off mask 70 is left in place when the substrate 30 is seeded and plated. This allows the trench to be filled with the conductor metallurgy 60 without plating the remaining surface of the substrate.
- the lift-off mask 70 is now completely covered by a thick layer of sputtered, evaporated or preferably electroplated metal 60 and subsequently will be fully attached to the repair path metallurgy by the full thickness of the metal.
- This causes removal of the lift-off mask 70 to be extremely difficult and/or impossible without damaging or removing the desired repair conductor metallurgy. It is therefore desirable to have a method to remove the lift-off mask 70 following just the seeding operation, but the seeding metallurgy 50 serves as the conductive path from the repair site to the edge of the substrate where the connection for the electroplating operation must be made.
- the current invention addresses a means to provide a repair conductor on a non-planar substrate without the above difficulties.
- FIG. 6 there is shown a cross sectional view of a defective net 80 connected to a defective net via 85 , a repair net 90 connected to a repair net via 95 , both contained within a MLC substrate 30 .
- Two layers of a protective adhesive tape consisting of a bottom layer lift-off mask 100 and a top layer lift-off mask 110 are placed on top of the substrate 30 . These layers of tape form a bottom and top lift-off mask respectively.
- a tightly focused laser beam preferably an ultraviolet laser beam having a wavelength of 0.266 ⁇ m, is used to ablate an opening 120 , typically a circular opening, in both layers of tape 100 , 110 over the defective net via 85 connected to the defective net 80 .
- the fluence (energy per unit area) of the laser is adjusted so that it ablates the tape 100 , 10 but does not affect the underlying ceramic substrate 30 or metallurgy.
- Suitable laser parameters in a preferred embodiment used a power of 0.01 mW at 1 KHz and approximately 200 nano-second pulse widths.
- the diameter of the hole 120 in the lift-off mask is preferably larger than the via 85 to allow an etchant solution to reach the via metallurgy. For a via diameter of approximately 0.004 inches the diameter is preferably about 0.010 inches.
- the etchant is an acid solution.
- An example is an acid solution of approximately 50% nitric acid.
- the etchant is then applied to the ablated area over the defective net via 85 , dissolving a portion of the via metallurgy to below the surface of the ceramic 30 .
- a typical etch depth is approximately 60 ⁇ m deep.
- the etchant is completely rinsed, preferably with distilled or de-ionized water, and passivation material 130 is deposited in the etched via 85 to ensure electrical isolation of the defective net 80 as shown in FIG. 8.
- the laser beam is again used to ablate a path completely through both tape layers 100 , 110 from the now electrically isolated defective net via 85 to an electrically good repair net via 95 .
- This path provides a repair path 140 on the surface of the substrate through which metal will be sputtered or otherwise deposited to create a repair.
- the laser fluence is then reduced such that the laser beam only removes a single layer of protective tape 110 .
- Suitable laser parameters in a preferred embodiment used a power of 0.02 mW at 1 KHz and approximately 200 nano-second pulse widths.
- This can be done in a single pass or in several passes to ablate only through the top layer of tape 110 to form a second path 150 .
- the second path 150 is formed so that the top tape layer 110 is fully removed exposing the bottom layer of tape 100 .
- This second path 150 is routed from at least one arbitrary point along the desired repair path 140 to a portion of the edge of the substrate 30 and preferably to a pad area 160 where contact will be made for electroplating the repair path 140 .
- seed metallurgy 170 is then sputtered or evaporated over the surface of the top mask 110 and into the openings formed by the laser.
- the seed metallurgy goes into the second path on top of layer 100 , and also into the repair path 140 on the substrate surface.
- the upper layer of tape 110 can now be removed as shown in FIG. 12, resulting in a seeded repair path 141 on the surface of the substrate 30 and a sacrificial seeded conduction path 180 which is used for connecting the seeded repair path 141 to the electroplating potential which is supplied to the pad area 160 .
- the sacrificial seeded conduction path 180 is formed so that its width is narrow (typically 10-25% of the repair metallurgy width) in relation to the width of the repair or if desired, an optional new piece of tape 190 can be applied over this sacrificial line leaving just its ends exposed, preventing the bulk of the line length from plating-up.
- the part can now be electroplated in a plating solution by connecting the end of the sacrificial conduction path 180 at the pad area 160 to the plating potential.
- the current typically micro amps
- the current is conducted through this path 180 through the sputtered seed layer 170 to the repair path 140 wherein only the repair path 140 and whatever exposed sacrificial seeded conduction path will plate-up.
- the sacrificial seeded conduction path 180 is formed only on the surface of the first layer of tape 100 and can be of very narrow width, or be optionally covered by an additional layer of tape 190 to prevent plating, only the small exposed area of this sacrificial line will plate up along with the repair path area.
- the small cross sectional area of this line allows for easy separation of the first layer of tape 100 with its sacrificial seeded repair path without pulling or otherwise damaging the desired repair metallurgy on the repair site. It is also beneficial, that the plated area be limited to only the exposed seeded area and not the entire top surface of the substrate as shown in the prior art. This reduces the quantity of costly plating solution consumed in the electroplating step.
- the resulting repair conductor can then be further processed (i.e., passivated, heat treated, or gold plated) as desired to complete the repair.
- passivated, heat treated, or gold plated i.e., passivated, heat treated, or gold plated
- a laser has been used as a preferred method for creating the apertures in the protective tape
- other methods such as reactive ion etching through a mask, engraving, cutting, sand blasting etc., can be used where applicable.
- the above process is performed without the acid etching of vias to form an EC wire.
- the laser fluence is increased (suitable laser parameters in a preferred embodiment used a power of 0.14 mW at 1 KHz and approximately 200 nano-second pulse widths) so that as the tape is ablated over the desired repair path, and a portion of the underlying ceramic is also removed to form a trench below the surface of the ceramic.
- Metallization and mask removal can then be done in the same manner as in the first embodiment. Forming a trench in the surface of the substrate allows the new metallization to be thicker without increasing its height above the surface of the substrate, ensuring adequate conductance of the metal line while maintaining low line height.
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Abstract
Description
- This application is related to subject matter described and claimed in U.S. patent application attorney docket no. FIS9-2003-0001 entitled Electronic Package Repair Process, both by the inventors of the instant application and filed on Feb. 4, 2003.
- The present invention is directed to electronic packaging in general, and specifically, a method to form additional surface plating metallization on post-fired MLC substrates.
- The present invention has been developed as an alternative to current thin-films repair approaches currently used in the electronic packaging industry. The present invention is also an alternative to the related application referenced above, where a laser beam is used to form a trench on a lapped substrate defining the path of a desired repair conductor from an isolated defective net via to an alternate repair net via. Once the trench is formed, a seed layer is sputtered or evaporated, covering at least a portion of the surface of the substrate and subsequently the bottom and sides of the laser formed trench. The trench is then completely filled by either continued sputtering of the desired metallurgy, or alternately, electroplated. The substrate is then lapped and polished to remove the metallurgy on the surface of the substrate exposing just the repair conductor metallurgy in the now filled trench.
- A requirement of the related process is that the substrate must be planarized.
- This presents several necessary process steps and may introduce other defects which must be addressed. Attempts to create a repair path by using a lift-off mask on non-planar substrates have been unsuccessful. In these methods, a lift-off mask would be placed on the substrate and the laser trench formed through it to expose the substrate surface. The lift-off mask would be left in place when the substrate is seeded and the trench filled with the conductor metallurgy. The lift-off mask, which must now be removed, is completely covered and is fully attached to the repair metallurgy. Removal is now difficult and may introduce undesirable defects to the repair area.
- The present invention addresses a means to repair an electrical conductor on a non-planar substrate without the above difficulties. A dual in-situ lift-off mask is disclosed as a means to post-fire personalize Multi-Layer Ceramic (MLC) substrates. The disclosed method can be used as a means to form additional Top Surface Metallization (TSM) wiring used for Engineering Changes (EC's) or repair of internal wiring defects on planar and non-planar substrates. This process has been developed as an alternative to the thin-film repair approach currently used in the manufacture of MLC substrates.
- These and other purposes of the present invention will become more apparent after referring to the following description considered in conjunction with the accompanying drawings.
- The purposes and advantages of the present invention have been achieved by providing a method to form surface plating metallization on a substrate comprising the steps of: providing a substrate having a top surface and a bottom surface and a plurality of conductive vias providing electrical connections between the top and bottom surface and between top surface vias; applying a first layer of tape on the top surface; applying a second layer of tape on the first layer of tape; creating a first path through both the first layer of tape and the second layer of tape, to expose a portion of the top surface, the first path contacting at least one conductive via on the top surface; creating a second path through the second layer of tape to expose a portion of the first layer of tape and intersecting with the first path wherein the second path is connected from the first path to an edge of the substrate; depositing a seed layer over the surface of the second layer of tape to create a seeded plating path in the first path and a sacrificial seeded conduction path in the second path intersecting with the seeded plating path; removing the second layer of tape while maintaining a seeded plating path in the first path and a sacrificial seeded conduction path on the surface of the first layer of tape; connecting the sacrificial seeded conduction path to a plating potential at the edge of the substrate; immersing the substrate in a plating solution and applying current through the sacrificial seeded conduction path to plate the seeded plating path; and removing the first layer of tape to remove the sacrificial seeded conduction path and uncovering a selectively plated substrate surface.
- The method may further comprise the steps of: applying a third layer of tape over the sacrificial seeded conduction path prior to plating such that only the ends of said sacrificial seeded conduction path are exposed to prevent the bulk of the sacrificial seeded conduction path from plating.
- In a preferred embodiment the first and second paths are formed by laser ablation. The laser power may also be increased such that the laser ablation also forms a trench in the top surface of the substrate coinciding with the first path.
- The present invention also provides a method to repair a defective electrical connection in a substrate comprising the steps of: providing a substrate having a top surface and a bottom surface and a plurality of conductive vias providing electrical connections between the top and bottom surface; applying a first layer of tape on the top surface; applying a second layer of tape on the first layer of tape; laser ablating an opening in both the first and second tape layers over a defective via; etching the defective via to create a void to a desired depth; filling the void with an insulating material to electrically isolate the defective via; laser ablating a first path through both the first layer of tape and the second layer of tape to expose a portion of the top surface, the first path connecting the isolated defective via to a repair via on the top surface; laser ablating a second path through the second layer of tape to expose a portion of the first layer of tape and intersecting with the first path wherein the second path is routed from the first path to an edge of the substrate; depositing a seed layer over the surface of the second layer of tape to create a seeded plating path in the first path and a sacrificial seeded conduction path in the second path intersecting with the seeded plating path; removing the second layer of tape while maintaining a seeded plating path in the first path and a sacrificial seeded conduction path on the surface of the first layer of tape; connecting the sacrificial seeded conduction path to a plating potential at the edge of the substrate; immersing the substrate in a plating solution and applying current through the sacrificial seeded conduction path to plate the seeded plating path; and removing the first layer of tape to remove the sacrificial seeded conduction path and uncovering a selectively plated repair path on the substrate surface.
- The present invention also provides a surface plating metallization structure comprising:substrate having a top surface and a bottom surface and a plurality of conductive vias providing electrical connections between said top and bottom surface; a first layer of tape on the top surface; a second layer of tape on the first layer of tape; a first path through both the first layer of tape and the second layer of tape exposing a portion of the top surface, the first path contacting at least one conductive via on the top surface; a second path through the second layer of tape exposing a portion of the first layer of tape and intersecting with the first path wherein the second path is connected from the first path to an edge of the substrate; and a seeded plating path in the first path and a sacrificial seeded conduction path in the second path and on the surface of the first layer of tape.
- The surface plating metallization structure may further comprise a third layer of tape over the sacrificial seeded conduction path such that only the ends of the sacrificial seeded conduction path are exposed to prevent the bulk of the sacrificial seeded conduction path from plating.
- The features of the invention believed to be novel and the elements characteristic of the invention are set forth with particularity in the appended claims. The Figures are for illustration purposes only and are not drawn to scale. The invention itself, however, both as to organization and method of operation, may best be understood by reference to the detailed descriptions which follows taken in conjunction with the accompanying drawings in which:
- FIG. 1 is an enlarge, partial cross-sectional view of a substrate illustrating laser ablation of a repair path.
- FIG. 2 is an enlarged, partial cross-sectional view of a substrate illustrating the deposition of a seed layer in the repair path.
- FIG. 3 is an enlarged, partial cross-sectional view of a substrate illustrating the deposition of conductive metal in the repair path.
- FIG. 4 is an enlarged, partial cross-sectional view of a substrate illustrating the removal of excess metal from the polished surface of the substrate.
- FIG. 5 is an enlarged, partial cross-sectional view of a substrate illustrating the deposition of conductive metal through a lift-off mask on the surface of the substrate.
- FIG. 6 is an enlarged, partial cross-sectional view of a substrate illustrating the application of a bottom and top lift-off mask on the surface of the substrate.
- FIG. 7 is an enlarged, partial cross-sectional view of a substrate illustrating laser ablation over a defective net via.
- FIG. 8 is an enlarged, partial cross-sectional view of a substrate illustrating via passivation.
- FIG. 9 is an enlarged, partial cross-sectional view of a substrate illustrating a repair path.
- FIG. 10 is an exploded isometric view illustrating the formation of a second path in the top lift-off mask.
- FIG. 11 is an exploded isometric view illustrating the deposition of seed metallurgy.
- FIG. 12 is an exploded isometric view illustrating the removal of the of the top lift-off mask.
- The purposes of the present invention have been achieved by providing, according to the present invention, a dual in-situ mask as a means to post-fire personalize an MLC substrate. Typical MLC substrates contain electrical wiring which interconnection the top and bottom of the substrate as well as providing electrical interconnections between top surface vias. This electrical interconnection typically consists of vertical columns of conductive metal commonly referred to as “vias”. Horizontal conductive lines or nets in turn connect to the vias. The disclosed method can be used as a means to aid in the formation of additional top surface metal “TSM” wiring or engineering changes “EC's” or repair of internal wiring on both planar and non-planar substrates.
- Conventional repair technology currently used on MLC substrates is accomplished primarily by means of thin-film repair processes. These are primarily photo processes which can only be performed on substrates which already possess thin film wiring on the top surface of the substrate or substrates which can have the thin films added for repair reasons. Thin film processes are very costly, involving numerous expensive and complicated tools and processes to accomplish a repair.
- The present invention is a low-cost alternative method to form repair or EC structures on a substrate using a pattern formed by a laser in at least two removable and disposable tape masks. By using an in-situ mask formed by a laser, most of the expensive tools and processes normally applied to form a thin-film repair (such as applying a photo resist, expose, develop, strip, etc.) can be eliminated, thereby reducing the cost and time consuming process steps. Additionally, the tape mask serves to protect the substrate surface during handling and processing resulting in reduced risk of damage.
- A first embodiment of the current invention is applicable where it is desired to repair a defective net on a substrate. Two layers of commercially available protective tape are applied over the entire top surface of the substrate. Although it is only necessary to cover the top of the substrate, it may be advantageous to cover the bottom surface with a layer of tape as a protective means. In a preferred embodiment the tape used is a transparent polyester film with a rubber adhesive having a total thickness of 0.0014 inches (#336 manufactured by 3M). This tape is water resistant and is also resistant to a variety of chemicals such as nitric acid. The tape has a very low-tack adhesive and has a high temperature stability. It can also be cleanly and completely ablated by a laser beam, making it ideally suited to this application. Although the tape currently used is a transparent polyester film with a rubber adhesive of total thickness of 0.0014 inch (#336 manufactured by 3M), any suitable tape or removable coating may be used.
- A tightly focused UV laser beam is first used to ablate both layers of tape over the via connected to the defective net. In a preferred embodiment the fourth harmonic of a Nd-YAG laser with a wavelength of 0.266 μm was used. The fluence of the laser is adjusted so that it ablates the tape but does not affect the underlying ceramic substrate or metallurgy. An acid solution is subsequently applied to the ablated area over the via, dissolving a portion of the metallurgy to below the surface. An electrically insulating material may then be applied to the removed via to ensure electrical isolation of the defective net if desired.
- The laser beam is then again used to ablate a path completely through both of the tape layers from this now isolated via to a good repair net via through which metal can be deposited. The laser fluence is then reduced such that it takes several passes to ablate fully through a layer of tape. A second path is then formed in only the top layer of tape so that it is fully removed and only partially formed in the lower layer. This path is routed from an arbitrary point along the repair path to a portion of the edge of the substrate. Seed metallurgy is then sputtered or evaporated over the surface of the top mask and into the openings formed by the laser.
- The upper layer of tape is now removed resulting in a seeded repair path and a sacrificial seeded conduction path which is used for connecting the repair path to the electroplating potential. If desired, an additional new piece of tape can be applied over this sacrificial line leaving just its ends exposed, preventing the bulk of the line length from plating-up. The substrate is now electroplated by connecting the end of the sacrificial conductor, routed to the edge of the substrate, to the plating potential, immersing the substrate in a plating solution, and applying current through the sacrificial seeded conduction path. The current, typically micro-amps, is conducted through this path through the sputtered seed layer to the repair path wherein only the repair path will plate-up.
- Since the second path is formed only on the surface of the first layer of tape and could be of very thin dimensions, and may optionally be covered by an additional layer of tape to prevent plating, only a small area of this line will plate up. This allows the first layer of tape to easily be removed, along with the sacrificial conductor, without pulling the desired repair metallurgy off of the repair site. The resulting repair conductor can then be further processed (i.e., electrical passivation or gold plated) as desired to complete the repair.
- A second embodiment of the present invention involves the above process without the acid etching of vias to form an EC wire. A third embodiment of the present invention involves the above process where after acid etching of the defective net via, the laser fluence is increased so that as the tape is ablated over the desired path, a portion of the underlying ceramic is also removed to form a trench in the ceramic substrate surface. Metallization and tape mask removal can then be done in the same manner as in the first embodiment. Forming a trench in the surface of the substrate allows the new metallization to be thicker without increasing its height above the surface of the substrate, ensuring adequate conductance of the metal line while maintaining low line height. Forming a trench also allows for planarization of the substrate following metallization if desired whereby the upper surface of the metal conductor after planarization is flush with the substrate surface.
- In a fourth embodiment of the present invention, the sacrificial conductor line is connected to a repair net via and after seeding, is completely over-coated with an additional layer of protective tape. The repair net via would then be connected to the plating potential through the preexisting internal wiring within the substrate to provide a conductive path during plate-up. This would prevent any portion of the sacrificial conductor line to plate-up at the repair site, reducing even further any likelihood of the repair conductor being pulled out of the repair site during tape lift-off.
- The above described embodiments will now be described in more detail with reference to the accompanying figures. Referring to FIG. 1, a
laser beam 10 is used to form atrench 20 on thesurface 25 of asubstrate 30. Thistrench 20 defines the path of a desired repair conductor from adefective net 40 and defective net via 45 to analternate repair net 46 and repair net via 47. In a preferred embodiment the trench is approximately 40 μm in width and approximately 18 μm in depth. Once thetrench 20 is formed, aseed layer 50, shown in FIG. 2, is evaporated or preferably sputtered, covering at least a portion of the surface of the substrate and subsequently the bottom and sides of the laser formedtrench 20. This seed layer provides adhesion of the repair metallurgy to the repair path side-walls as well as an electrically conductive path to the edge of thesubstrate 30 for connection to the plating potential required for subsequent electroplating steps. - The
trench 20 is then completely filled by either continued sputtering of the desired metallurgy, or preferably, electroplated as shown in FIG. 3. The addedmetallurgy 60 is formed on at least a portion of the surface of thesubstrate 30 as well as in the laser formedtrench 20, at the full thickness required to fill the trench, thus, thesubstrate 30 must be lapped and polished to remove the undesired metallurgy residing on the surface of the polished substrate 26to expose and isolate just the repair conductor metallurgy 65 in the now filled trench as shown in FIG. 4. The requirement, however, that the substrate be planarized (lapped and/or polished) presents several required, but potentially damaging and costly process steps, and introduces other defects on the surface of the substrate which must be addressed. - Attempts to create repairs on non-planar substrates by using an in-situ lift-off mask have been unsuccessful. An example is illustrated in FIG. 5. A lift-off
mask 70 consisting of a protective adhesive tape is placed on the surface of thesubstrate 30. A laser beam is used to form an opening through the lift-off mask and a correspondingtrench 20 on thesurface 25 of thesubstrate 30. As above, thetrench 20, through theprotective tape 70 and into the surface of the substrate, defines the path of a desired repair conductor from an isolated defective net via 45 to an alternate repair net via 47. The lift-offmask 70 is left in place when thesubstrate 30 is seeded and plated. This allows the trench to be filled with theconductor metallurgy 60 without plating the remaining surface of the substrate. - Consequently, the lift-off
mask 70 is now completely covered by a thick layer of sputtered, evaporated or preferably electroplatedmetal 60 and subsequently will be fully attached to the repair path metallurgy by the full thickness of the metal. This causes removal of the lift-offmask 70 to be extremely difficult and/or impossible without damaging or removing the desired repair conductor metallurgy. It is therefore desirable to have a method to remove the lift-offmask 70 following just the seeding operation, but the seedingmetallurgy 50 serves as the conductive path from the repair site to the edge of the substrate where the connection for the electroplating operation must be made. - The current invention addresses a means to provide a repair conductor on a non-planar substrate without the above difficulties. Referring to FIG. 6 there is shown a cross sectional view of a defective net80 connected to a defective net via 85, a
repair net 90 connected to a repair net via 95, both contained within aMLC substrate 30. Two layers of a protective adhesive tape consisting of a bottom layer lift-offmask 100 and a top layer lift-offmask 110 are placed on top of thesubstrate 30. These layers of tape form a bottom and top lift-off mask respectively. - Referring now to FIG. 7, a tightly focused laser beam, preferably an ultraviolet laser beam having a wavelength of 0.266 μm, is used to ablate an
opening 120, typically a circular opening, in both layers oftape defective net 80. The fluence (energy per unit area) of the laser is adjusted so that it ablates thetape ceramic substrate 30 or metallurgy. Suitable laser parameters in a preferred embodiment used a power of 0.01 mW at 1 KHz and approximately 200 nano-second pulse widths. The diameter of thehole 120 in the lift-off mask is preferably larger than the via 85 to allow an etchant solution to reach the via metallurgy. For a via diameter of approximately 0.004 inches the diameter is preferably about 0.010 inches. - In a preferred embodiment the etchant is an acid solution. An example is an acid solution of approximately 50% nitric acid. The etchant is then applied to the ablated area over the defective net via85, dissolving a portion of the via metallurgy to below the surface of the ceramic 30. As an example, a typical etch depth is approximately 60 μm deep. The etchant is completely rinsed, preferably with distilled or de-ionized water, and
passivation material 130 is deposited in the etched via 85 to ensure electrical isolation of the defective net 80 as shown in FIG. 8. - The laser beam is again used to ablate a path completely through both tape layers100, 110 from the now electrically isolated defective net via 85 to an electrically good repair net via 95. This path, as shown in FIG. 9, provides a
repair path 140 on the surface of the substrate through which metal will be sputtered or otherwise deposited to create a repair. - Referring now to the exploded isometric view shown in FIG. 10, the laser fluence is then reduced such that the laser beam only removes a single layer of
protective tape 110. (Suitable laser parameters in a preferred embodiment used a power of 0.02 mW at 1 KHz and approximately 200 nano-second pulse widths.) This can be done in a single pass or in several passes to ablate only through the top layer oftape 110 to form asecond path 150. Thesecond path 150 is formed so that thetop tape layer 110 is fully removed exposing the bottom layer oftape 100. Thissecond path 150 is routed from at least one arbitrary point along the desiredrepair path 140 to a portion of the edge of thesubstrate 30 and preferably to apad area 160 where contact will be made for electroplating therepair path 140. - Referring now to FIG. 11,
seed metallurgy 170 is then sputtered or evaporated over the surface of thetop mask 110 and into the openings formed by the laser. The seed metallurgy goes into the second path on top oflayer 100, and also into therepair path 140 on the substrate surface. At this point, the upper layer oftape 110 can now be removed as shown in FIG. 12, resulting in aseeded repair path 141 on the surface of thesubstrate 30 and a sacrificialseeded conduction path 180 which is used for connecting theseeded repair path 141 to the electroplating potential which is supplied to thepad area 160. The sacrificialseeded conduction path 180 is formed so that its width is narrow (typically 10-25% of the repair metallurgy width) in relation to the width of the repair or if desired, an optional new piece oftape 190 can be applied over this sacrificial line leaving just its ends exposed, preventing the bulk of the line length from plating-up. - The part can now be electroplated in a plating solution by connecting the end of the
sacrificial conduction path 180 at thepad area 160 to the plating potential. The current (typically micro amps) is conducted through thispath 180 through the sputteredseed layer 170 to therepair path 140 wherein only therepair path 140 and whatever exposed sacrificial seeded conduction path will plate-up. - Since the sacrificial
seeded conduction path 180 is formed only on the surface of the first layer oftape 100 and can be of very narrow width, or be optionally covered by an additional layer oftape 190 to prevent plating, only the small exposed area of this sacrificial line will plate up along with the repair path area. The small cross sectional area of this line allows for easy separation of the first layer oftape 100 with its sacrificial seeded repair path without pulling or otherwise damaging the desired repair metallurgy on the repair site. It is also beneficial, that the plated area be limited to only the exposed seeded area and not the entire top surface of the substrate as shown in the prior art. This reduces the quantity of costly plating solution consumed in the electroplating step. - The resulting repair conductor can then be further processed (i.e., passivated, heat treated, or gold plated) as desired to complete the repair. Although a laser has been used as a preferred method for creating the apertures in the protective tape, other methods such as reactive ion etching through a mask, engraving, cutting, sand blasting etc., can be used where applicable.
- In a second embodiment of the present invention, the above process is performed without the acid etching of vias to form an EC wire. In a third embodiment of the present invention, after acid etching the defective net via, the laser fluence is increased (suitable laser parameters in a preferred embodiment used a power of 0.14 mW at 1 KHz and approximately 200 nano-second pulse widths) so that as the tape is ablated over the desired repair path, and a portion of the underlying ceramic is also removed to form a trench below the surface of the ceramic. Metallization and mask removal can then be done in the same manner as in the first embodiment. Forming a trench in the surface of the substrate allows the new metallization to be thicker without increasing its height above the surface of the substrate, ensuring adequate conductance of the metal line while maintaining low line height.
- While the preferred embodiments described above relate to electrical repair/EC metallurgy on ceramic substrates, this technique can also be utilized on any of a variety of substrates such as plastic, fiberglass, glass, stone, etc. The above processes can also be used for cosmetic purposes, for example, placing logo's, initials, inscriptions, or decorations on items such as on the surface of eyeglasses, wrist and pocket watches, picture frames, or any item where fine metallurgy would be applied to a surface. It should also be known that although the preferred embodiments allow the utilization for repair of non-planarized substrates, the knowledge can also be easily applied to substrates which are planarized, and in some instances can present a significant cost savings over alternate methods.
- It will be apparent to those skilled in the art having regard to this disclosure that other modifications of this invention beyond those embodiments specifically described here may be made without departing from the spirit of the invention. Accordingly, such modifications are considered within the scope of the invention as limited solely by the appended claims.
Claims (22)
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US20110033977A1 (en) * | 2009-08-06 | 2011-02-10 | Maxim Integrated Products, Inc. | Method of forming solderable side-surface terminals of quad no-lead frame (qfn) integrated circuit packages |
WO2013169636A1 (en) * | 2012-05-08 | 2013-11-14 | Cree, Inc. | Light emitting diode (led) contact structures and process for fabricating the same |
CN114729466A (en) * | 2019-11-27 | 2022-07-08 | 朗姆研究公司 | Edge removal for through resist plating |
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US20060289966A1 (en) * | 2005-06-22 | 2006-12-28 | Dani Ashay A | Silicon wafer with non-soluble protective coating |
WO2007142747A2 (en) * | 2006-04-21 | 2007-12-13 | Sifco Selective Plating | Selective plating system |
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