JP3003422B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a field of manufacturing a semiconductor device using a plating method and a laser irradiation method.

[0002]

2. Description of the Related Art A conventional semiconductor device and its manufacturing method will be described with reference to the accompanying drawings. 19 to 23
3A to 3C are cross-sectional views illustrating a conventional method of manufacturing a semiconductor device in the order of steps.

As shown in FIG. 19, first, about 0.5 to 1.
A first insulating film 43 made of a silicon oxide film having a thickness of 0 μm is formed on a semiconductor substrate 41 by a thermal CVD method. Further, an interlayer connection hole 44 having a diameter of about 0.5 to 1.5 μm is formed in the first insulating film 43 by a reactive ion etching method using a resist as a mask. Next, the diffusion layer 42 is formed on the surface of the semiconductor substrate 41 by ion implantation using the first insulating film 43 as a mask.

[0004] Next, as shown in FIG.
A first conductive film layer 45 made of a titanium-tungsten alloy obtained by adding 10% by weight of titanium to tungsten on the top 3 and inside the interlayer connection hole 44 by a DC magnetron sputtering method at a film forming power of 1.0 to 2.0 kW and a film forming pressure. 2 to 10m
Under a condition of Torr, it is formed to a thickness of about 0.1 μm.

Further, a second conductive film layer 46 made of, for example, gold is formed on the entire surface of the first conductive film layer 45 by using a method similar to the method of forming the first conductive film layer 45 to have a film forming power of 1 μm. .
Under the conditions of 0 to 2.0 kW and a deposition pressure of 2 to 10 mTorr,
It is formed to a thickness of about 0.02 to 0.05 μm.

The first conductive layer 45 is formed by a first conductive layer 45 formed in a later step.
Although provided as a layer for preventing the constituent elements of the low resistance metal film 48 and the second conductive film layer 46 from diffusing into the active region, the first low resistance metal film 48 and the first conductive layer
It also functions as a layer that makes close contact with the insulating film.

The second conductive film layer 46 comprises a first low resistance metal film 48
Current supply at the time of growth, stable growth of the plating film, ensuring adhesion between the first low-resistance metal film 48 and the first conductive film layer 45, and a plating solution on the surface of the first conductive film layer 45. It is formed for the purpose of protection from

Next, as shown in FIG. 21, a photolithography method using a g-line or an i-line is performed to about 1.0 to 2.0.
A first mask film 47 made of a photoresist having a thickness of μm is patterned on the second conductive film layer 46.

Further, a first low-resistance metal film 48 made of gold is selectively formed on the exposed second conductive film layer 46 to a thickness of about 0.5 to 1.5 μm by using a usual electrolytic plating method. . At this time, if the interlayer connection hole 44 is fine, if the aspect ratio is large, or if the hole shape is bad, the first
A void (cavity) 56 is formed in the low resistance metal film 48. The electrolytic gold plating solution is mainly composed of sulfuric acid, sodium gold sulfate, etc., to which a flattening agent, a pH stabilizer and the like are added. This plating solution is usually 1
It is non-cyan containing about 10 g of gold per liter and has a near neutral pH (6-8). The gold plating is preferably performed at a plating temperature of 35 to 60 ° C. and a current density of 1 to 4 mA / cm ² from the viewpoint of the quality and uniformity of the plating film.

Next, as shown in FIG. 22, the first mask film 47 is removed by a wet stripping method using an organic solvent or an ashing method using oxygen plasma. Further, the second conductive film layer 46 is etched using the first low-resistance metal film 48 as an etching mask, and then the first conductive film layer 45 is also etched to form a wiring pattern. For example, when the first conductive film layer 45 is made of a titanium-tungsten alloy and the second conductive film layer 46 is made of gold, and these are removed by a wet etching method, the gold is made of aqua regia having a concentration of 10 to 20% by volume. Etching is performed at a temperature of 25 to 50 ° C., and the titanium-tungsten alloy is preferably etched at a temperature of 25 to 45 ° C. using a hydrogen peroxide solution having a concentration of 50 to 100% by volume.

If the second conductive film layer 46 is to be removed by dry etching, an unnecessary portion of the second conductive film layer 46 is removed by ion milling using Ar gas as a milling source, and the first conductive film layer 45 is removed by CF ₄ or SF. It can also be removed by a reactive ion etching method using a fluorine-based gas such as ₆ .

It is also possible to remove the second conductive film layer 46 by wet etching and the first conductive film layer 45 by dry etching.

Next, as shown in FIG. 23, a second insulating film 53 made of a silicon nitride film is formed on the entire surface by a plasma CVD method using SiH ₄ and NH ₃ as reaction gases.
It is formed with a thickness of 0.5 to 1.0 μm.

Through the above steps, a diffusion layer 42, a first insulating film 43, a first conductive film layer 45, a second conductive film layer 46, a first low-resistance metal film 48, and a second insulating film 53 are formed on the semiconductor substrate 41. I do.

[0015]

However, in the above-described conventional method for manufacturing a semiconductor device, when the integration of the semiconductor device is advanced and the diameter of the interlayer connection hole 44 is reduced, the conventional electrolytic plating method is used. When the first low-resistance metal film 48 is formed, a void (void) 5 is formed in the interlayer connection hole 46.
6 is formed, and there is a problem that the defect rate increases due to the influence of the residue in the cavity 56 and the yield in the manufacturing process increases.

Furthermore, even after the product is completed, the residue in the voids and the existence of the voids themselves tend to cause characteristic fluctuations and disconnection due to electromigration and stress migration at interlayer connection parts.
There is a problem that the long-term reliability of the semiconductor device is reduced.

When the first low-resistance metal film 48 is an element having a high corrosiveness, corrosion tends to occur, which also causes a problem that the long-term reliability of the semiconductor device is reduced.

The present invention has been made in view of the above problems, and has high long-term reliability, good electric characteristics, a reduced defect rate, and a high yield. and to provide a manufacturing method of a semiconductor equipment.

[0019]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming an insulating film on a semiconductor substrate;
Diffusion layer formed on board surface or wiring layer on semiconductor substrate
To obtain a structure in which interlayer connection holes are formed at positions that match
The first step is to form a barrier metal on the inner surface of the interlayer connection hole.
A step of forming a conductive film layer, and a step of forming a film on the first conductive film layer;
A step of forming a second conductive film layer to be a base film;
On the second conductive film layer existing inside and around the via hole
Forming a first mask film in which only the first mask film is exposed;
By plating using the first mask film as a plating mask,
Selectively forming the first low-resistance metal film on the exposed second conductive film layer
Forming the first mask film and removing the first mask film.
And irradiates a laser beam to melt the first low-resistance metal film
Flow to fill the first low-resistance metal film inside the interlayer connection hole.
Filling the first and second conductive layers on the insulating film.
Removing a film layer, the first low-resistance metal film and the
Forming a third conductive film layer serving as a barrier metal on the insulating film;
And a fourth step of forming a plating base film on the third conductive film layer.
Forming a conductive film layer and selecting on the fourth conductive film layer
Forming a second mask film for wiring formation;
By plating the second mask film as a plating mask
Selectively forming a second low-resistance metal film on the exposed fourth conductive film layer
And removing the second mask film
Using the second low-resistance metal film as a mask,
An unnecessary portion of the fourth conductive film layer is selectively removed to remove the third and fourth conductive layers.
And a fourth conductive film layer and a second low-resistance metal film.
Forming a line, and forming a second insulating film on the wiring
And a step of

[0020]

[0021]

According to a method of manufacturing a semiconductor device according to the present invention, a first low-resistance metal film having a predetermined thickness is formed on the inner surface of an interlayer connection hole in which a second conductive film layer is formed. The resistance metal film is melted by laser irradiation. Since the first low-resistance metal film is formed to a predetermined thickness, a void is formed by closing the upper portion of the interlayer connection hole before laser irradiation,
Reflow cannot be prevented, and the lower layer is not adversely affected by laser heat. Therefore, even if the first low-resistance metal film includes a void when the first low-resistance metal film is formed, the first low-resistance metal film melts and flows by laser irradiation to float the void, and as a first low-resistance metal film containing no void. The inside of the interlayer connection hole is filled. Thus, the first low-resistance metal film containing no voids therein can be formed in the fine interlayer connection hole. Thus, the first conductive film layer and the third conductive film, which are high-melting-point conductive layers, are formed under the first low-resistance metal film and the second low-resistance metal film, each of which has a small electric resistance, such as gold or copper. Since each layer exists, low interlayer connection resistance, high electromigration, and high stress migration resistance can be obtained not only in the wiring portion but also in the interlayer connection portion.

In the semiconductor device according to the present invention, a first low resistance material is formed by forming a predetermined thickness on the inner surface of the interlayer connection hole in which the second conductive film layer is formed, and then melting by laser to fill the inside of the interlayer connection hole. It has a metal film. Therefore, as described above, the first low-resistance metal film does not include voids therein, and can obtain low interlayer connection resistance and high electromigration and stress migration not only in the wiring portion but also in the interlayer connection portion. .

Further, since the first low-resistance metal film has a structure in which the periphery is covered with the first conductive film layer and the third conductive film layer, which are high-melting-point metals, the plating solution or the like in another step may enter. And can be prevented from corroding for a long time. Further, since the first conductive film layer and the third conductive film layer are protected, the reaction hardly proceeds. This makes it possible to use metals that have low electrical resistance but are difficult to use because of their high corrosivity, and that metals that have low electrical resistance but high reactivity are difficult to use. can do.

[0024]

Next, embodiments of the present invention will be specifically described with reference to the accompanying drawings.

FIGS. 1 to 9 are sectional views showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps.
FIG. 3 is a plan view showing one step of the method of the present embodiment. As shown in FIG. 1, a first insulating film 3 made of a silicon oxide film having a thickness of about 0.5 to 1.0 μm is formed by heat CV of a SiH ₄ source.
It is formed on a semiconductor substrate by the D method. Further, an interlayer connection hole 4 having a diameter of about 0.5 to 1.5 μm is formed by a reactive ion etching method using a resist as a mask. Next, the diffusion layer 2 is formed on the surface of the semiconductor substrate 1 by ion implantation using the first insulating film 3 as a mask.

Next, as shown in FIG. 2, a first conductive film layer 5 composed of a titanium-tungsten alloy obtained by adding 10% by weight of titanium to tungsten is formed with a film forming power of 1.0 to 1.0 by a normal DC magnetron sputtering method. Under a condition of 2.0 kW and a film forming pressure of 1 to 10 mTorr, a film is formed over the entire surface to a thickness of about 0.1 μm.

Further, a second conductive film layer 6 made of, for example, gold is formed on the first conductive film layer 5 by a method similar to the method of forming the first conductive film layer 5 with a film forming power of 0.2 to 1.0 kw. Under a condition of a film forming pressure of 2 to 10 mTorr, about 0.02 to 0.
It is formed to a thickness of 05 μm. The first conductive film layer 5 functions as a diffusion prevention film (barrier metal) for the constituent elements of the first low-resistance metal film 8 formed in a later step, and serves as a barrier between the first low-resistance metal film 8 and the first insulating film 3. It functions as an adhesion layer between them.

The second conductive film layer 6 serves as a base (plating current supply layer) at the time of plating, and promotes stable growth at the time of forming the first low-resistance metal film 8 formed by plating in a later step. It is formed for the purpose of ensuring the adhesion of the resistance metal film 8 and protecting the surface of the first conductive film layer 5 from the plating solution.

Next, as shown in FIG. 3, a first mask film 7 made of a photoresist is formed on the second conductive film layer 6 by a photolithography method using a known g-line or i-line. Is patterned to a thickness of about 1.0 to 2.0 μm. The first mask film 7 has a pattern in which the interlayer connection hole 4 and the second conductive film layer 6 only in the peripheral portion thereof are exposed, and is used for forming a wiring pattern for connecting elements of the semiconductor device. Different from mask.

Further, the first mask film 7 on the second conductive film layer 6
The first low-resistance metal film 8 made of gold is applied to a region not covered with the metal by about 0.2 to 0.6 by a usual electrolytic gold plating method.
It is formed with a thickness of μm in the inner surface of the interlayer connection hole 4 and the region where the second conductive film layer 6 is exposed. At this time, the plating current is supplied through the first conductive film layer 5 and the second conductive film layer 6 existing below. It is desirable that the thickness of the first low-resistance metal film 8 be about １ ／ of the diameter of the interlayer connection hole 4. This is because if the first low-resistance metal film 8 is formed with a thickness larger than that, voids may be formed inside the interlayer connection hole 4 before laser reflow in a later step, and the reflow may not be performed properly. The electrolytic gold plating solution contains sulfuric acid, sodium gold sulfate or the like as a main component, to which a flattening agent, a pH stabilizer and the like are added. This plating solution is a non-cyan type plating solution usually containing about 10 g of gold per liter, and has a pH near neutral (6 to 8). Also, the plating operation should be performed at the plating temperature from the viewpoint of the quality and uniformity of the plating film.
It is preferable to carry out under the conditions of 35 to 60 ° C. and current density of 1 to 4 mA / cm ² .

In FIG. 10, the section taken along the line AA in FIG.
This corresponds to the longitudinal section shown in FIG. In FIG. 10, the appropriate margin from the edge of the interlayer connection hole 4 to the end of the first mask film 7 indicated by L is the diameter of the interlayer connection hole 4, the aspect ratio, and the film of the first low-resistance metal film to be formed later. Although it depends on the thickness, basically a value of about １ ／ of the interlayer connection hole 4 is used as a guide.

Next, as shown in FIG. 4, after removing the first mask film 7 by an ashing method using oxygen plasma or a wet stripping method using an organic solvent, an excimer having a wavelength of 308 nm using XeCl as a light source. The laser is pulsed. Thereby, the first low-resistance metal film 8 melts and flows and fills the inside of the interlayer connection hole 4. Irradiation conditions such as the pulse interval and pulse energy density of the irradiation need to be changed depending on the reflectivity, the film thickness, the buried depth of the first low-resistance metal film 8, and the pulse interval is usually several to several tens of nanoseconds.
And the pulse energy density is about 0.2 to 1.0 J / cm ²
It is preferable that In addition, when irradiation is performed with excessive energy, care must be taken because the supplied heat may destroy the pn junction existing in the lower layer. First
At the interface between the low resistance metal film 8 and the second conductive film layer 6, a reaction layer of both is formed, but no structural difference occurs before and after laser irradiation.

Next, as shown in FIG. 5, the exposed second conductive film layer 6 is removed with aqua regia, and then the first conductive film layer 5 is cleaned with a fluorine-based gas such as CF ₄ and SF _6. Anisotropic etching is performed by a reactive ion etching method to be used and removed.

Next, as shown in FIG. 6, a third conductive film layer 9 made of a titanium-tungsten alloy is formed by a DC magnetron sputtering method with a film forming power of 1.0 to 2.0 K.
W, about 0.05 μm under the conditions of film formation pressure of 1 to 10 mTorr
The entire surface is formed to a thickness of. Further, the fourth conductive film layer 10 made of gold is formed with a film forming power of 0.2 to
A film having a thickness of about 0.02 to 0.05 μm is formed on the third conductive film layer 9 under the conditions of 1.0 KW and a film forming pressure of 2 to 10 mTorr.

Next, as shown in FIG. 7, a second mask film 11 made of a photoresist is formed on the fourth conductive film layer 10 by a photolithography method using a g-line or an i-line for about 1.0 to 2.0. Pattern with a thickness of μm.
This mask film is for forming a wiring pattern for connecting the elements of the semiconductor device. The first mask film 7 for filling the first low-resistance metal film 8 into the interlayer connection holes 4 used in the previous step is formed. Are different.

Further, since the second mask film is not formed and the fourth
The second low-resistance metal film 12 made of gold is applied to a region where the conductive film layer 10 is exposed by a usual electrolytic gold plating method.
It is formed with a thickness of 0.5 to 1.5 μm.

Next, as shown in FIG. 8, the second mask film 11 is removed by an ashing method using oxygen plasma and a peeling method using an organic solvent. Next, unnecessary portions of the fourth conductive film layer 10 and unnecessary portions of the third conductive film layer 9 are sequentially removed by a wet etching method using the second low-resistance metal film 12 as an etching mask to form a wiring pattern.

The third conductive film layer 9 is made of a titanium-tungsten alloy, and the fourth conductive film layer 10 is made of gold. When these are removed by a wet etching method, the gold of the fourth conductive film layer 10 is 10 to 20 vol%.
Etching is performed at a temperature of 25 to 50 ° C. using aqua regia, and the titanium-tungsten alloy of the third conductive layer 9 is 50 to 100 V
Etching is performed at a temperature of 25 to 45 ° C. using ol% hydrogen peroxide solution. Thereby, a favorable wiring shape with less side etching can be obtained. Since the second low-resistance metal film 12 is slightly etched in this etching step, the thickness at the time of film formation needs to be determined in consideration of the reduction of the film. The wet etching method has no ion attack on the second low-resistance metal film 12,
There is an advantage that surface damage can be suppressed as compared with the dry etching method.

Next, as shown in FIG. 9, SiH ₄ on the entire surface
And a second insulating film 13 formed of a silicon oxide film by plasma CVD using N ₂ O.
It is formed with a thickness of 1.0 μm.

The semiconductor device formed by the above-described process has a thickness of about ３ of the diameter of the interlayer connection hole 4 formed on the second conductive film 6 inside the interlayer connection hole 4 by electrolytic gold plating. (1) forming a first low-resistance metal film 8;
Is melted by laser irradiation. By setting the first low-resistance metal film 8 to a predetermined thickness, a void is formed by closing the upper part of the interlayer connection hole 4 before laser irradiation,
Reflow cannot be prevented, and the lower layer is not adversely affected by laser heat. Furthermore, even if a void is generated, the entire area of the first low-resistance metal film 8 is melted by a laser heat source in a later step, and the void can be raised. Therefore, the molten metal flows and causes defects such as voids to float, whereby the first low-resistance metal film 8 not included in the voids or the like can be formed inside the fine interlayer connection hole. As a result, the first conductive film layer 5 and the third conductive film 5, which are conductive layers having a high melting point, are formed under the first low-resistance metal film 8 and the second low-resistance metal film 12 having low electric resistance typified by gold and copper. Since the conductive film layers 9 are respectively provided, low interlayer connection resistance, high electromigration, and high stress migration resistance can be obtained not only in the wiring portion but also in the interlayer connection portion.

Further, since the first low-resistance metal film 8 has a structure in which the periphery is covered with the metal layers of the second conductive film layer 6 and the third conductive film layer 9, a plating solution or the like in another process enters. Can be prevented, and is not easily corroded for a long time. Further, since the metal layer protects the silicon-based oxide film and the nitride film, the reaction hardly proceeds.

As a result, a fine semiconductor device having higher long-term reliability and better electrical characteristics than the conventional semiconductor device can be stably obtained by a manufacturing process with a higher yield than before.

FIGS. 11 to 18 are sectional views showing a method of manufacturing a semiconductor device according to a second embodiment of the present invention in the order of steps.

First, as shown in FIG.
0.50 by thermal CVD using SiH ₄ as a reaction gas.
A first insulating film 23 having a thickness of μm is formed. On the first insulating film 23, titanium having a thickness of about 0.05 μm and about 0.1 μm
barrier metal layer 34 made of μm titanium nitride
a is selectively formed. The barrier metal layer 34
A sputtered gold film 34b having a thickness of about 0.02 to 0.05 μm is formed on a. Further, a gold plating film 34c having a thickness of about 0.8 to 1.1 μm is formed on the sputtered gold film 34b. As a result, the lower wiring 34 composed of the barrier metal layer 34a, the sputtered gold film 34b, and the gold plating film 34c can be formed. A second insulating film 33 made of a silicon oxide film having a thickness of about 0.5 to 1.0 μm is formed on the gold plating film 34c and the first insulating film 23 by a plasma CVD method using SiH ₄ gas and N ₂ O gas. . Further, the second insulating film is partially opened on the gold plating film 34c by using a reactive ion etching method to remove the second insulating film, and the second insulating film is opened to form an interlayer connection hole having a diameter of about 0.5 to 1.0 μm. 24 are formed. This barrier metal layer 34
The titanium of a is formed by a DC magnetron sputtering method using argon as a sputtering gas as a target,
Titanium nitride can be formed by a reactive sputtering method using a mixed gas of nitrogen and argon as a sputtering gas.

The sputtered gold film 34b can be formed by DC magnetron sputtering under the conditions of a film forming power of 0.2 to 1.0 KW and a film forming pressure of 2 to 10 mTorr. The plated gold film 34c is formed by the electrolytic gold plating method using a photoresist as shown in the first embodiment, and the wiring pattern is formed by the etching technique shown in the first embodiment.

Next, as shown in FIG. 12, a first conductive film layer 25 composed of a two-layer film of titanium and titanium nitride is formed.
Titanium is formed on the entire surface with a thickness of about 0.05 μm and titanium nitride with a thickness of about 0.1 μm. Further, on the first conductive film layer 25,
For example, the second conductive film layer 26 made of copper is formed to a thickness of about 0.02 to 0.05 μm by DC magnetron sputtering. The first conductive film layer 25 functions as a diffusion preventing film below the constituent elements of the first low-resistance metal film 28 formed in a later step, and furthermore, the first low-resistance metal film 28 and the second insulating film 33 Acts as an adhesion layer between the layers.

Further, the second conductive film layer 26 functions as a plating current supply layer at the time of plating to promote stable growth at the time of forming the first low-resistance metal film 28, and furthermore, is formed around the first low-resistance metal film. To protect the first low-resistance metal film 28 from the plating solution on the surface of the first conductive film layer 25.

Next, a first mask film 27 made of a photoresist is formed on the second conductive film layer 26 by a photolithography method using a g-line or an i-line by about 1.0 to 2.0.
Pattern with a thickness of μm. This first mask film 27
Similarly to the first embodiment, the second conductive film layer has a pattern such that only the interlayer connection hole 24 and the second conductive film layer 26 in the peripheral portion thereof are exposed.

Further, a first low-resistance metal film 28 made of copper by electrolytic plating is applied to the inside of the interlayer connection hole 24 and the region on the second conductive film layer 26 where the first mask film 27 is not formed. To have a thickness of about 0.4 μm. In this electrolytic plating step, the uniformity of the copper film to be deposited is important, so the plating solution contains copper sulfate, metallic copper and sulfuric acid, respectively, at 60 to 100, 15 to 25, and 170 to 220 g / l. It is easy to obtain high uniformity of plating film thickness,
A material containing a small amount of chlorine and additives such as a leveling agent is used. In addition, the temperature of the plating operation is 20-30 ° C.
And under a condition of a current density of 1 to 3 mA / cm ² . Thereby, a flat and highly uniform copper film can be formed.

Next, as shown in FIG. 13, the first mask film 27 is removed using oxygen plasma or an organic solvent.
Further, the first low-resistance metal film 28 is pulse-irradiated with an excimer laser having a wavelength of 308 nm using XeCl as a light source. As a result, the first low-resistance metal film 28 melts and flows and fills the inside of the interlayer connection hole 24. Irradiation conditions such as an irradiation pulse interval and a pulse energy density are determined by the first low-resistance metal film 28.
Need to be changed depending on the reflectance, film thickness, burying depth, and the like. For example, the pulse interval is about several to several tens of nanoseconds, and the pulse energy density is about 0.2 to 1.0 J / cm ² . When the excimer laser is irradiated with excessive energy, the lower wiring 34 is melted or cracks occur in the second insulating film 33 due to the supplied heat.

Next, as shown in FIG. 14, the exposed second conductive film layer 26 is removed by a reactive ion etching method using a chlorine-based gas such as CCl ₄ and BCl _3. The first conductive film layer 23 is also etched back by a reactive ion etching method using a chlorine-based gas to expose the second insulating film 33.

Next, as shown in FIG. 15, a third conductive film layer 29 made of titanium nitride is formed on the entire surface by a reactive sputtering method to a thickness of about 0.05 to 0.1 μm. Further, a fourth conductive film layer 30 made of gold is formed on the third conductive film layer 29 to a thickness of about 0.02 to 0.05 μm by a sputtering method. Further, a second mask film 31 made of a photoresist is formed on the fourth conductive film layer 30 by a photolithography method using a g-line or an i-line by about 1.0 to 2.0.
Pattern with a thickness of μm. This second mask film 31
Is for forming a wiring pattern for connecting elements of a semiconductor device, unlike the first mask film 27.

Next, as shown in FIG. 16, a region on the fourth conductive film layer 30 where the second mask film 31 is not formed,
A second low-resistance metal film 32 made of gold is formed to a thickness of about 0.5 to 1.5 μm by electrolytic gold plating. Further, the second mask film 31 is removed by an ashing method using oxygen plasma and a peeling method using an organic solvent.

Next, as shown in FIG. 17, unnecessary portions of the fourth conductive film layer 30 and unnecessary portions of the third conductive film layer 29 are sequentially removed using the second low-resistance metal film 32 as an etching mask to form a wiring pattern. Become The third conductive film layer 29 is made of titanium nitride, can be removed by a reactive ion etching method using a chlorine-based gas such as CCl ₄ and BCl _3, and is made of gold. Is
It can be removed by etching by Ar ion milling. Further, in this etching step, the second low-resistance metal film 32 is slightly etched, so that the thickness of the second low-resistance metal film 32 at the time of film formation is determined in consideration of the film reduction.

Next, as shown in FIG.
₄ and N third insulating film 35 of about 0.5 to 1.0 comprised of silicon oxide film by plasma CVD that uses ₂ O
It is formed with a thickness of μm.

The semiconductor device manufactured by the method of this embodiment is similar to that of the first embodiment in that the second
The interlayer connection hole 2 is formed on the conductive film layer 26 by electrolytic gold plating.
The first low-resistance metal film 28 is formed to have a thickness of about の of the diameter of No. 4, and the first low-resistance metal film 28 is melted by laser irradiation, so that defects such as voids are floated. The first low resistance metal film 28 having no voids therein can be formed in the fine interlayer connection hole 24.

Thus, similarly to the first embodiment, low interlayer connection resistance can be obtained not only in the wiring portion but also in the interlayer connection portion.
High electromigration and high stress migration resistance can be obtained.

The first low-resistance metal film 28 is surrounded by a second
Since the structure is covered with the conductive film layer 26 and the third conductive film layer 29, it is possible to prevent the plating solution or the like in another process from invading, and it is possible to prevent corrosion for a long time and to have high corrosion resistance. ing.

Further, since the third conductive film layer and the fourth conductive film layer, which are the refractory metal film layers, also exist under the second low-resistance metal film 32 serving as the main conductive material, the wiring portion and the interlayer connection portion are provided. In both cases, a fine semiconductor device having higher long-term reliability as compared with the related art can be obtained.

As a result, a fine semiconductor device having higher long-term reliability and better electrical characteristics than the conventional semiconductor device can be stably obtained by a manufacturing process with a higher yield than before.

Incidentally, the layer formed on the surface of the semiconductor substrate 1 of the first embodiment is not limited to the above-mentioned diffusion layer, but also uses a metal silicide such as other crystalline silicon, titanium silicide or tungsten silicide. be able to.

The first and third conductive layers 5, 9, 25 and 29 in the first and second embodiments are not limited to the above-mentioned materials, that is, titanium-tungsten alloy, titanium and titanium.
In addition to the two-layer film of titanium and titanium nitride, for example, tungsten,
Titanium, molybdenum, zirconium, vanadium, Huff
And alloys containing these metals as main components
Silicon compounds, nitrogen compounds, boron compounds and
Single-layer film or carbon compound selected from the group consisting of
Has a two-layer film composed of titanium and titanium boride.
Ri, high melting point, can be used as long as the material can ensure the heat resistance and the base adhesion.

The second and fourth conductive layers 6, 10, 26 and 30 of the first and second embodiments are made of the above-mentioned materials other than gold and copper .
For example, palladium, platinum, osmium, iridium,
Rhodium, ruthenium, rhenium, titanium, or the like can be used. As a base for film growth at the time of forming the first low-resistance metal films 8 and 28, they are compatible with each other in terms of heat resistance, adhesion, plating property, and the like. If there is, it is not particularly limited.

Although the second conductive film layer 26 of the second embodiment is made of copper, it basically has heat resistance, adhesiveness and plating as a base for film growth when the first low resistance metal film 28 is formed. From the viewpoint of the properties and the like, the compatibility is good, the copper plating film formed in a later step can be deposited, and the heat treatment does not deteriorate the electrical properties of copper and the heat resistance as a barrier metal of the first conductive film layer. Can be used.

The first and second mask films 7, 11, 27, 31 of the first and second embodiments are not limited to the above-mentioned materials, but may be polyimide organic resin materials, silicon oxide films, Inorganic materials such as a nitride film and an oxynitride film can also be used.

The first low-resistance metal films 8 and 28 of the first and second embodiments are not limited to the above-mentioned materials, and can be formed on the second conductive film layers 6 and 26 by plating. As long as the metal is hard to adhere to the upper and lower insulating films, a metal having a lower electric resistance can be used.

Further, the removal of unnecessary portions of the third and fourth conductive layers 9, 10, 29 and 30 in the first and second embodiments is not limited to the above-mentioned wet etching method. Depending on the type and wiring width, a dry etching method can be used, or a method combining a dry etching method and a wet etching method can be used. For example, when the third and fourth conductive layers are elements having low chemical activity and difficult to remove by the wet etching method, such as platinum, a physical etching method using ion collision energy such as ion milling. Can be removed.

The removal of the third conductive film layers 9 and 29 by dry etching can be performed by reactive ion etching.
Further, removal of the fourth conductive layer 10, 30 can try the chlorine-based gas typified by fluorine-based gas or CCL ₄ and BCL ₃ or the like described above. However, the second low-resistance metal films 12 and 32 serving as a mask are also etched in the removing process by the dry etching method, so that the film thickness is reduced. Therefore, it is necessary to set the film thickness at the time of film formation in consideration of this film reduction.

The second insulating film 13 of the first embodiment and the third insulating film 35 of the second embodiment are not limited to the above-mentioned silicon oxide film, but may be, for example, PSG, BSG or BPSG. For example, an oxide film containing phosphorus or boron as typified by, for example, can be used. Alternatively, a silicon nitride film, a silicon oxynitride film, a polyimide resin-based organic film, or the like can be used. Its film formation method is plasma CV
The method is not limited to the method D, but may be another method such as a spin coating method represented by SOG (spin-on-glass) and a polyimide resin material. Further, it is also effective to combine an insulating film flattening process typified by an insulating film etch-back method using reactive ion etching.

The lower wiring 34 of the second embodiment is not particularly limited to gold, but may be an aluminum-based material.

Further, in the first and second embodiments, the laser source used to irradiate the first low-resistance metal films 8 and 28 is not limited to XeCl, but KrF or the like can be used. . However, since the wavelength and the like are different, the appropriate irradiation conditions are different from those in the case of XeCl and need to be examined again.

The semiconductor device and the method of manufacturing the same according to the present embodiment can be applied irrespective of the type of semiconductor integrated circuit such as a MOS transistor and a BIPOLAR transistor.

[0073]

As described above, according to the present invention, the first low-resistance metal film having low electric resistance is filled in the interlayer connection hole by melting with a laser. Further, the periphery of the first low-resistance metal film is covered with a second conductive film layer which is a high-melting-point metal film layer, and further, a lower layer of a low-resistance second low-resistance metal film serving as a main conductive material. Also, a fourth conductive film layer which is a refractory metal film layer is formed.

As a result, voidless embedding can be performed even in a small interlayer connection hole, and a structure having high electromigration and stress migration resistance can be obtained in both the wiring portion and the interlayer connection portion. Further, even when the first low-resistance metal film is a highly corrosive element, its surroundings are covered and protected, so that corrosion is unlikely to occur, making it possible to use an element that has been difficult to use conventionally. . Therefore, a fine semiconductor device having high long-term reliability and good electric characteristics can be obtained, and a high yield can be obtained by the method of manufacturing the semiconductor device.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one step in a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing another step of the embodiment method.

FIG. 3 is a sectional view showing another step of the embodiment.

FIG. 4 is a cross-sectional view showing another process of the embodiment method.

FIG. 5 is a cross-sectional view showing another process of the embodiment method.

FIG. 6 is a sectional view showing another step of the embodiment.

FIG. 7 is a sectional view showing another step of the embodiment method.

FIG. 8 is a sectional view showing another step of the embodiment method.

FIG. 9 is a sectional view showing another step of the embodiment method.

FIG. 10 is a plan view showing another step in the method of the embodiment.

FIG. 11 is a cross-sectional view showing one step in a method for manufacturing a semiconductor device according to a second example of the present invention.

[12] which is also a cross-sectional view showing another one step in the inventive method.

[13] which is also a cross-sectional view showing another one step in the inventive method.

[14] which is also a cross-sectional view showing another one step in the inventive method.

[15] which is also a cross-sectional view showing another one step in the inventive method.

[16] which is also a cross-sectional view showing another one step in the inventive method.

[17] which is also a cross-sectional view showing another one step in the inventive method.

[18] which is also a cross-sectional view showing another one step in the inventive method.

FIG. 19 is a cross-sectional view showing one step in a conventional semiconductor device manufacturing method.

FIG. 20 is a sectional view showing another step of the conventional method.

FIG. 21 is a sectional view showing another step of the conventional method.

FIG. 22 is a cross-sectional view showing another step of the conventional method.

FIG. 23 is a sectional view showing another step of the conventional method.

[Explanation of symbols]

 1, 21, 41; semiconductor substrates 2, 42; diffusion layers 3, 23, 43; first insulating films 4, 24, 44; interlayer connection holes 5.25.45; first conductive film layers 6, 26, 46; Second conductive film layers 7, 27, 47; first mask layers 8, 28, 48; first low-resistance metal films 9, 29; third conductive film layers 10, 30; fourth conductive film layers 11, 31; 2 mask layers 12, 32; second low resistance metal film 13, 33, 53; second insulating film 34a; barrier metal layer 34b; sputter layer 34c; plating layer 34; lower wiring 35; third insulating film 56;

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/28-21/288 H01L 21/3205-21/3213 H01L 21/768

Claims (6)

(57) [Claims] An insulating film on a semiconductor substrate includes a semiconductor substrate.
Diffusion layer formed on board surface or wiring layer on semiconductor substrate
To obtain a structure in which interlayer connection holes are formed at positions that match
The first step is to form a barrier metal on the inner surface of the interlayer connection hole.
A step of forming a conductive film layer, and a step of forming a film on the first conductive film layer;
A step of forming a second conductive film layer to be a base film;
On the second conductive film layer existing inside and around the via hole
Forming a first mask film in which only the first mask film is exposed;
By plating using the first mask film as a plating mask,
Selectively forming the first low-resistance metal film on the exposed second conductive film layer
Forming the first mask film and removing the first mask film.
And irradiates a laser beam to melt the first low-resistance metal film
Flow to fill the first low-resistance metal film inside the interlayer connection hole.
Filling the first and second conductive layers on the insulating film.
Removing a film layer, the first low-resistance metal film and the
Forming a third conductive film layer serving as a barrier metal on the insulating film;
And a fourth step of forming a plating base film on the third conductive film layer.
Forming a conductive film layer and selecting on the fourth conductive film layer
Forming a second mask film for wiring formation;
By plating the second mask film as a plating mask
Selectively forming a second low-resistance metal film on the exposed fourth conductive film layer
And removing the second mask film
Using the second low-resistance metal film as a mask,
An unnecessary portion of the fourth conductive film layer is selectively removed to remove the third and fourth conductive layers.
And a fourth conductive film layer and a second low-resistance metal film.
Forming a line, and forming a second insulating film on the wiring
The method of manufacturing a semiconductor device characterized by having a that step. 2. The method according to claim 1, wherein the laser irradiation is performed using XeCl or Kr.
3. The method according to claim 1, wherein a light source of F is used. 3. The method according to claim 1, wherein the laser irradiation uses an intermittent pulse irradiation method. 4. The first conductive film layer and the third conductive film layer,
Tungsten, titanium, molybdenum, zirconium, vanadium, hafnium, and alloys containing these metals as main components, silicon compounds of these metals, nitrogen compounds,
A single-layer film of a material selected from the group consisting of boron compounds and carbon compounds, a two-layer film composed of titanium and titanium nitride, or a two-layer film composed of titanium and titanium boride. 1
A method for manufacturing a semiconductor device . 5. The second conductive film layer and the fourth conductive film layer,
2. The semiconductor device according to claim 1, wherein the semiconductor device is formed of at least one element selected from the group consisting of gold, palladium, platinum, osmium, iridium, rhodium, ruthenium, rhenium, titanium and copper.
Manufacturing method of the device . Wherein said first low-resistance metal film and the second low-resistance metal film, method of manufacturing a semiconductor device according to claim 1, characterized in that a layer made of gold or copper.