US20040145505A1 - Current dac code independent switching - Google Patents
Current dac code independent switching Download PDFInfo
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- US20040145505A1 US20040145505A1 US10/351,066 US35106603A US2004145505A1 US 20040145505 A1 US20040145505 A1 US 20040145505A1 US 35106603 A US35106603 A US 35106603A US 2004145505 A1 US2004145505 A1 US 2004145505A1
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- signal
- data signal
- digital data
- current steering
- switching
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
- H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
- H03M1/0678—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components
- H03M1/068—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components the original and additional components or elements being complementary to each other, e.g. CMOS
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0836—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of phase error, e.g. jitter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/742—Simultaneous conversion using current sources as quantisation value generators
Definitions
- the current steering circuit contains multiple switching elements arranged so that a constant number of switching elements change conduction state with every cycle of the clocking signal.
- the current steering circuit may receive the digital data signal as a first input and an auxiliary data signal as a second input.
- the auxiliary data signal changes logic state when: (i) triggered by the clocking signal, and (ii) the digital data signal does not change logic state.
- FIG. 3A shows a current steering DAC according to one embodiment of the present invention.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
- Electronic Switches (AREA)
Abstract
Methods and devices for code independent switching in a digital-to-analog converter (DAC) are described. A synchronous digital circuit is triggered by a clocking signal and develops a digital data signal. A current steering circuit has a common source node for supplying current, and develops an analog output signal representative of the digital data signal. Any switching disturbances at the common source node are substantially data independent.
Description
- The invention generally relates to electronic signal processing, and more specifically, to digital to analog signal conversion.
- A current steering digital-to-analog converter (DAC) converts a digital data stream input into a corresponding analog signal output. FIG. 1 shows a portion of a typical
current steering DAC 100 in which a digital data stream is applied to a synchronousdigital output latch 101. “Synchronous” means that the data on the latch input is transferred to the output in response to triggering of the latch by a clocking signal In real world applications, considerable digital processing is involved in producing such a digital data stream, but in the context of a DAC, such preceding digital circuitry need not be described. When thelatch 101 is clocked, the data present on the D-input is transferred to the Q output, and its complement is transferred to the Q-bar output. - The outputs of
latch 101 asynchronously controlswitch drivers 102, which in turn controldifferential switching elements 103 that control a constant current source supplied from a common source node. “Asynchronously” means that the logic state of the outputs of theswitch drivers 102 and thedifferential switching elements 103 change state in response to their inputs changing state, rather than in response to a clocking signal. For a given logic state present on the output of thelatch 101, one switch of thedifferential switching elements 103 will be on, and the other will be off. When the logic state on theoutput latch 101 changes, the on-off states of thedifferential switching elements 103 also change correspondingly. Whicheverdifferential switching element 103 is on provides a current path for constantcurrent source 104 through one of theanalog output resistors 105. Thus, an analog signal output signal is developed atoutput terminals 106. - In theory, such a
current steering DAC 100 can operate at any frequency to provide an analog output corresponding to the digital data input. In the real world, errors and noise occur throughout the system, the effects of which increase with operating frequency. These effects may be code dependent and may result in harmonic distortion and harmonic spurs in the analog output signal. - One approach to reducing code dependent noise is presented by FIG. 8 of U.S. Pat. No. 6,344,816, which describes adding an additional clocked circuit called a “dummy latch” in parallel with the
output latch 101. The output of the dummy latch is not itself used in any way, rather the dummy latch and theoutput latch 101 are connected and operated such that with every cycle of the clocking signal, one of the latches will change state and the other will not. Thus, if theoutput latch 101 changes state with the data signal, the dummy latch maintains its logic state, and if theoutput latch 101 maintains its logic state constant with an unchanging data signal, then the dummy latch will change logic states. According to the '816 patent, this arrangement maintains a constant loading on the clocking signal that is independent of the data signal logic state. There is no suggestion in the '816 that its teaching might be extensible beyond its focus on the clocking signal. - A representative embodiment of the present invention includes a method and device for code independent switching in a digital-to-analog converter (DAC). In the DAC shown in FIG. 1, if the
switch drivers 102 can completely settle for every data transition fromlatch 101, the switching characteristics will be constant for thedifferential switching elements 103. As the output frequency increases, thedifferential switching elements 103 are switched faster, requiring theswitch drivers 102 to settle in a shorter time. If theswitch drivers 102 do not settle to the same value each time, the switching characteristics may vary and code dependent distortion will result. Embodiments of the present invention avoid such code dependent distortion. - A synchronous digital circuit is triggered by a clocking signal and develops a digital data signal. A current steering circuit has a common source node for supplying current, and develops an analog output signal representative of the digital data signal. Any switching disturbances at the common source node are substantially data independent.
- In a further embodiment, the current steering circuit contains multiple switching elements arranged so that a constant number of switching elements change conduction state with every cycle of the clocking signal. In addition or alternatively, the current steering circuit may receive the digital data signal as a first input and an auxiliary data signal as a second input. The auxiliary data signal changes logic state when: (i) triggered by the clocking signal, and (ii) the digital data signal does not change logic state.
- In another embodiment, the current steering circuit includes (i) a switch driver circuit for developing a switch control signal representative of the digital data signal, and (ii) a differential switching circuit responsive to the switch control signal for switching the current from the common source node to develop the analog output signal.
- The current steering circuit may use a single switching element for developing the analog output signal.
- A representative embodiment of the present invention also includes a method and device for code independent switching in a digital-to-analog converter (DAC). A synchronous digital circuit is triggered by a clocking signal and develops a digital data signal. A current steering circuit has a common source node for supplying current, and develops an analog output signal representative of the digital data signal. The current steering circuit has multiple switching arrangements arranged so that a constant number of switching elements change conduction state with every cycle of the clocking signal.
- In a further such embodiment, the current steering circuit receives the digital data signal as a first input and an auxiliary data signal as a second input, the auxiliary data signal changing logic state when: (i) triggered by the clocking signal, and (ii) the digital data signal does not change state.
- In another embodiment, the current steering circuit includes: (i) a switch driver circuit for developing a switch control signal representative of the digital data signal, and (ii) a differential switching circuit responsive to the switch control signal for switching the current from the common source node to develop the analog output signal.
- The present invention will be more readily understood by reference to the following detailed description taken with the accompanying drawings, in which:
- FIG. 1 shows a typical prior art current steering DAC.
- FIG. 2 shows various waveform traces associated with the DAC in FIG. 1.
- FIG. 3A shows a current steering DAC according to one embodiment of the present invention.
- FIG. 3B shows the associated clock and data waveforms for the DAC circuit in FIG. 3A.
- FIG. 4 shows a further embodiment of the present invention.
- A representative embodiment of the present invention includes a method and device for code independent switching in a digital-to-analog converter (DAC). While U.S. Pat. No. 6,344,816 limited its focus to removing code dependent loading on the clocking signal supplied to clocked digital elements, but embodiments of the present invention are directed at preventing code dependent noise generated by changes in the conduction states of the unclocked circuit switching elements—for example, the
switch drivers 102 and thedifferential switching elements 103 in FIG. 1. This ensures that electrical disturbances on the common source node of thedifferential switching elements 103 are data independent. - It can be shown that when the
switch drivers 102 change conduction state between ON and OFF, some energy is taken from the common source node of thedifferential switching elements 103 to charge capacitances on the output of theswitch drivers 102. The bottom trace in FIG. 2 shows a voltage waveform reflecting this capacitive charging effect at high frequency (above 100 MHz) at node N1, the bias voltage node forswitch drivers 102. This capacitive charging effect, in turn, contributes to a glitch in the voltage at node N2 (the upper trace in FIG. 2), the common source node which supplies the constantcurrent source 104 to thedifferential switching elements 103. This glitch at node N2 then affects the analog output signal atoutput terminals 106. - As explained in the Summary section above, if the
switch drivers 102 can completely settle for every data transition fromlatch 101, the switching characteristics will be constant for thedifferential switching elements 103. As the output frequency increases, thedifferential switching elements 103 are switched faster, requiring theswitch drivers 102 to settle in a shorter time—i.e., the capacitive charging depicting in the lower trace of FIG. 2. If theswitch drivers 102 do not settle to the same value each time, the switching characteristics may vary and code dependent distortion will result. That is, the noise glitch at common source node N2 will vary in amplitude and period with the digital data stream input, and be passed along through thedifferential switching elements 103 as harmonic distortion in the analog output signal atoutput terminals 106. - Embodiments of the present invention address this common source node noise by various techniques, which focus on preventing code dependent switching disturbances caused by either or both of the
switch drivers 102 and thedifferential switching elements 103. This objective can be satisfied by adapting data switching blocks so that for every clocking cycle, the same number of switches turn ON and OFF, regardless of whether or not the data signal changes logic states. This ensures that disturbances on the common source node are uncorrelated to the data stream so that any switching noise generated will have frequency components at the sample rate and its harmonics. - One specific embodiment, shown in FIG. 3A, uses an alternate data path to ensure that the
switch drivers 102 draw the same amount of energy every time that theoutput latch 101 is clocked. FIG. 3B shows the associated clock and data waveforms for the DAC circuit in FIG. 3A. In the DAC shown in FIG. 3A, thedigital output latch 101 is preceded by adata transfer latch 301. Also connected to thedata transfer latch 301 are an alternatedata transfer latch 302 and an alternatedata output latch 303. Connected to the D-input of the alternatedata transfer latch 302 is analternate data gate 304 controlled bydata transfer XNOR 305. The Q and Q-bar outputs of thealternate data latch 302 are input to thealternate data gate 304, and the D-input and Q-bar output of thedata transfer latch 301 are the inputs to thedata transfer XNOR 305. - On clocking transitions when the true data stream stays constant, the
alternate data latch 303 is forced to change logic states. On clocking transitions when the true data stream changes states, the alternate datastream output latch 303 maintains its logic state. By connecting theswitch drivers 102 to a true data path and an alternate data path, and ensuring that at every clocking cycle one but not both of the two data paths changes conduction state, theswitch drivers 102 will draw the same amount of energy with every clock pulse. Theswitch drivers 102 will therefore settle to the same value independent of the data, resulting in no code dependent switching characteristics, i.e., constant switching levels are maintained that are data independent. A second advantage of such an approach is that the final sample clocking signal, ACLK, sees a data transition at the clock rate, stabilizing any code dependent load on the clock signal and reducing code dependent jitter. - The approach used in FIG. 3A is extended further in the circuit shown in FIG. 4. In this embodiment, the
switch drivers 102 control both thedifferential switching elements 103 and an alternatedifferential switching block 107. The alternate differential switching block 107 shares common source node N2 with thedifferential switching elements 103, but drives its own separate alternateAC load resistor 108 viacoupling capacitor 109. Providing an alternate AC data path without a corresponding alternate DC current path for alternatedifferential switching block 107 avoids problems that may arise if common source node N2 were required to supply current to the alternatedifferential switching block 107. - As before, the
differential switching elements 103 are driven in accordance with the digital data stream to develop a corresponding analog output signal atoutput terminals 106. As with FIG. 3A, in FIG. 4, the alternate data stream changes state when the true data stream does not, and in turn, theswitch drivers 102 create a corresponding data transition in the alternatedifferential switching block 107. Thus, four switches (differential switching elements 103 and alternate differential switching block 107) are coupled to common source node N2, and at every clocking cycle, exactly one of these switches will turn on and one will turn off. - Although various exemplary embodiments of the invention have been disclosed, it should be apparent to those skilled in the art that various changes and modifications can be made which will achieve some of the advantages of the invention without departing from the true scope of the invention. For example, embodiments could be implemented with N-MOS or bi-polar switches. Or, single switch output stages could be used instead of the two-switch differential switching circuits shown. Other implementation details could also be altered in a specific embodiment of the invention.
Claims (18)
1. A digital to analog converter comprising:
a synchronous digital circuit triggered by a clocking signal and developing a digital data signal;
a current steering circuit having a common source node for supplying current to develop an analog output signal representative of the digital data signal, wherein any switching disturbances at the common source node are substantially data independent.
2. A converter according to claim 1 , wherein the current steering circuit contains a plurality of switching elements arranged so that a constant number of switching elements change conduction state with every cycle of the clocking signal.
3. A converter according to claim 2 , wherein the current steering circuit receives the digital data signal as a first input and an auxiliary data signal as a second input, the auxiliary data signal changing logic state when:
i. triggered by the clocking signal, and
ii. the digital data signal does not change logic state.
4. A converter according to claim 1 , wherein the current steering circuit includes:
i. a switch driver circuit for developing a switch control signal representative of the digital data signal, and
ii. a differential switching circuit responsive to the switch control signal for switching the current from the common source node to develop the analog output signal.
5. A converter according to claim 1 , wherein the current steering circuit includes a single switching element for developing the analog output signal.
6. A method of signal processing comprising:
developing a digital data signal with a synchronous digital circuit triggered by a clocking signal;
developing an analog output signal representative of the digital data signal with a current steering circuit having a common source node that supplies current, wherein any switching disturbances at the common source node are substantially data independent.
7. A method according to claim 6 , wherein the current steering circuit contains a plurality of switching elements arranged so that a constant number of switching elements change conduction state with every cycle of the clocking signal.
8. A method according to claim 6 , wherein the current steering circuit receives the digital data signal as a first input and an auxiliary data signal as a second input, the auxiliary data signal changing logic state when:
i. triggered by the clocking signal, and
ii. the digital data signal does not change logic state.
9. A method according to claim 6 , wherein the current steering circuit includes:
i. a switch driver circuit for developing a switch control signal representative of the digital data signal, and
ii. a differential switching circuit responsive to the switch control signal for switching the current from the common source node to develop the analog output signal.
10. A method according to claim 6 , wherein the current steering circuit includes a single switching element for developing the analog output signal.
11. A digital to analog converter comprising:
a synchronous digital circuit triggered by a clocking signal and developing a digital data signal;
a current steering circuit having a common source node for supplying current to develop an analog output signal representative of the digital data signal, the current steering circuit including a plurality of switching arrangements arranged so that a constant number of switching elements change conduction state with every cycle of the clocking signal.
12. A converter according to claim 11 , wherein the current steering circuit receives the digital data signal as a first input and an auxiliary data signal as a second input, the auxiliary data signal changing logic state when:
i. triggered by the clocking signal, and
ii. the digital data signal does not change state.
13. A converter according to claim 11 , wherein the current steering circuit includes:
i. a switch driver circuit for developing a switch control signal representative of the digital data signal and
ii. a differential switching circuit responsive to the switch control signal for switching the current from the common source node to develop the analog output signal.
14. A converter according to claim 11 , wherein the current steering circuit includes a single switching element for developing the analog output signal.
15. A method of signal processing comprising:
developing a digital data signal with a synchronous digital circuit triggered by a clocking signal;
developing an analog output signal representative of the digital data signal with a current steering circuit having a common source node for supplying current, the current steering circuit including a plurality of switching arrangements arranged so that a constant number of switching elements change conduction state with every cycle of the clocking signal.
16. A method according to claim 15 , wherein the current steering circuit receives the digital data signal as a first input and an auxiliary data signal as a second input, the auxiliary data signal changing logic state when:
i. triggered by the clocking signal, and
ii. the digital data signal does not change state.
17. A method according to claim 15 , wherein the current steering circuit includes:
i. a switch driver circuit for developing a switch control signal representative of the digital data signal, and
ii. a differential switching circuit responsive to the switch control signal for switching the current from the common source node to develop the analog output signal.
18. A method according to claim 15 , wherein the current steering circuit includes a single switching element for developing the analog output signal.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/351,066 US6768438B1 (en) | 2003-01-24 | 2003-01-24 | Current DAC code independent switching |
JP2006502932A JP2006517768A (en) | 2003-01-24 | 2004-01-23 | Cord independent switch for current DAC |
EP04704794A EP1586165A2 (en) | 2003-01-24 | 2004-01-23 | Current dac code independent switching |
CNB2004800027051A CN100536341C (en) | 2003-01-24 | 2004-01-23 | Current DAC code independent switching |
PCT/US2004/001717 WO2004068717A2 (en) | 2003-01-24 | 2004-01-23 | Current dac code independent switching |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/351,066 US6768438B1 (en) | 2003-01-24 | 2003-01-24 | Current DAC code independent switching |
Publications (2)
Publication Number | Publication Date |
---|---|
US6768438B1 US6768438B1 (en) | 2004-07-27 |
US20040145505A1 true US20040145505A1 (en) | 2004-07-29 |
Family
ID=32712820
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/351,066 Expired - Lifetime US6768438B1 (en) | 2003-01-24 | 2003-01-24 | Current DAC code independent switching |
Country Status (5)
Country | Link |
---|---|
US (1) | US6768438B1 (en) |
EP (1) | EP1586165A2 (en) |
JP (1) | JP2006517768A (en) |
CN (1) | CN100536341C (en) |
WO (1) | WO2004068717A2 (en) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2390945B (en) * | 2001-08-24 | 2004-03-10 | Fujitsu Ltd | Switching circuitry |
US7098830B2 (en) * | 2004-04-09 | 2006-08-29 | Texas Instruments Incorporated | Current switching arrangement for D.A.C. reconstruction filtering |
WO2008002858A2 (en) * | 2006-06-28 | 2008-01-03 | Analog Devices, Inc. | Return-to-hold switching scheme for dac output stage |
US7619552B1 (en) * | 2008-04-24 | 2009-11-17 | Analog Devices, Inc. | Low distortion current switch |
WO2009133658A1 (en) * | 2008-04-30 | 2009-11-05 | パナソニック株式会社 | Multiple signal switching circuit, current switching cell circuit, latch circuit, current addition type dac, semiconductor integrated circuit, video device, and communication device |
US8928513B1 (en) | 2014-09-18 | 2015-01-06 | IQ-Analog Corporation | Current steering digital-to-analog converter (DAC) switch driver |
US8830101B1 (en) | 2013-10-21 | 2014-09-09 | Ion E. Opris | Single phase clock D/A converter with built-in data combiner |
US9584152B1 (en) | 2016-01-15 | 2017-02-28 | Euvis, Inc. | Current steering digital to analog converter with dual current switch modules |
US9716508B1 (en) | 2016-03-28 | 2017-07-25 | Analog Devices Global | Dummy signal generation for reducing data dependent noise in digital-to-analog converters |
US10148277B1 (en) | 2017-05-19 | 2018-12-04 | Stmicroelectronics International N.V. | Current steering digital to analog converter with decoder free quad switching |
US10122372B1 (en) * | 2017-12-22 | 2018-11-06 | Keysight Technologies, Inc. | Circuit including calibration for offset voltage compensation |
US10187080B1 (en) | 2018-04-26 | 2019-01-22 | Avago Technologies International Sales Pte. Limited | Apparatus and system for high speed keeper based switch driver |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5343196A (en) * | 1992-12-04 | 1994-08-30 | Analog Devices, Inc. | D/A converter with reduced power consumption |
US6369734B2 (en) * | 1998-02-10 | 2002-04-09 | Intel Corporation | Method and apparatus for increasing linearity and reducing noise coupling in a digital to analog converter |
US20020190778A1 (en) * | 2001-05-24 | 2002-12-19 | Intersil Corporation | Apparatus and method for minimizing spurious harmonic noise in switched current steering architectures |
US20030043062A1 (en) * | 2001-08-24 | 2003-03-06 | Fujitsu Limited | Switching circuitry |
US6621438B1 (en) * | 2002-04-30 | 2003-09-16 | Motorola, Inc. | Digital-to-analog conversion with current path exchange during clock phases |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4056740A (en) | 1976-01-06 | 1977-11-01 | Precision Monolithics, Inc. | Differential input-differential output transistor switching cell |
CA1312956C (en) | 1989-08-18 | 1993-01-19 | Richard Stephen Phillips | Cmos digital to analog signal converter circuit |
US5909187A (en) | 1997-08-26 | 1999-06-01 | C-Cube Microsystems | Current steering circuit for a digital-to-analog converter |
WO2000057558A2 (en) * | 1999-03-22 | 2000-09-28 | Siemens Aktiengesellschaft | 1bit digital-analog converter circuit |
GB2356750B (en) | 1999-11-24 | 2002-12-04 | Fujitsu Ltd | Reducing jitter in mixed-signal circuitry |
-
2003
- 2003-01-24 US US10/351,066 patent/US6768438B1/en not_active Expired - Lifetime
-
2004
- 2004-01-23 CN CNB2004800027051A patent/CN100536341C/en not_active Expired - Fee Related
- 2004-01-23 EP EP04704794A patent/EP1586165A2/en not_active Withdrawn
- 2004-01-23 WO PCT/US2004/001717 patent/WO2004068717A2/en active Application Filing
- 2004-01-23 JP JP2006502932A patent/JP2006517768A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5343196A (en) * | 1992-12-04 | 1994-08-30 | Analog Devices, Inc. | D/A converter with reduced power consumption |
US6369734B2 (en) * | 1998-02-10 | 2002-04-09 | Intel Corporation | Method and apparatus for increasing linearity and reducing noise coupling in a digital to analog converter |
US20020190778A1 (en) * | 2001-05-24 | 2002-12-19 | Intersil Corporation | Apparatus and method for minimizing spurious harmonic noise in switched current steering architectures |
US20030043062A1 (en) * | 2001-08-24 | 2003-03-06 | Fujitsu Limited | Switching circuitry |
US6621438B1 (en) * | 2002-04-30 | 2003-09-16 | Motorola, Inc. | Digital-to-analog conversion with current path exchange during clock phases |
Also Published As
Publication number | Publication date |
---|---|
CN1742435A (en) | 2006-03-01 |
JP2006517768A (en) | 2006-07-27 |
WO2004068717A2 (en) | 2004-08-12 |
US6768438B1 (en) | 2004-07-27 |
WO2004068717A3 (en) | 2004-09-30 |
CN100536341C (en) | 2009-09-02 |
EP1586165A2 (en) | 2005-10-19 |
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