CN209767494U

CN209767494U - CMOS-PECL interface circuit

Info

Publication number: CN209767494U
Application number: CN201920873391.6U
Authority: CN
Inventors: 杨艳军; 杨洁; 李阳军; 钟福如
Original assignee: Zunyi Normal University
Current assignee: Zunyi Normal University
Priority date: 2019-06-11
Filing date: 2019-06-11
Publication date: 2019-12-10
Anticipated expiration: 2029-06-11

Abstract

The utility model provides a CMOS-PECL interface circuit, which comprises a PECL driving main circuit, a reference current source and a control signal generating circuit; the PECL drives a main circuit to drive a PECL interface to generate a PECL level; the reference current source provides a driving current insensitive to temperature for the PECL driving main circuit; the control signal generating circuit generates a timing control signal required by the PECL to drive the main circuit to work. The utility model discloses because the time that pulse current lasts is very short, the consumption of increase is very little, consequently through adopting the pulse current technique to minimum consumption cost has significantly reduced output voltage's transformation time, has strengthened PECL output circuit's driving force.

Description

CMOS-PECL interface circuit

Technical Field

The utility model relates to a CMOS-PECL interface circuit belongs to integrated circuit technical field.

Background

The amount of data processed by today's computer networks is explosively increasing, requiring ever-increasing data transfer rates, and the conventional approach is to use ECL circuits composed of bipolar transistors to achieve high-speed data transfer, but the BiCMOS process that provides bipolar transistors is more expensive than the standard CMOS process. In addition, the ECL circuit has a negative operating voltage, which is incompatible with CMOS processes, and therefore a PECL driver circuit is generally used in CMOS for high-speed data transmission.

However, in the prior art, for the situation that the driving capability of the PECL output circuit is weak, it is difficult to avoid the high power consumption penalty by the general method of enhancing the driving capability of the PECL output circuit.

SUMMERY OF THE UTILITY MODEL

In order to solve the technical problem, the utility model provides a CMOS-PECL interface circuit, this CMOS-PECL interface circuit can show with minimum consumption cost and reduce output voltage's conversion time through adopting the pulse current technique, has strengthened PECL output circuit's driving force.

The utility model discloses a following technical scheme can realize.

The utility model provides a CMOS-PECL interface circuit, which comprises a PECL driving main circuit, a reference current source and a control signal generating circuit; the PECL drives a main circuit to drive a PECL interface to generate a PECL level; the reference current source provides a driving current insensitive to temperature for the PECL driving main circuit; the control signal generating circuit generates a timing control signal required by the PECL to drive the main circuit to work.

The PECL driving main circuit is provided with a load consisting of R _L1, R _L2 and a voltage source V _com, wherein R _L1 and R _L2 are respectively connected to an output voltage V _outp end and a V _outn end, the R _L1 branch is connected with four branches, the first branch of the four branches is connected with one path of driving current of a reference current source, the second branch of the four branches is connected with one path of clock output signal of a control signal generating circuit, the third branch of the four branches is connected with one path of pulse control signal P of the driving current and control signal generating circuit, the fourth branch of the four branches is connected with one path of pulse control signal N of the driving current and control signal generating circuit, and the R _L2 branch is connected with the four branches which are symmetrical to the four branches connected with the R _L1.

The control signal generating circuit is connected with two paths of clock output signals of the PECL driving main circuit in an inverted mode.

And the branch where the two driving currents of the reference current source are located and the branch where the two pulse control signals P of the control signal generating circuit are connected are independently connected to the same node.

The branch connected with the two clock output signals of the control signal generating circuit is connected into a branch, one branch is connected with one drive current of the reference current source and then is grounded with the voltage source V _com, and the branch connected with the two pulse control signals N of the control signal generating circuit is also grounded with the voltage source V _com.

In the control signal generating circuit, two clock output signals are generated into C _lkp and C _lkn through in-phase delay and reverse phase delay of an input clock signal C _lk, the C _lkp and the C _lkn are respectively connected with a C _lk and an AND gate to generate two symmetrical pulse control signals P + and P-, and a branch circuit generating the symmetrical pulse control signals P + and P-is respectively connected with an inverter and a transmission gate to generate symmetrical pulse control signals N-and N +.

the beneficial effects of the utility model reside in that: because the duration of the pulse current is extremely short, the increased power consumption is extremely small, so that by adopting the pulse current technology, the conversion time of the output voltage is obviously reduced at the expense of extremely small power consumption, and the driving capability of the PECL output circuit is enhanced.

Drawings

FIG. 1 is a schematic block diagram of the present invention;

FIG. 2 is a schematic diagram of the connections of the control signal generating circuit of FIG. 1;

FIG. 3 is a timing diagram of the operation of FIG. 1;

Fig. 4 is a specific implementation circuit of the PECL interface circuit.

Detailed Description

the technical solution of the present invention is further described below, but the scope of the claimed invention is not limited to the described.

Fig. 1 shows a CMOS-PECL interface circuit, which includes a PECL driving main circuit, a reference current source, and a control signal generating circuit; the PECL drives a main circuit to drive a PECL interface to generate a PECL level; the reference current source provides a driving current insensitive to temperature for the PECL driving main circuit; the control signal generating circuit generates a timing control signal required by the PECL to drive the main circuit to work.

Therefore, as shown in fig. 1, the external load resistor R _L -R _L1 -R _L2 -50 Ω of the driver, the external common mode level V _com -1.3V, the current sources I _REFP1, I _REFP2 and I _REFN are provided by the reference current source module, I _REFP1, I _REFP2 and I _REFN have small temperature coefficients and have small temperature changes, so as to ensure the stability of the output driving capability at different temperatures, I _P1, I _P2, I _N1 and I _N2 are pulse currents, and are used to reduce the transition time of the output voltage.

When C _clkp is in the positive half cycle of the clock, switch SW _clkp is turned on, switch SW _clkp is turned off, switch SW _clkp controlled by pulse signal P + and switch SW _clkp controlled by pulse signal N-are turned off, switch SW _clkp controlled by pulse signal N + and switch SW _clkp controlled by pulse signal P-are turned on for a short period of time and then turned off immediately, when switches SW _clkp, SW _clkp and SW _clkp are all in the on state, the current flowing through resistor R _clkp is I _clkp -I _clkp -I _clkp, the introduction of I _clkp makes V _clkp more quickly convert to low voltage, the introduction of I _clkp makes current I _clkp + I _clkp, the introduction of I _clkp makes V _clkp more quickly convert to high voltage, after the duration of pulse signal N + and P-is over, only switch SW 72 is turned off, SW 72 and SW 72 are both turned on, and SW 72 is turned off, and the current flowing through resistor R _clkp is stabilized as power consumption of power and power consumption is reduced by power consumption of the power _clkp, and the power consumption of the power generator _clkp, wherein the power consumption of the power generator _clkp is reduced by:

V_outp1＝V_com+(I_REFP1-I_REFN)R_L1

V_outn1＝V_com+I_REFP2R_L2

When the C _clkn is in the positive half cycle of the clock, the switch SW ₂ is turned on, the switch SW ₁ is turned off, the switch SW ₅ controlled by the pulse signal N + and the switch SW ₄ controlled by the pulse signal P-are turned off, the switch SW ₃ controlled by the pulse signal P + and the switch SW ₆ controlled by the pulse signal N-are turned off immediately after being turned on for a short period of time, when the switches SW ₆, SW ₆ and SW ₆ are all in the on state, the current flowing through the resistor R ₆ is I ₆ + I ₆, the introduction of I ₆ makes the V ₆ switch to the high voltage more quickly, the current flowing through the resistor R ₆ is I ₆ -I ₆, and the introduction of I ₆ makes the V ₆ switch to the low voltage more quickly, after the duration of the pulse signals P + and N-is over, only the switches SW ₆, SW ₆ and SW ₆ are turned off, power consumption is saved, and at this time, the current flowing through the resistor R ₆ is I ₆, the voltage of the output voltage V ₆ is stable:

V_outp2＝V_com+I_REFP1R_L1

V_outn2＝V_com+(I_REFP2-I_REFN)R_L2

The generation circuits of the pulse signals P +, P-, N + and N-are shown in FIG. 2, wherein C _lk is an input clock signal, C _lka and C _lkp are in-phase output signals of C _lk, C _lkb and C _lkn are inverted output signals of C _lk, C _lkp and C _lkn are different from C _lka and C _lkb in delay of one NAND gate, one transmission gate and three inverters, and the timing diagram thereof is shown in FIG. 3.

Fig. 4 shows a specific implementation circuit of the PECL interface circuit, where I _REF is provided by a reference current source module, current source I _REFP1 is composed of cascode current sources M9 and M11, current source I _REFP2 is composed of cascode current sources M10 and M12, and current source I _REFN is composed of cascode current sources M5 and M6.

In practical tests, the rise time and the fall time of the output differential signal (V _outp -V _outn) with the pulse current are 164.6ps and 147.3 ps., while the rise time and the fall time of the output differential signal (V _outp -V _outn) without the pulse current are 367.1ps and 348.1 ps., so that the rise time and the fall time are improved by about 200ps and the rise time and the fall time of the output signal are reduced by more than one time by adopting the pulse current technology.

Claims

1. A CMOS-PECL interface circuit comprises a PECL driving main circuit, a reference current source and a control signal generating circuit, and is characterized in that: the PECL drives a main circuit to drive a PECL interface to generate a PECL level; the reference current source provides a driving current insensitive to temperature for the PECL driving main circuit; the control signal generating circuit generates a timing control signal required by the PECL to drive the main circuit to work.

2. The CMOS-PECL interface circuit as claimed in claim 1, wherein the PECL driver main circuit has R _L1, R _L2 and V _com forming a load, R _L1 and R _L2 are connected to V _outp and V _outn output voltages respectively, the R _L1 branch is connected to four branches, the first branch is connected to a driving current of a reference current source, the second branch is connected to a clock output signal of a control signal generating circuit, the third branch is connected to a pulse control signal P of a driving current and control signal generating circuit, the fourth branch is connected to a pulse control signal N of a driving current and control signal generating circuit, and the R _L2 branch is connected to four branches symmetrically connected to the R _L1 branch.

3. The CMOS-PECL interface circuit of claim 2, wherein: the control signal generating circuit is connected with two paths of clock output signals of the PECL driving main circuit in an inverted mode.

4. The CMOS-PECL interface circuit of claim 2, wherein: and the branch where the two driving currents of the reference current source are located and the branch where the two pulse control signals P of the control signal generating circuit are connected are independently connected to the same node.

5. The CMOS-PECL interface circuit of claim 2, wherein the branch to which the two clock output signals of the control signal generating circuit are connected is connected as a branch, a driving current of the reference current source is connected to the branch and then is grounded with a voltage source V _com, and the branch to which the two pulse control signals N of the control signal generating circuit are connected is also grounded with a voltage source V _com.

6. The CMOS-PECL interface circuit of claim 2, wherein in the control signal generating circuit, two clock output signals are generated by the input clock signal C _lk through in-phase delay and anti-phase delay as C _lkp and C _lkn, C _lkp and C _lkn respectively connect with C _lk to the AND gate to generate two symmetrical pulse control signals P + and P-, and the branch circuit generating the symmetrical pulse control signals P + and P-respectively connect with the inverter and the transmission gate to generate the symmetrical pulse control signals N-and N +.