CN116318089A - Negative-pressure multi-way switch and chip based on SOI - Google Patents

Abstract

The invention discloses a negative pressure multi-way switch and a chip based on SOI, wherein the negative pressure multi-way switch comprises: a power supply circuit and one or more driving circuits; the driving circuits are distributed on a plurality of different SOI base islands, the different SOI base islands correspond to different voltage domains, and the different SOI base islands are isolated through a medium; the power supply circuit is used for supplying power to the driving circuit; the driving circuit is used for outputting one or more high dynamic range voltage signals according to the external low-voltage logic signals. The scheme of the invention can provide voltage output in a wider range and save an external power supply.

Description

Negative-pressure multi-way switch and chip based on SOI

Technical Field

The invention relates to the technical field of circuits, in particular to a negative-pressure multi-way switch and a chip based On Silicon On Insulator (SOI).

Background

In the prior art, the multi-way switch is mainly used for driving, and has two modes of separation and integration.

As shown in fig. 1, the structure of the existing discrete multi-way switch mainly comprises five major parts, namely a PWM (pulse width modulation ) logic processing module, a level conversion module, a gate driving module, a power supply and a MOS transistor switch. The basic principle is as follows: the PWM signal is externally input, and is processed by the PWM controller to generate a logic signal (mainly for judging high and low levels) suitable for the inside of the chip, and the logic signal is subjected to level conversion, and then is subjected to grid driving to increase driving capability and is used for driving the MOS transistor switch of the last stage. The power module is used for supplying power to other modules, multiple groups of power supplies are usually needed, the occupied area of a PCB (Printed Circuit Board ) is large, and the control mode is complex. This solution has mainly the following problems: the PCB has large area, large transmission delay and high cost; (2) the system control mode is complex; (3) multiple power supplies are needed, and resources are occupied; (4) The final output does not support negative pressure and cannot adapt to a scene requiring negative pressure.

The existing integration scheme is to integrate all the functional modules in fig. 1 onto one chip using a conventional silicon process. This integration scheme has the following problems: (1) The final output does not support negative pressure (2) and parasitic latch-up is easy to generate; latch-up is a parasitic effect specific to the CMOS process, which seriously leads to failure of the circuit and even burning out of the chip; (3) the maximum operating voltage is limited to only 120V.

Disclosure of Invention

The embodiment of the invention provides a negative-pressure multi-way switch and a chip based on SOI, which can provide voltage output in a wider range and save an external power supply.

Therefore, the embodiment of the invention provides the following technical scheme:

in one aspect, an embodiment of the present invention provides a negative-pressure multi-way switch based on SOI, the negative-pressure multi-way switch including: a power supply circuit and one or more driving circuits; the driving circuits are distributed on a plurality of different SOI base islands, the different SOI base islands correspond to different voltage domains, and the different SOI base islands are isolated through a medium;

the power supply circuit is used for supplying power to the driving circuit;

the driving circuit is used for outputting one or more high dynamic range voltage signals according to the external low-voltage logic signals.

Optionally, the driving circuit includes: an I/O processing module, a level shifting circuit, one or more power switch modules;

the I/O processing module is used for converting the external low-voltage logic signal into an analog signal;

the level conversion module is used for carrying out level shift on the analog signal and outputting a logic control signal;

and the power switch module is used for outputting one or more high dynamic range voltage signals according to the logic control signals.

Optionally, the I/O processing module operates in a first voltage domain.

Optionally, the power switch module includes: logic control circuit, and power module;

the logic control circuit is used for generating a switch control signal according to the logic control signal;

the power module is used for outputting the high dynamic range voltage signal according to the switch control signal.

Optionally, the power module includes: a first switching unit and a second switching unit;

the logic control circuit outputs a first switch control signal and a second switch control signal respectively, wherein the first switch control signal is used for controlling the on and off of the first switch unit, and the second switch control signal is used for controlling the on and off of the second switch unit.

Optionally, the first switch unit is a PMOS tube, and the second switch unit is an NMOS tube.

Optionally, the first switch unit and the second switch unit are both NMOS transistors.

Optionally, the power switch module further comprises:

a first driving unit for enhancing driving capability of the first switch control signal;

and the second driving unit is used for enhancing the driving capability of the second switch control signal.

Optionally, the first driving unit operates in a second voltage domain; the second driving unit operates in a third voltage domain.

Optionally, the multiple high dynamic range voltage signals are in phase and in phase or in anti-phase with the external low voltage logic signal.

Optionally, the amplitude of the external low-voltage logic signal is 0-5V; the amplitude of the high dynamic range voltage signal is-5-200V.

On the other hand, the embodiment of the invention also provides a chip which comprises the negative-pressure multi-way switch based on the SOI.

According to the negative-pressure multi-way switch and the chip based on the SOI, the driving circuit is distributed on a plurality of different SOI base islands, the different SOI base islands correspond to different voltage domains, and the different SOI base islands are isolated through a medium, so that the medium isolation in components can be realized, the latch-up effect is avoided, the voltage output in a wider range can be obtained, the high-voltage power supply can reach 200V, and the low-voltage power supply can reach-5V. And the external power supply is saved. By arranging a plurality of driving circuits, multiple paths of high dynamic range voltage signals can be provided, and an external power supply is saved. The negative-pressure multi-way switch based on the SOI is simple in control mode and high in reliability. Further, through high integration, the area of an external system PCB can be saved, the cost is reduced, the propagation delay is reduced, the switching speed is increased, and the loss is reduced.

Drawings

FIG. 1 is a schematic diagram of a prior art multiple-way switch;

fig. 2 is a schematic structural diagram of a negative-pressure multi-way switch based on SOI according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a relationship between a plurality of SOI islands in an SOI-based negative-pressure multi-path switch according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a specific structure of a negative-pressure multi-way switch based on SOI according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a circuit configuration of a driving circuit according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of the power module in the embodiment of FIG. 5;

FIG. 7 is a schematic diagram of the operating principle of the power module shown in FIG. 6;

fig. 8 is a schematic diagram of a structure of a first driving unit corresponding to the power module shown in fig. 6;

FIG. 9 is a schematic diagram of another configuration of a driving circuit according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of the power module in the embodiment of FIG. 9;

FIG. 11 is a schematic diagram of the operating principle of the power module shown in FIG. 10;

fig. 12 is a schematic diagram of a structure of a first driving unit corresponding to the power module shown in fig. 10.

Detailed Description

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 2 is a schematic structural diagram of a negative-pressure multi-way switch based on SOI according to an embodiment of the present invention.

The negative-voltage multi-way switch 200 of this embodiment includes: a power supply circuit 201, and one or more driving circuits 202; the driving circuit 202 is distributed on a plurality of different SOI islands, such as SOI islands 21 and 22 identified by different ground patterns in fig. 2, wherein the different SOI islands correspond to different voltage domains, and the different SOI islands are isolated by a medium;

the power supply circuit 201 is configured to supply power to the driving circuit;

the driving circuit 202 is configured to output one or more high dynamic range voltage signals according to an external low voltage logic signal.

It should be noted that, the SOI islands 21 and the SOI islands 22 in fig. 2 are only schematic, and in practical applications, the number of SOI islands may be determined according to the number of different voltage domains required, which is not limited to the embodiment of the present invention.

In addition, in order to more clearly illustrate the relationship between different SOI islands, fig. 3 shows a schematic diagram of the relationship between multiple SOI islands in the SOI-based negative-pressure multi-path switch according to the embodiment of the present invention.

In the negative-pressure multi-way switch based on SOI provided by the embodiment of the invention, the amplitude of the external low-voltage logic signal can be 0-5V; the amplitude of the high dynamic range voltage signal can reach-5-200V.

Fig. 4 is a schematic diagram of a specific structure of a negative-pressure multi-way switch based on SOI according to an embodiment of the present invention.

In this embodiment, the power supply circuit 201 includes a power supply circuit 201 and multiple driving circuits I1, …, in, where the power supply circuit 201 can provide power for the driving circuits of each path.

In order to more clearly illustrate the structure of each driving circuit, fig. 5 shows a schematic diagram of the structure of one driving circuit.

Referring to fig. 5, the driving circuit I1 includes: an I/O processing module I11, a level shifting circuit I12, one or more power switching modules. One power switching module is shown in fig. 5. Wherein:

the I/O processing module I11 is used for converting the external low-voltage logic signal into an analog signal; the I/O processing module operates in a first voltage domain.

The level conversion module I12 is used for level shifting the analog signal and outputting a logic control signal;

the power switch module is used for outputting one or more high dynamic range voltage signals according to the logic control signals.

As shown in fig. 5, the power switch module includes: logic control circuit I13, and power module I16. Wherein:

the logic control circuit I13 is used for generating a switch control signal according to the logic control signal;

the power module I16 is configured to output the high dynamic range voltage signal according to the switch control signal.

As shown in fig. 5, the power module I16 includes: a first switching unit I161 and a second switching unit I162.

The logic control circuit I13 generates a first switch control signal and a second switch control signal, where the first switch control signal is used to control on and off of the first switch unit I161, and the second switch control signal is used to control on and off of the second switch unit I162. The first switching unit I161 and the second switching unit I162 may be implemented by using MOS transistors.

Further, in order to enhance the driving capability of the first switch control signal and the second switch control signal, the power switch module may further include:

a first driving unit I14 for enhancing a driving capability of the first switching control signal;

and a second driving unit I15 for enhancing the driving capability of the second switch control signal.

The first driving unit I14 works in a second voltage domain; the second driving unit I15 operates in a third voltage domain.

The working principle of the SOI-based negative-pressure multi-way switch according to the embodiment of the present invention will be described in detail with reference to fig. 4 and 5.

As shown in fig. 4, in the SOI-based negative pressure multiplexing switch, each input signal INx may control n output signals OUTx. For example, the external low voltage logic signal IN1 may control the output signals OUT1, OUT2 to OUTn, and the output signals OUT1 to OUTn are output IN phase, and if a larger driving capability is required, the output signals OUT1 to OUTn may be used IN parallel. Meanwhile, the scheme of the invention can have n input signals IN. Correspondingly, the scheme of the invention has n groups of submodules, as shown by I1 and In the figure.

In the scheme of the invention, all the submodules share one power supply circuit 201 for generating two voltages according to an external voltage signal, wherein one voltage is 5V lower than VDDH and is called VSS3; one 5V higher than VDDL is referred to as VDD2.VDDH and VDDL are external power and ground, respectively.

Each sub-module has the same structure, and can share three groups of power supplies with different voltage domains, namely, a power supply VDD1 and a ground VSS1 of a first voltage domain, a power supply VDD2 and a ground VSS2 of a second voltage domain, and a power supply VDD3 and a ground VSS3 of a third voltage domain. The external ground VDDL may be the ground VSS2 of the second voltage domain, and the external power supply VDDH may be the power supply VDD3 of the third voltage domain.

Referring to fig. 5, each sub-module inputs an external low voltage logic signal IN1 and outputs a voltage signal OUT1.

The working voltage of the I/O processing module I11 is VDD 1-VSS 1, and VDD1 is the relative power supply of the externally given first group of voltage domains; VSS1 is the relative ground of the externally given first set of voltage domains.

The input end of the I/O processing module I11 is connected with an external low-voltage logic signal IN1, and the output end of the I/O processing module I11 is connected with the input end of the level conversion circuit I12. The main function of the I/O processing module I11 is to perform level processing on the externally output low voltage logic signal IN1, and convert the externally output low voltage logic signal IN1 into an analog signal, so as to provide input for a subsequent circuit.

The level shifter circuit I12 operates in two voltage domains, namely VDD 1-VSS 1 and VDD 2-VSS 2 (i.e., VDDL). Where VDD2 is the relative power supply of the second set of voltage domains generated by VDDH. The output terminal of the level shift circuit I12 is connected to the input terminal of the logic control circuit I13. The level shift circuit I12 has a main function of level shifting the signal output from the I/O processing block I11, converting from VDD1 to VDD2 with respect to the power supply, converting from VSS1 to VDDL with respect to the power supply, and then taking the signal as an input of a subsequent circuit to control the output of the signal.

The working voltage of the logic control circuit I13 is VDD 2-VDDL; a first output end of the logic control circuit I13 is connected to the first driving unit I14; a second output terminal of the logic control circuit I13 is connected to the second driving unit I15. The logic control circuit I13 mainly outputs a first switch control signal and a second switch control signal to control dead time between a first switch unit I161 and a second switch unit I162 in the power module I16, so that excessive current and damage to devices caused by direct connection of upper MOS tubes and lower MOS tubes are prevented.

The first driving unit I14 operates in two voltage domains, VDD2 to VSS2 (i.e., VDDL), VDD3 (i.e., VDDH) to VSS3, respectively, that is, two sets of power supplies are required.

The output end of the first driving unit I14 is connected to the first input end of the power module I16; the primary function of the first driving unit I14 is to enhance the driving capability of the first switch control signal output by the logic control circuit I13, and then control the on or off of the first switch unit I161 in the power module I16.

The operating voltage of the second driving unit I15 is VDD2 to VSS2 (i.e., VDDL).

The output end of the second driving unit I15 is connected to the second input end of the power module I16; the main function of the second driving unit I15 is to enhance the driving capability of the second switch control signal output by the logic control circuit I13, and then control the on or off of the second switch unit I162 in the power module I16.

The working voltage of the power module I16 is VDDH-VDDL; the amplitude of the output voltage signal OUT1, OUT1 is VDDH-VDDL. The voltage signal OUT1 has a high dynamic range, e.g. VDDL can reach-5V at the lowest and VDDH can reach 200V.

The phase of the voltage signal OUT1 is the same as or opposite to the phase of the external low voltage logic signal IN1, depending on the application.

In a specific application, the first switching unit I161 and the second switching unit I162 in the power module I16 may be implemented by using MOS transistors, which are described in detail below.

Fig. 6 is a schematic diagram of the power module in the embodiment shown in fig. 5.

In this embodiment, the power module includes a PMOS transistor P1 and an NMOS transistor N1. Referring also to fig. 5, wherein:

the source electrode of the PMOS transistor P1 is connected with the external power supply VDDH, the GATE electrode of the PMOS transistor P1 is connected with the output terminal gate_hs of the first driving unit I14, the drain electrode of the PMOS transistor P1 is connected with the drain electrode of the NMOS transistor N1, and the connection node is used as the output terminal of the power module, and outputs the voltage signal OUT1 with a high dynamic range.

The GATE of the NMOS transistor N1 is connected to the output gate_ls of the second driving unit I15, and the source of the NMOS transistor N1 is connected to the external power supply VDDL.

The power module of this embodiment operates on the principle that gate_hs has a high level of VDDH and a low level of VSS3 as shown in fig. 7. In this embodiment, VSS3 is 5V lower than VDDH. The high level of gate_ls is VDD2 and the low level is VDDL. In this embodiment, VDD2 is 5V higher than VDDL.

When gate_hs is low and gate_ls is low, PMOS transistor P1 is turned on, NMOS transistor N1 is turned off, and output signal OUT1 outputs high level VDDH.

When gate_hs is high and gate_ls is high, the PMOS transistor P1 is turned off, the NMOS transistor N1 is turned on, and the output signal OUT1 outputs the low level VDDL.

In this embodiment, VDDH is up to 200V in voltage and VDDL is down to-5V in voltage.

In addition, dead time is set at the moment of switching between the PMOS transistor P1 and the NMOS transistor N1, in the dead time, gate_hs is at a high level, gate_ls is at a low level, and at this time, both the PMOS transistor P1 and the NMOS transistor N1 are in an off state, so that the PMOS transistor P1 and the NMOS transistor N1 are effectively prevented from being directly connected. The dead time can have various implementation schemes, and can be an adaptive dead time or a dead time with fixed time, and the functions can be implemented in the logic control circuit I13.

Referring to fig. 6, the adaptive dead zone refers to that when the PMOS transistor P1 is turned on (even if the PMOS transistor P1 is turned on), the NMOS transistor N1 is turned off first, whereas when the NMOS transistor N1 is turned on, the PMOS transistor P1 is turned off first. That is, after detecting that gate_hs goes high, gate_ls is pulled high again; after detecting that gate_ls goes low, gate_hs is pulled low again.

Referring to fig. 5, the fixed dead time refers to a fixed delay time of the two control signals output by the logic control circuit I13, that is, the first switch control signal and the second switch control signal, when the level is inverted, so as to prevent the PMOS transistor P1 and the NMOS transistor N1 from being directly connected.

Accordingly, a specific structure of the first driving unit I14 is shown in fig. 8, corresponding to the power module shown in fig. 6 described above.

Referring to fig. 8, in this embodiment, the first driving unit I14 includes a first level converting unit I141 and a first buffer driving unit I142. The input end ctrl_hs of the first level shifter I141 is connected to the first output end of the pre-stage logic control circuit I13, the output end of the first level shifter I141 is connected to the input end of the first buffer driving unit I142, and the output end gate_hs of the first buffer driving unit I142 is connected to the GATE of the PMOS transistor P1 in fig. 6.

In the embodiment shown in fig. 8, the first level shifting unit I141 is configured to shift the first switch control signal output by the logic control circuit I13 from the second voltage domain to the third voltage domain, i.e., the high level of the input terminal ctrl_hs is VDD2, and the low level is VDDL. The first buffer driving unit I142 operates in a third voltage domain, that is, the operating voltage is VDD3 (i.e., VDDH) to VSS3, and is used for enhancing the driving capability of the logic signal output by the preceding logic control circuit I13, that is, the first switch control signal, so as to accelerate the switching speed of the power transistor. The high level of the output gate_hs of the first buffer driving unit I142 is VDDH, and the low level is VSS3, as shown in fig. 7.

It should be noted that, the first level shifter I141 may be an existing conventional level shifter circuit, which is not limited in this embodiment of the present invention.

With continued reference to fig. 5, the second driving unit I15 operates in the second voltage domain, i.e., VDD2 to VSS2 (i.e., VDDL), and does not need to perform voltage domain conversion, but only needs to enhance the driving capability of the second switch control signal output by the logic control circuit I13. The high level of the output gate_ls of the second driving unit I15 is VDD2, and the low level is VSS2 (i.e., VDDL), as shown in fig. 7.

Referring to fig. 9, another schematic diagram of a driving circuit according to an embodiment of the invention is shown.

The difference from the embodiment shown in fig. 5 is that in this embodiment, the first switching unit I161 and the second switching unit I162 in the power module I16 are each implemented by an NMOS tube. Accordingly, the specific operation of the first driving unit I14 may also be correspondingly different. In this embodiment, the first driving unit I14 also operates in two voltage domains, VDD2 to VSS2 (i.e., VDDL), VDD3 (i.e., VDDH) to VSS3, respectively, that is, two sets of power supplies are required.

The power module I16 and the first driving unit I14 are described in detail below with reference to fig. 10, 11 and 12, respectively.

Referring to fig. 10, a schematic diagram of the power module in the embodiment shown in fig. 9 is shown.

In this embodiment, the power module I16 includes a first NMOS transistor N1 and a second NMOS transistor N2. The grid electrode of the first NMOS tube N1 is connected with the output end GATE_LS of the second driving unit I15, and the source electrode of the first NMOS tube N1 is connected with the external ground VDDL; the drain electrode of the first NMOS tube N1 is connected with the drain electrode of the second NMOS tube, and the connecting node is used as the output end of the power module to output a voltage signal OUT1 with a high dynamic range.

The GATE of the second NMOS transistor N2 is connected to the output gate_hs of the first driving unit I14, and the source of the second NMOS transistor N2 is connected to the external power supply VDDH.

The power module of this embodiment operates on the principle that the gate_hs has a high level of VDD3 and a low level of VDDH, i.e., VSS3, as shown in fig. 11, and VDD3 is 5V higher than VDDH in this embodiment. The high level of gate_ls is VDD2, and the low level is VDDL, i.e., VSS2, and VDD2 is 5V higher than VDDL in this embodiment.

When gate_hs is at high level and gate_ls is at low level, the second NMOS transistor N2 is turned on, the first NMOS transistor N1 is turned off, and the output signal OUT1 outputs the high level VDDH.

When gate_hs is at low level and gate_ls is at high level, the second NMOS transistor N2 is turned off, the first NMOS transistor N1 is turned on, and the output signal OUT1 outputs the low level VDDL.

In this embodiment, the voltage of VDDH may be as high as 200V and the voltage of VDDL may be as low as-5V.

In addition, dead time is set at the moment of switching the first NMOS transistor N1 and the second NMOS transistor N2, in the dead time, gate_hs is low level, gate_ls is low level, and at this time, the first NMOS transistor N1 and the second NMOS transistor N2 are both in an off state, so that the first NMOS transistor N1 and the second NMOS transistor N2 are effectively prevented from being directly connected. The dead time can have various implementation schemes, and can be an adaptive dead time or a dead time with fixed time, and the functions can be implemented in the logic control circuit I13.

Accordingly, a specific structure of the first driving unit I14 is shown in fig. 12, corresponding to the power module shown in fig. 9 described above.

Referring to fig. 12, in this embodiment, the first driving unit I14 includes a second level converting unit I171 and a second buffer driving unit I172. The input end ctrl_hs of the second level shifter circuit I171 is connected to the first output end of the pre-stage logic control circuit I13, the output end of the second level shifter circuit I171 is connected to the input end of the second buffer driving unit I172, and the output end gate_hs of the second buffer driving unit I172 is connected to the GATE of the second NMOS transistor N2 in fig. 10.

In the embodiment shown in fig. 8, the second level shifting unit I172 is configured to shift the first switch control signal output by the logic control circuit I13 from the second voltage domain to the third voltage domain, i.e., the high level of the input terminal ctrl_hs is VDD2, and the low level is VDDL. The second buffer driving unit I172 operates in a third voltage domain, that is, the operating voltage is VDD3 (i.e., VDDH) to VSS3, and is used for enhancing the driving capability of the logic signal output by the preceding logic control circuit I13, that is, the first switch control signal, so as to accelerate the switching speed of the power tube. The high level of the output gate_hs of the second buffer driving unit I172 is VDDH, and the low level is VSS3, as shown in fig. 11.

According to the negative-pressure multi-way switch based on SOI, the driving circuit is distributed on a plurality of different SOI base islands, the different SOI base islands correspond to different voltage domains, and dielectric isolation is carried out among the different SOI base islands, so that dielectric isolation in components can be realized, latch-up effect is avoided, voltage output in a wider range can be obtained, a high-voltage power supply can reach 200V, and a low-voltage power supply can reach-5V. And the external power supply is saved. By arranging a plurality of driving circuits, multiple paths of high dynamic range voltage signals can be provided, and an external power supply is saved. The negative-pressure multi-way switch based on the SOI is simple in control mode and high in reliability. Further, through high integration, the area of an external system PCB can be saved, the cost is reduced, the propagation delay is reduced, the switching speed is increased, and the loss is reduced.

Correspondingly, the embodiment of the invention also provides a chip, which comprises the negative-pressure multi-way switch based on the SOI.

It should be understood that the term "and/or" is merely an association relationship describing the associated object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In this context, the character "/" indicates that the front and rear associated objects are an "or" relationship.

The term "plurality" as used in the embodiments of the present invention means two or more.

The first, second, etc. descriptions in the embodiments of the present invention are only used for illustrating and distinguishing the description objects, and no order is used, nor is the number of the devices in the embodiments of the present invention limited, and no limitation on the embodiments of the present invention should be construed.

In the several embodiments provided in the present invention, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the device embodiments described above are merely illustrative; for example, the division of the units is only one logic function division, and other division modes can be adopted in actual implementation; for example, multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may be physically disposed separately, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in hardware plus software functional units.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (12)

1. A negative-pressure multiple-way switch based on SOI, characterized in that the negative-pressure multiple-way switch comprises: a power supply circuit and one or more driving circuits; the driving circuits are distributed on a plurality of different SOI base islands, the different SOI base islands correspond to different voltage domains, and the different SOI base islands are isolated through a medium;

the power supply circuit is used for supplying power to the driving circuit;

the driving circuit is used for outputting one or more high dynamic range voltage signals according to the external low-voltage logic signals.

2. The SOI-based negative pressure multi-way switch of claim 1 wherein the drive circuit comprises: an I/O processing module, a level shifting circuit, one or more power switch modules;

the I/O processing module is used for converting the external low-voltage logic signal into an analog signal;

the level conversion module is used for carrying out level shift on the analog signal and outputting a logic control signal;

and the power switch module is used for outputting one or more high dynamic range voltage signals according to the logic control signals.

3. The SOI-based negative pressure multi-way switch of claim 2 wherein the I/O processing module operates in a first voltage domain.

4. The SOI-based negative pressure multi-way switch of claim 2 wherein the power switch module comprises: logic control circuit, and power module;

the logic control circuit is used for generating a switch control signal according to the logic control signal;

the power module is used for outputting the high dynamic range voltage signal according to the switch control signal.

5. The SOI-based negative pressure multi-way switch of claim 4 wherein the power module comprises: a first switching unit and a second switching unit;

the logic control circuit outputs a first switch control signal and a second switch control signal respectively, wherein the first switch control signal is used for controlling the on and off of the first switch unit, and the second switch control signal is used for controlling the on and off of the second switch unit.

6. The SOI-based negative pressure multi-way switch of claim 5 wherein the first switch unit is a PMOS transistor and the second switch unit is an NMOS transistor.

7. The SOI-based negative pressure multi-way switch of claim 5 wherein the first and second switch units are NMOS transistors.

8. The SOI-based negative pressure multi-way switch of claim 5 wherein the power switch module further comprises:

a first driving unit for enhancing driving capability of the first switch control signal;

and the second driving unit is used for enhancing the driving capability of the second switch control signal.

9. The SOI-based negative pressure multi-way switch of claim 8 wherein the first drive unit operates in a second voltage domain; the second driving unit operates in a third voltage domain.

10. The SOI-based negative pressure multi-way switch of claim 2 wherein the multi-way high dynamic range voltage signal is in phase and either in phase or in anti-phase with the external low voltage logic signal.

11. The SOI-based negative-pressure multi-way switch of any one of claims 1 to 10 wherein the external low-voltage logic signal has an amplitude of 0-5V; the amplitude of the high dynamic range voltage signal is-5-200V.

12. A chip comprising a SOI-based negative-pressure multi-way switch as claimed in any one of claims 1 to 11.

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