US20040036152A1 - Integrated circuit package employing flip-chip technology and method of assembly - Google Patents

Integrated circuit package employing flip-chip technology and method of assembly Download PDF

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Publication number
US20040036152A1
US20040036152A1 US10/677,078 US67707803A US2004036152A1 US 20040036152 A1 US20040036152 A1 US 20040036152A1 US 67707803 A US67707803 A US 67707803A US 2004036152 A1 US2004036152 A1 US 2004036152A1
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Prior art keywords
integrated circuit
array
interconnection sites
circuit die
package substrate
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US10/677,078
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Timothy Harper
Greg Allen
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Avago Technologies General IP Singapore Pte Ltd
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Harper Timothy V.
Allen Greg L.
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Priority to US10/199,441 priority Critical patent/US6659512B1/en
Application filed by Harper Timothy V., Allen Greg L. filed Critical Harper Timothy V.
Priority to US10/677,078 priority patent/US20040036152A1/en
Publication of US20040036152A1 publication Critical patent/US20040036152A1/en
Assigned to AGILENT TECHNOLOGIES, INC. reassignment AGILENT TECHNOLOGIES, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HEWLETT-PACKARD COMPANY
Assigned to AVAGO TECHNOLOGIES GENERAL IP PTE. LTD. reassignment AVAGO TECHNOLOGIES GENERAL IP PTE. LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AGILENT TECHNOLOGIES, INC.
Assigned to AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. reassignment AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 017206 FRAME: 0666. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Assignors: AGILENT TECHNOLOGIES, INC.
Application status is Abandoned legal-status Critical

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L51/00
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1418Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181On opposite sides of the body
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171Disposition
    • H01L2224/1718Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181On opposite sides of the body
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01BASIC ELECTRIC ELEMENTS
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    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate
    • HELECTRICITY
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    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
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    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06589Thermal management, e.g. cooling
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15151Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. IMC (insert mounted components)
    • H05K1/183Components mounted in and supported by recessed areas of the printed circuit board

Abstract

An integrated circuit package includes a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites. A second integrated circuit die has a first surface including an array of interconnection sites. The first array of interconnection sites is electrically connected to the array of interconnection sites of the second integrated circuit die. The second array of interconnection sites is electrically connected to the array of interconnection sites of the first integrated circuit die. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.

Description

    CROSS REFERENCE TO RELATED APPLICATION
  • This patent application is related to U.S. patent application Ser. No. ______, entitled “Flip-Chip Integrated Circuit Package And Method Of Assembly”, filed on even date herewith, assigned to the same assignee, and incorporated herein by reference thereto.[0001]
  • TECHNICAL FIELD
  • This invention relates to a flip-chip integrated circuit assembly, and processes for assembling the integrated circuit assembly using flip-chip techniques. [0002]
  • BACKGROUND OF THE INVENTION
  • In recent years, technologies have emerged which can provide high density electrical interconnections between an integrated circuit (IC) chip and a substrate to form IC assemblies, otherwise known as IC packages. These technologies for forming electrical connections between an IC chip and a substrate are commonly known as wire bonding, tape-automatic bonding (TAB) and solder flip-chip bonding. Although, all these bonding techniques can be used to form high density electrical interconnections, the use of one particular technique over another is typically dictated by the desired number and spacing of the electrical connections on the IC chip and the substrate, as well as the permissible cost for assembling the IC package. [0003]
  • In a comparison of these three techniques, wire bonding is the most common technique for electrically connecting an IC chip to a substrate. This is due to that fact that this technique provides the maximum number of chip connections with the lowest cost per connection. A disadvantage of wire bonding is that inductance present in the wires used in connecting the IC chip to the substrate degrades the electrical performance of the assembled IC package. Moreover, since the wires connect perimeter connections of the IC chip to contacts on the substrate in areas not occupied by the IC chip, wire bonding electrical interconnects require a relatively large surface area of the substrate. Lastly, since wire bonding requires each connection between the IC chip and the substrate to be made one at a time, the process of electrically interconnecting an IC chip to a substrate using the wire bonding technique is somewhat time consuming. [0004]
  • TAB bonding permits a higher density of electrical interconnects when compared to wire bonding. However, TAB bonding is more expensive than wire bonding because TAB bonding requires special tooling for each different IC chip design. Also, like wire bonding, TAB bonding requires perimeter connections and therefore a relatively large surface area of the substrate to accomplish the IC chip and substrate electrical interconnect. Moreover, like wire bonding, undesirable inductance as a result of TAB bonding degrades the electrical performance of the IC chip circuitry. [0005]
  • Flip-chip bonding is achieved by providing an IC chip with an area array of solder wettable contact pads which comprise the signal terminals on the chip. A matching footprint of solder wettable contact pads are provided on the substrate. Before assembly onto the substrate, solder bumps are deposited on the metal pads of the chip and/or the substrate. The chip is then placed upside down on the upper surface of the substrate such that the metal pads (solder bumps) of the chip are in alignment with the metal pads (solder bumps) of the substrate. All connections between the chip and the substrate are then made simultaneously by heating the solder bumps to a reflow temperature at which the solder flows and an electrically conductive joint is formed between the contact pads of the IC chip and the substrate. [0006]
  • When compared to wire bonding and TAB bonding, flip-chip bonding of an IC chip to a substrate provides the advantage of requiring less surface area on the substrate, and thereby facilitates high-density interconnections commonly required in IC assemblies. Since the interconnections between the substrate and the IC chip in flip-chip bonding are short, well controlled electrical characteristics are provided, and undesirable inductance that can degrade the electrical performance of the IC chip circuitry is minimized. In other words, high speed signals are thus propagated in and through the packaged integrated circuits with minimum delay and distortion. [0007]
  • There is a need for improved integrated circuit assemblies. In particular there is a need for an improved integrated circuit assembly that can be assembled using flip-chip bonding techniques to achieve a packaged integrated circuit having low interconnect capacitance, thereby improving signal speed and eliminating some need for off chip driver cells. The improved integrated circuit assembly should provide these features while being amenable to high volume low defect manufacturing. [0008]
  • SUMMARY OF THE INVENTION
  • One embodiment of the present invention is an integrated circuit package that includes a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites. A first integrated circuit die has a first surface including an array of interconnection sites electrically connected to the second array of interconnection sites of the package substrate. A second integrated circuit die has a first surface including an array of interconnection sites electrically connected to the first array of interconnection sites of the package substrate. The first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.[0009]
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention of the present invention will be readily appreciated as the same become better understood by reference to the following detailed description when considered in connection with the accompanying drawings, in which like reference numerals designate like parts throughout the figures thereof, and wherein: [0010]
  • FIG. 1 is a top elevational view of an integrated circuit package in accordance with one embodiment of the present invention. [0011]
  • FIG. 2 is a sectional view taken along line [0012] 2-2 in FIG. 1.
  • FIG. 3 is a top elevational view of a package substrate of the integrated circuit package shown in FIGS. 1 and 2. [0013]
  • FIG. 4 is a sectional view taken along line [0014] 4-4 in FIG. 3.
  • FIGS. [0015] 5A-5E illustrate a method of assembling the integrated circuit package of FIGS. 1 and 2 in accordance with one embodiment of the present invention.
  • FIG. 6 is sectional view similar to FIG. 5B illustrating one embodiment of the present invention in which both contact pads to be connected have a solder bump. [0016]
  • FIGS. [0017] 7A-7F illustrate an alternative method of assembling the integrated circuit package of FIGS. 1 and 2.
  • FIG. 8 is a top elevational view of an integrated circuit package in accordance with one alternative embodiment of the present invention. [0018]
  • FIG. 9 is a sectional view taken along line [0019] 9-9 in FIG. 8.
  • FIG. 10 is a top elevational view of a package substrate of the integrated circuit package shown in FIGS. 8 and 9. [0020]
  • FIG. 11 is a sectional view taken along line [0021] 11-11 in FIG. 10.
  • FIGS. [0022] 12A-12E illustrate a method of assembling the one alternative embodiment integrated circuit package of FIGS. 8 and 9.
  • FIG. 13 is sectional view similar to FIG. 12B illustrating one embodiment of the one alternative embodiment of the integrated circuit package in which both contact pads to be connected have a solder bump. [0023]
  • FIGS. [0024] 14A-14F illustrate an alternative method of assembling the integrated circuit package of FIGS. 8 and 9.
  • FIG. 15 is a sectional view of an integrated circuit package in accordance with one further embodiment of the present invention. [0025]
  • FIGS. [0026] 16A-16E illustrate a method of assembling the one further embodiment of the integrated circuit package of FIG. 15.
  • FIG. 17 is sectional view similar to FIG. 16B illustrating one further embodiment of the integrated circuit package in which both contact pads to be connected have a solder bump. [0027]
  • FIGS. [0028] 18A-18F illustrate an alternative method of assembling the integrated circuit package of FIG. 15.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • FIGS. 1 and 2 depict an integrated circuit package [0029] 10 in accordance with one preferred embodiment of the present invention. The integrated circuit package 10 includes a package substrate 12, a first integrated circuit (IC) die 14, such as an IC memory die, and a second IC die 16, such as a processor die. As seen best in FIGS. 2-4, the package substrate 12 includes an upper or first surface 18 and an opposite lower or second surface 20. The first surface 18 of the package substrate 12 defines a through opening 22 of the package substrate 12. As seen in FIG. 2, the through opening 22 of the package substrate 12 is sized to accommodate the first IC die 14. In particular, the length, width and depth dimensions of the recessed area 22 are sized to fully accommodate the length, width and height dimensions of the first IC die 14.
  • The first surface [0030] 18 of the package substrate surrounding the through opening 22 of the package substrate 12 includes a first land grid array of interconnection sites or first contact pads 26. The first surface 18 of the package substrate 12 also includes a second land grid array of interconnection sites or second contact pads 28 concentrically surrounding the first contact pads 26. The dashed line 30 in FIG. 3 depicts the dividing line between the first and second contacts pads 26, 28 on the first surface 18 of the package substrate 12.
  • As seen best in FIG. 2, the first IC die [0031] 14 includes a first surface 32 and an opposite second surface 34. The second surface 34 of the first IC die 14 includes a land grid array of interconnection sites or contact pads 38.
  • The second IC die [0032] 16 includes a lower or first surface 42 and an opposite upper or second surface 44. The first surface 42 of the second IC die 16 includes a first land grid array of interconnection sites or first contact pads 46. The first surface 42 of the second IC die 16 further includes a second land grid array of interconnection sites or second contact pads 48 concentrically surrounded by the first contact pads 46. Dashed lines 50 in FIG. 2 depict the dividing line between the first and second contacts pads 46, 48 on the first surface 42 of the second IC die 16. The first contact pads 46 of the second IC die 16 are electrically connected to the first contact pads 26 of the package substrate 12 by way of reflowed solder joints 52. The second contact pads 48 of the second IC die 16 are electrically connected to the contact pads 38 on the second surface 34 of the first IC die 14 by way of reflowed solder joints 54. As seen in FIGS. 1 and 2, in the assembled IC package 10, the first IC die 14 is positioned amid (i.e., between) the package substrate 12 and the second IC die 16. In particular, the first IC die 14 is positioned within the through opening 22 of the package substrate 12. The second contact pads 28 of the package substrate 12 are provided for the electrical connection of further components (not shown). Alternatively, the second contact pads 28 can take the form of traces that are connectable to other electronic components. In this alternative version, the IC package 10 could be in essence the main printed circuit board of an electronic component. In addition, although the contact pads 26, 28, 38, 46, 48 have been described as land grid arrays, the contact pads can take other forms, such as ball grid arrays.
  • Assembly of the integrated circuit package [0033] 10 (shown in FIGS. 1 and 2) in accordance with one preferred embodiment of the present invention is illustrated in FIGS. 5A-5E. FIG. 5A illustrates the package substrate 12, the first IC die 14 and the second IC die 16 of the integrated circuit package 10 at the start of the assembly process. In FIG. 5B solder bumps 58 and 60 have been deposited in a known manner on the first and second contact pads 46, 48, respectively, on the first surface 42 of the second IC die 16. In FIG. 5C, the first IC die 14 has been positioned (i.e., engaged) with the second IC die 16 such that the contact pads 38 of the first IC die 14 are substantially aligned with the second contact pads 48 (i.e., solder bumps 60) of the second IC die 16. The inherent tackiness of flux associated with the solder bumps 60 tends to hold the first IC die 14 on the second IC die 16. In addition, in FIG. 5C, the second IC die 16 is positioned (i.e., engaged) atop the package substrate 12 with the first IC die 14 positioned amid the package substrate 12 and the second IC die 16. In particular, the first IC die 14 is positioned within the through opening 22 of the package substrate 12. In this position, the first contact pads 46 (i.e., solder bumps 58) of the second IC die 16 are substantially aligned with the first contact pads 26 of the package substrate 12. In FIG. 5D, sufficient heat is applied to the IC package 10 (in a known manner) to simultaneously reflow the solder bumps 58, 60 to simultaneously create the reflowed solder joints 52, 54 thereby simultaneously electrically connecting together the package substrate 12, the second IC die 16 and the first IC die 14 and completing assembly of the IC package 10. It bears noting that the surface tension of the molten solder (particularly at the interface of the contact pads 38 of the first IC die 14 and the second contact pads 48 of the second IC die 16) tends to help align the package substrate 12, the first IC die 14 and the second IC die 16 if they are slightly misaligned before the reflow process step.
  • If desired, physical integrity of the IC package [0034] 10 can be optimized by underfilling, in a known manner, one or all gaps in the IC package with a suitable epoxy. For example as shown in FIG. 5E, epoxy 62 may be used to just underfill gaps between the second IC die 16 and the package substrate 12 at the first contact pads 46 of the second IC die 16 and the first contact pads 26 of the package substrate 12; or epoxies 62 and 63 can be used to underfill gaps between the second IC die 16 and the package substrate 12 at the first contact pads 46 of the second IC die 16 and the first contact pads 26 of the package substrate 12; and gaps between the first IC die 14 and the second IC die 16 at the contact pads 38 of the first IC die 14 and the second contact pads 48 of the second IC die 16.
  • Although, it has been described in connection with FIG. 5B, that the solder bumps [0035] 58, 60 are only deposited on the first and second contact pads 46, 48 of the second IC die 16, it is to be understood that alternatively the solder bumps could only be deposited on the first contact pads 26 of the package substrate 12, and on the contact pads 38 of the first IC die 14. As illustrated in FIG. 6, as a further alternative, solder bumps 64 can be applied to all of the contact pads 26, 28, 38, 46, 48. Moreover, as even a further alternative to solder bumps and flux, a solder paste can be employed.
  • Assembly of the integrated circuit package [0036] 10 (shown in FIGS. 1 and 2) in accordance with one alternative embodiment of the present invention is illustrated in FIGS. 7A-7F. The steps depicted in FIGS. 7A and 7B are identical to the steps previously described in connection with FIGS. 5A and 5B. In FIG. 7C, the first IC die 14 has been positioned (i.e., engaged) with the second IC die 16 such that the contact pads 38 of the first IC die 14 are substantially aligned with the second contact pads 48 (i.e., solder bumps 60) of the second IC die 16. Once again, the inherent tackiness of flux on the solder bumps 60 holds the first IC die 14 to the second IC die 16. In FIG. 7D, sufficient heat is applied to the IC package 10 to reflow the solder bumps 60 to create the reflowed solder joints 54 thereby electrically connecting together the second IC die 16 and the first IC die 14. In FIG. 7E, the second IC die 16 (with the first IC die 14 attached thereto) is been positioned (i.e., engaged) atop the package substrate 12 with the first IC die 14 positioned amid (i.e., between) the package substrate 12 and the second IC die 16 in the through opening 22. In this position, the first contact pads 46 (i.e., solder bumps 58) of the second IC die 16 are substantially aligned with the first contact pads 26 of the package substrate 12. In FIG. 7F, sufficient heat is applied to the IC package 10 to reflow the solder bumps 58 to create the reflowed solder joints 52 thereby electrically connecting the package substrate 12 to the previously assemble first and second IC dies 14, 16, thereby completing assembly of the IC package 10.
  • The physical integrity of the IC package [0037] 10 assembled with this alternative method can, if desired, be optimized by underfilling one or all gaps in the IC package with a suitable epoxy as previously discussed with regards to FIG. 5E. Likewise, the particular contact pads that have solder bumps deposited thereon can be varied as previously described above.
  • FIGS. 8 and 9 depict one alternative integrated circuit package [0038] 10 a. Parts in common with the preferred embodiment shown in FIGS. 1-7F are labeled with like numerals except for the inclusion of “a”. The integrated circuit package 10 a includes the package substrate 12 a, the first integrated circuit (IC) die 14 a, and the second IC die 16 a. As seen best in FIGS. 9-11, the first surface 18 a of the package substrate 12 a defines a recessed area 70 (instead of the through opening 22). The recessed area 70 of the package substrate 12 a is sized to accommodate the first IC die 14 a. In particular, the length, width and depth dimensions of the recessed area 70 are sized to fully accommodate the length, width and height dimensions of the first IC die 14 a. The first surface 18 a in the recessed area 70 of the package substrate 12 a includes a further land grid array of interconnection sites or further contact pads 24. The first contact pads 26 a concentrically surround the recessed area 70 and the further contact pads 24 therein.
  • As seen best in FIG. 9, the first surface [0039] 32 a includes a land grid array of interconnection sites or additional contact pads 36. The first IC die 14 a is positioned within the recessed area 70 of the package substrate 12 a, with the additional contact pads 36 of the first IC die 14 a electrically connected to the further contact pads 24 of the package substrate 12 a by way of reflowed solder joints 40. The reflowed solder joints 52 a connect the first contact pads 26 a of the package substrate 12 a to the first contact pads 46 a of the second IC die 16 a. In this embodiment, the contact pads 38 and 48 and the reflowed solder joints 54 of the embodiment of FIGS. 1-7F have been eliminated and the first IC die 14 a is electrically connected to the second IC die 16 a through the package substrate 12 a.
  • Assembly of the one alternative embodiment integrated circuit package [0040] 10 a (shown in FIGS. 8 and 9) in accordance with one embodiment of the present invention is illustrated in FIGS. 12A-12E. FIG. 12A illustrates the package substrate 12 a, the first IC die 14 a and the second IC die 16 a of the integrated circuit package 10 a at the start of the assembly process. In FIG. 12B solder bumps 56 have been deposited on the additional contact pads 36 on the first surface 32 a of the first IC die 14 a, and the solder bumps 58 a have been deposited on the contact pads 46 a on the first surface 42 a of the second IC die 16 a. In FIG. 12C, the first IC die 14 a has been positioned (i.e., engaged) in the recessed area 70 of the package substrate 12 a such that the first contact pads 36 (i.e., solder bumps 56) of the first IC die 14 are substantially aligned with the first contact pads 24 of the package substrate 12 a. Likewise the second IC die 16 a has been positioned (i.e., engaged) atop the package substrate 12 a with the first IC die 14 a positioned between the package substrate 12 a and the second IC die 16 a and in the recessed area 70. In this position, the first contact pads 46 a (i.e., solder bumps 58 a) of the second IC die 16 a are substantially aligned with the first contact pads 26 a of the package substrate 12 a. In FIG. 12D, sufficient heat is applied to the IC package 10 to simultaneously reflow the solder bumps 56, 58 a to simultaneously create the reflowed solder joints 40, 52 a thereby simultaneously electrically connecting together the package substrate 12 a, the first IC die 14 a and the second IC die 16 a and completing assembly of the IC package 10.
  • If desired, physical integrity of the IC package [0041] 10 a can be optimized by underfilling one or all gaps in the IC package with a suitable epoxy 62 a, 63 a (FIG. 12E). Moreover, the particular contact pads that include the solder bumps can be varied as previously described. For example, as illustrated in FIG. 13, as a further alternative, solder bumps 64 a can be applied to all of the contact pads 24, 26, 28, 36, 46.
  • Assembly of the one alternative integrated circuit package [0042] 10 a (shown in FIGS. 8 and 9) in accordance with one alternative embodiment of the present invention is illustrated in FIGS. 14A-14F. The steps depicted in FIGS. 14A and 14B are identical to the steps previously described in connection with FIGS. 12A and 12B. In FIG. 14C, the first IC die 14 a has been positioned (i.e., engaged) in the recessed area 70 of the package substrate 12 a such that the additional contact pads 36 (i.e., solder bumps 56) of the first IC die 14 a are substantially aligned with the further contact pads 24 of the package substrate 12 a. In FIG. 14D, sufficient heat is applied to the IC package 10 a to reflow the solder bumps 56 to create the reflowed solder joints 40 thereby electrically connecting together the package substrate 12 a and the first IC die 14 a. In FIG. 14E, the second IC die 16 a has been positioned (i.e., engaged) atop the package substrate 12 a with the first IC die 14 a positioned between the package substrate 12 a and the second IC die 16 a and in the recessed area 70. In this position, the first contact pads 46 a (i.e., solder bumps 58 a) of the second IC die 16 a are substantially aligned with the second contact pads 26 a of the package substrate 12 a. In FIG. 14F, sufficient heat is applied to the IC package 10 a to reflow the solder bumps 58 a to create the reflowed solder joints 52 a thereby electrically connecting the package substrate 12 a to the previously assembled first and second IC dies 14 a, 16 a, thereby completing assembly of the IC package 10.
  • FIG. 15 depicts one further embodiment integrated circuit package [0043] 10 b. The integrated circuit package 1 b is a combination of integrated circuit package 10 (FIGS. 1-7F) and integrated circuit package 10 a (FIGS. 8-14F). As such like parts are labeled with like numerals except for the inclusion of “b”. The integrated circuit package 10 b includes the package substrate 12 b, the first integrated circuit (IC) die 14 b, and the second IC die 16 b. The first surface 18 b of the package substrate 12 b includes the recessed area 70 b sized to accommodate the first IC die 14 b.
  • The first surface [0044] 18 b in the recessed area 70 b includes the further contact pads 24 b. The first surface 18 b of the package substrate 12 b also includes the first contact pads 26 b and the second contact pads 28 b. The first surface 32 b of the first IC die 14 b includes the additional contact pads 36 b, while the second surface 34 b of the first IC die 14 b includes the contact pads 38 b. The first surface 42 b of the second IC die 16 b includes the first and second contact pads 46 b, 48 b. The first IC die 14 b is positioned within the recessed area 70 b of the package substrate 12 b, with the additional contact pads 36 b of the first IC die 14 b electrically connected to the further contact pads 24 b of the package substrate 12 b by way of the reflowed solder joints 40 b. The first contact pads 46 b are electrically connected to the first contact pads 26 b of the package substrate 12 b by way of the reflowed solder joints 52 b. The second contact pads 48 b are electrically connected to the contact pads 38 b of the first IC die 14 b by way of reflowed solder joints 54 b.
  • Assembly of the integrated circuit package [0045] 10 b (shown in FIG. 15) in accordance with one embodiment is illustrated in FIGS. 16A-16E. FIG. 16A illustrates the package substrate 12 b, the first IC die 14 b and the second IC die 16 b of the integrated circuit package 10 b at the start of the assembly process. In FIG. 16B solder bumps 56 b have been deposited on the additional contact pads 36 b on the first surface 32 b of the first IC die 14 b, and solder bumps 58 b and 60 b have been deposited on the first and second contact pads 46 b, 48 b, respectively, on the first surface 42 b of the second IC die 16 b. In FIG. 16C, the first IC die 14 b has been positioned (i.e., engaged) in the recessed area 70 b of the package substrate 12 b such that the additional contact pads 36 b (i.e., solder bumps 56 b) of the first IC die 14 b are substantially aligned with the further contact pads 24 b of the package substrate 12 b. Likewise the second IC die 16 b is positioned (i.e., engaged) atop the package substrate 12 b with the first IC die 14 b positioned between the package substrate 12 b and the second IC die 16 b and in the recessed area 70 b. In this position, the first contact pads 46 b (i.e., solder bumps 58 b) of the second IC die 16 b are substantially aligned with the first contact pads 26 b of the package substrate 12 b, and the second contact pads 48 b (i.e., solder bumps 60 b) of the second IC die 16 b are substantially aligned with the contact pads 38 b on the second surface 34 b of the first IC die 14 b. In FIG. 16D, sufficient heat is applied to the IC package 10 b to simultaneously reflow the solder bumps 56 b, 58 b, 60 b to simultaneously create the reflowed solder joints 40 b, 52 b, 54 b thereby simultaneously electrically connecting together the package substrate 12 b, the first IC die 14 b and the second IC die 16 b and completing assembly of the IC package 10 b.
  • If desired, physical integrity of the IC package [0046] 10 b can be optimized by underfilling one or all gaps in the IC package with a suitable epoxy 62, 63 b (FIG. 16E). Moreover, the particular contact pads having the solder bumps can be varied as previously described. For example, as illustrated in FIG. 17, as a further alternative, solder bumps 64 b can be applied to all of the contact pads 24 b, 26 b, 28 b, 36 b, 38 b, 46 b, 48 b.
  • Assembly of the integrated circuit package [0047] 10 b (shown in FIG. 15) in accordance with one alternative embodiment of the present invention is illustrated in FIGS. 18A-18F. The steps of FIGS. 18A and 18B are identical to FIGS. 16A and 16B. In FIG. 18C, the first IC die 14 b has been positioned (i.e., engaged) in the recessed area 70 b of the package substrate 12 b such that the additional contact pads 36 b (i.e., solder bumps 56 b) are substantially aligned with the further contact pads 24 b. In FIG. 18D, sufficient heat is applied to the IC package 10 b to reflow the solder bumps 56 b to create the reflowed solder joints 40 b thereby electrically connecting together the package substrate 12 b and the first IC die 14 b. In FIG. 18E, the second IC die 16 b is been positioned (i.e., engaged) atop the package substrate 12 b with the first IC die 14 b positioned between the package substrate 12 b and the second IC die 16 b in the recessed area 70 b. In this position, the first contact pads 46 b (i.e., solder bumps 58 b) of the second IC die 16 b are substantially aligned with the first contact pads 26 b of the package substrate 12 b, and the second contact pads 48 b (i.e., solder bumps 60 b) of the second IC die 16 b are substantially aligned with the contact pads 38 b on the second surface 34 b of the first IC die 14 b. In FIG. 18F, sufficient heat is applied to the IC package 10 b to simultaneously reflow the solder bumps 58 b, 60 b to simultaneously create the reflowed solder joints 52 b, 54 b thereby electrically connecting the second IC die 16 b to the previously assemble package substrate 12 b and first IC die 14 b, thereby completing assembly of the IC package 10 b.
  • This integrated circuit package [0048] 10, 10 a, 10 b assembled using flip-chip bonding techniques has low interconnect capacitance, thereby improving signal speed and substantially eliminating the need for off chip driver cells between the first and second IC dies. Moreover the assembly process of the integrated circuit package 10, 10 a, 10 b is amenable to high volume low defect manufacturing.
  • Although the present invention has been described with reference to preferred embodiments, workers skilled in the art will recognize that changes may be made in form and detail without departing from the spirit and scope of the invention. [0049]

Claims (25)

What is claimed is:
1. An integrated circuit package comprising:
a package substrate having a first surface including a first array of interconnection sites, and a second array of interconnection sites;
a first integrated circuit die having a first surface including an array of interconnection sites electrically connected to the second array of interconnection sites of the package substrate; and
a second integrated circuit die having a first surface including an array of interconnection sites electrically connected to the first array of interconnection sites of the package substrate, wherein the first integrated circuit die is positioned amid the package substrate and the second integrated circuit die.
2. The integrated circuit package of claim 1 wherein the package substrate defines a recessed area sized to accommodate the first integrated circuit die, the recessed area including the second array of interconnection sites.
3. The integrated circuit package of claim 1 wherein the first array of interconnection sites of the package substrate is electrically connected to the array of interconnection sites of the second integrated circuit die by reflowed solder.
4. The integrated circuit package of claim 1 wherein the second array of interconnection sites of the package substrate is electrically connected to the array of interconnection sites of the first integrated circuit die by reflowed solder.
5. The integrated circuit package of claim 1 wherein gaps between the second integrated circuit die and the package substrate at the first array of interconnection sites of the package substrate and the array of interconnection sites of the second integrated circuit die are underfilled with epoxy.
6. The integrated circuit package of claim 5 wherein gaps between the first integrated circuit die and the package substrate at the array of interconnection sites of the first integrated circuit die and the second array of interconnection sites of the package substrate are underfilled with epoxy.
7. The integrated circuit package of claim 1 wherein the first integrated circuit die has a second surface opposite the first surface, with the second surface of the first integrated circuit die having an additional array of interconnection sites, wherein the first surface of the second integrated circuit die includes a further array of interconnection sites that is different than the array of interconnection sites of the first surface of the second integrated circuit die, and wherein the further array of interconnection sites of the second integrated circuit die is electrically connected to the additional array of interconnection sites on the second surface of the first integrated circuit die.
8. The integrated circuit package of claim 7 wherein the first array of interconnection sites of the package substrate is electrically connected to the array of interconnection sites on the first surface of the second integrated circuit die by reflowed solder, wherein the second array of interconnection sites of the package substrate is electrically connected to the array of interconnection sites on the first surface of the first integrated circuit die by reflowed solder, and wherein the further array of interconnection sites of the second integrated circuit die is electrically connected to the additional array of interconnection sites on the second surface of the first integrated circuit die by reflowed solder.
9. The integrated circuit package of claim 7 wherein the package substrate defines a recessed area sized to accommodate the first integrated circuit die, the recessed area including the second array of interconnection sites.
10. The integrated circuit package of claim 1 wherein the first surface of the package substrate includes an auxiliary array of interconnection sites that is different than the first and second arrays of interconnection sites of the package substrate.
11. The integrated circuit package of claim 1 wherein the first integrated circuit die is a memory die.
12. The integrated circuit package of claim 1 wherein the second integrated circuit die is a processor die.
13. A method of assembling an integrated circuit package comprising:
providing a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites;
engaging a first integrated circuit die with the package substrate such that an array of interconnection sites on a first surface of the first integrated circuit die are substantially aligned with the second array of interconnection sites of the package substrate;
engaging a second integrated circuit die with the package substrate such that an array of interconnection sites on a first surface of the second integrated circuit die are substantially aligned with the first array of interconnection sites of the package substrate, with the first integrated circuit die positioned amid the package substrate and the second integrated circuit die; and
simultaneously electrically connecting the first array of interconnection sites to the array of interconnection sites of the second integrated circuit die, and the second array of interconnection sites to the array of interconnection sites of the first integrated circuit die.
14. The method of claim 13 wherein the package substrate defines a recessed area that includes the second array of interconnection sites, and wherein the step of engaging the first integrated circuit die with the package substrate includes:
positioning the first integrated circuit die within the recessed area of the package substrate.
15. The method of claim 13 wherein the step of simultaneously electrically connecting the first array of interconnection sites to the array of interconnection sites of the second integrated circuit die, and the second array of interconnection sites to the array of interconnection sites of the first integrated circuit die includes:
simultaneously reflowing solder between the first array of interconnection sites and the array of interconnection sites of the second integrated circuit die, and between the second array of interconnection sites and the array of interconnection sites of the first integrated circuit die.
16. The method of claim 13 wherein the step of engaging the second integrated circuit die with the package substrate includes:
aligning a further array of interconnection sites on the first surface of the second integrated circuit die that is different than the array of interconnection sites on the first surface of the second integrated circuit die with an additional array of interconnection sites on a second surface of the first integrated circuit die that is opposite the first surface of the first integrated circuit die.
17. The method of claim 16 wherein the package substrate defines a recessed area that includes the second array of interconnection sites, and wherein the step of engaging the second integrated circuit die with the package substrate further includes:
positioning the first integrated circuit die within the recessed area of the package substrate such that the additional array of interconnection sites on the second surface of the first integrated circuit die is substantially aligned with the further array of interconnection sites of the second integrated circuit die.
18. The method of claim 16 wherein the step of simultaneously electrically connecting the second array of interconnection sites to the array of interconnection sites of the first integrated circuit die, and the first array of interconnection sites to the array of interconnection sites of the second integrated circuit die includes:
simultaneously electrically connecting the further array of interconnection sites of the second integrated circuit die to the additional array of interconnection sites on the second surface of the first integrated circuit die.
19. The method of claim 18 wherein the step of simultaneously electrically connecting the second array of interconnection sites to the array of interconnection sites of the first integrated circuit die, the first array of interconnection sites to the array of interconnection sites of the second integrated circuit die, and the further array of interconnection sites of the integrated circuit die to the additional array of interconnection sites on the second surface of the first integrated circuit die includes:
simultaneously reflowing solder between the second array of interconnection sites and the array of interconnection sites of the first integrated circuit die, between the first array of interconnection sites and the array of interconnection sites of the second integrated circuit die, and between the further array of interconnection sites of the second integrated circuit die and the additional array of interconnection sites on the second surface of the first integrated circuit die.
20. A method of assembling an integrated circuit package comprising:
providing a package substrate having a first surface including a first array of interconnection sites and a second array of interconnection sites;
engaging a first integrated circuit die with the package substrate such that an array of interconnection sites on a first surface of the first integrated circuit die are substantially aligned with the second array of interconnection sites of the package substrate;
electrically connecting the second array of interconnection sites to the array of interconnection sites of the first integrated circuit die;
engaging a second integrated circuit die with the package substrate such that an array of interconnection sites on a first surface of the second integrated circuit die are substantially aligned with the first array of interconnection sites of the package substrate, with the first integrated circuit die positioned amid the package substrate and the second integrated circuit die; and
electrically connecting the first array of interconnection sites to the array of interconnection sites of the second integrated circuit die.
21. The method of claim 20 wherein the step of electrically connecting the second array of interconnection sites to the array of interconnection sites of the first integrated circuit die includes:
reflowing solder between the second array of interconnection sites and the array of interconnection sites of the first integrated circuit die.
22. The method of claim 21 wherein the step of electrically connecting the first array of interconnection sites to the array of interconnection sites of the package substrate includes:
reflowing solder between the first array of interconnection sites and the array of interconnection sites of the package substrate.
23. The method of claim 20 wherein the step of engaging the second integrated circuit die with the package substrate includes:
engaging a further array of interconnection sites on the first surface of the second integrated circuit die that is different than the array of interconnection sites on the first surface of the second integrated circuit die with an additional array of interconnection sites on a second surface of the first integrated circuit die that is opposite the first surface of the first integrated circuit die.
24. The method of claim 23, and further including:
electrically connecting the further array of interconnection sites of the second integrated circuit die to the additional array of interconnection sites on the second surface of the first integrated circuit die.
25. The method of claim 24 wherein the step of electrically connecting the further array of interconnection sites of the second integrated circuit die to the additional array of interconnection sites on the second surface of the first integrated circuit die includes:
reflowing solder between the further array of interconnection sites of the second integrated circuit die and the additional array of interconnection sites on the second surface of the first integrated circuit die.
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