US20030205753A1 - Non-volatile semiconductor memory device - Google Patents

Non-volatile semiconductor memory device Download PDF

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US20030205753A1
US20030205753A1 US10/454,316 US45431603A US2003205753A1 US 20030205753 A1 US20030205753 A1 US 20030205753A1 US 45431603 A US45431603 A US 45431603A US 2003205753 A1 US2003205753 A1 US 2003205753A1
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layer
silicon nitride
floating gate
silicon oxide
oxide layer
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Seiichi Mori
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Toshiba Corp
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Toshiba Corp
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Priority to US10/454,316 priority Critical patent/US20030205753A1/en
Publication of US20030205753A1 publication Critical patent/US20030205753A1/en
Priority to US10/933,035 priority patent/US7101749B2/en
Priority to US11/458,330 priority patent/US20060244046A1/en
Priority to US11/458,324 priority patent/US20060249781A1/en
Priority to US11/458,317 priority patent/US20060249780A1/en
Priority to US12/049,148 priority patent/US7479430B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation

Definitions

  • the present invention relates to a non-volatile semiconductor memory device including a memory cell having a stacked gate structure.
  • a non-volatile semiconductor memory device uses a memory cell structure on which a floating gate is provided through a tunnel insulating layer on a semiconductor substrate, and a control gate is stacked thereon through an inter-layer insulating layer.
  • the inter-layer insulating layer of this memory cell normally involves the use of a so-called ONO (Oxide-Nitride-Oxide) structure composed of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer.
  • ONO Oxide-Nitride-Oxide
  • FIGS. 4A and 4B show sections, taken in two directions orthogonal to each other, of the memory cell structure described above. Normally in a flash memory, the control gate of the a plurality of memory cells are consecutively arranged and serve as word lines.
  • FIG. 4A is the section in the direction parallel to a direction of the word line.
  • An element isolation insulating layer 2 is provided on a p-type silicon substrate 1 , and a floating gate 4 is provided through a tunnel insulating layer 3 on a device region defined by the element isolation insulating layer 2 .
  • a floating gate 4 is provided through a tunnel insulating layer 3 on a device region defined by the element isolation insulating layer 2 .
  • an ONO layer 5 is provided on the floating gate 4 as an inter-layer insulating layer including a silicon oxide layer 5 a , a silicon nitride layer 5 b and a silicon oxide layer 5 c which are stacked in this sequence.
  • a control gate 6 is provided on the ONO layer 5 .
  • Source/drain diffused layers 7 , 8 are provided in self-alignment with the control gate 6 .
  • the ONO layer 5 functions to prevent electric charges accumulated in the floating gate 3 from leaking out during a writing process to the memory cell, and, because of a necessity for confining the electric charges within the floating gate 4 over a long period of time, is required to exhibit a high insulating property.
  • the floating gate retains electrons. In an electron accumulating state, however, a comparatively weak electric field (a self electric field) generated by the electrons is applied to the ONO layer 5 .
  • Te silicon oxide layer 5 a on the side of the floating gate 4 , of the ONO layer 5 , if a layer thickness thereof is 5-6 nm, works as a Fowler-Nordheim type tunnel current conductive mechanism, wherein the electric current flowing with a low electric field is extremely small. Further, a barrier height of the silicon oxide layer 5 a with respect to silicon is as high as 3.2 eV. Accordingly, if the silicon oxide layer 5 has no defect and there is no electric field enhancement effect based on a two-dimensional configuration of the floating gate 4 , only the silicon oxide layer 5 a must be capable of sufficiently retaining the electrons for a long time. In fact, however, there exist the defect and the two-dimensional electric field enhancement effect, and hence the ONO layer is used.
  • the two-dimensional electric field enhancement effect is typified by, for example, as indicated by a broken line A in FIG. 4A, an electric field enhancement at an edge which is obtained by forming the floating gate 4 in pattern.
  • an electric field enhancement caused by a rugged area formed on the surface of the floating gate 4 when the silicon oxide layer 5 a is formed by thermal oxidation.
  • the silicon nitride layer 5 b of the ONO layer 5 contains much of trap level, and trapping occurs even when the electric current flows due to the electric field enhancement and acts to relieve the electric field, thereby restraining a leak of the electric charges from the oxide layer 5 a surrounding the floating gate. If the oxide layer 5 a has a defect, the same mechanism works. This is the reason why the silicon nitride layer 5 b is used.
  • the upper and lower silicon oxide layers 5 a , 5 c of the ONO layer 5 are each required to have a thickness of 5-6 nm for exhibiting functions of relieving the electric field and preventing the leak.
  • the silicon nitride layer 5 b has a thickness on the order of 10 nm (converted into 5 nm in the case of the oxide layer). Hence, an equivalent oxide thickness of the ONO layer 5 is 15-16 nm thick.
  • the memory cell it is desirable for enabling the memory cell to operate at a low voltage that a capacitance coupling between the control gate and the floating gate be large. It is desirable for attaining this that the ONO layer be as thin as possible. If the layer thickness is thinned down to a limit thereof, it can be thinned totally down to approximately 14 nm as an equivalent oxide thickness.
  • a bird's beak B intrudes in a portion between the floating gate 4 and the control gate 6 from a side surface.
  • the bird's beak decreases the capacitance coupling between the control gate 6 and the floating gate 4 .
  • the silicon oxide layer 5 a disposed directly on the floating gate is provided by a CVD (Chemical vapor Deposition) method, a characteristic of density thereof is inferior to a thermal oxide layer, and hence oxygen diffuses fast within the layer, with the result that a large bird's beak occurs.
  • the silicon oxide layer formed by the CVD method might be used more often than by the thermal oxidation, and therefore, in such a case, the intrusion of the bird's beak turns out a problem.
  • a silicon nitride layer having a trap level density well lower than that of a silicon nitride layer formed by a normal CVD (Chemical Vapor Deposition), especially LPCVD (Low Pressure Chemical Vapor Deposition) method is provided in the inter-layer insulating layer, whereby a large capacitance coupling between a control gate and a floating gate can be ensured by making an effective thickness of an oxide layer smaller than in the prior art while exhibiting an electric field relieving effect and a lead reducing effect.
  • CVD Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • FIGS. 1A and 1B are sectional views each showing a memory cell structure in a first embodiment of the present invention
  • FIG. 2 is a sectional view showing a memory cell structure in a second embodiment of the present invention.
  • FIGS. 3 A- 3 D are sectional views showing a structure of an inter-layer insulating layer of the memory cell in a third embodiment of the present invention.
  • FIGS. 4A and 4B are sectional views each showing a memory cell structure of a non-volatile memory in the prior art.
  • FIGS. 1A and 1B are sectional views taken indirection orthogonal to each other, showing a memory cell structure of a non-volatile semiconductor memory device in a first embodiment of the present invention.
  • An element isolation insulating layer 12 is provided on a p-type silicon substrate 11 , and a floating gate 14 composed of a polycrystalline silicon layer is provided through a tunnel insulating layer 13 on a device area defined by the element isolation insulating layer 12 .
  • the tunnel insulating layer 13 is classified as a silicon oxide layer.
  • a control gate 16 composed of a polycrystalline silicon layer is stacked on the floating gate 14 via an inter-layer insulating layer 15 .
  • Source/drain diffused layers 17 , 18 are so provided on the substrate as to be self-aligned with the control gate 16 .
  • the inter-layer insulating layer 15 includes a silicon oxide layer 15 a contiguous to the floating gate 14 , and double-layered silicon nitride layers 15 b , 15 c provided thereon.
  • the first silicon nitride layer 15 b is provided by a normal CVD method, especially low pressure (LP) CVD method
  • the second silicon nitride layer 15 c is provided by a JVD (Jet Vapor Deposition) method.
  • the second silicon nitride layer 15 c is well lower in trap level density than the first silicon nitride layer 15 b and has a less leak current at a low electric field region.
  • the silicon oxide layer 15 a is a thermal oxide layer obtained by thermally oxidating the floating gate 14 , or a silicon oxide layer based on the LPCVD method.
  • the first silicon nitride layer 15 b is formed by the LPCVD method, wherein dichlorosilane (SiH 2 Cl 2 ) and ammonia (NH 4 ) are used as raw gases.
  • the second silicon nitride layer 15 c is formed such that active Si and N are generated by plasma-decomposing a silane-series gas (e.g., SiH 4 ) supplied together with a carrier gas such as He etc.
  • a silane-series gas e.g., SiH 4
  • a quantity of hydrogen content of the first silicon nitride layer 15 b deposited by the LPCVD method is 10 21 /cm 3 or more, while a quantity of hydrogen content of the second silicon nitride layer 15 c deposited by the JVD method is 10 19 /cm 3 or less.
  • This difference in quantity of hydrogen content therebetween correlates to magnitudes of the trap level densities of those two layers, and, in other words, the silicon nitride layer having a less quantity of hydrogen content, which is deposited by the JVD method, exhibits a low trap level density and has a smaller leak current at the low electric field region.
  • silicon nitride layers deposited by other deposition methods may also be used on condition that those layers have a quantity of hydrogen content which is as small as the silicon nitride layer deposited by the JVD method, and exhibit a low trap level density.
  • the silicon nitride layer 15 a In the single layer 15 c of the silicon nitride layer deposited by the JVD method, Frenkel-Poole type current, though not so much as the silicon nitride layer deposited by the LPCVD method, flows across the low electric field region, and hence this layer 15 is hard to be used solely as an inter-layer insulating layer. Further, the silicon nitride layer has a lower barrier height with respect to silicon than the silicon oxide layer, and is therefore insufficient as a barrier against a release of the electrons from the floating gate. Accordingly, it is required for forming the inter-layer insulating layer that the silicon oxide layer 15 a be disposed just on, e.g., the floating gate 14 . The silicon oxide layer 15 a requires a thickness on the order of 5-6 nm for keeping a sufficient dielectric strength.
  • This first silicon nitride layer 15 b provided based on the LPCVD method is needed for preventing the lead as well as for obtaining the electric field relieving effect. That is, the first silicon nitride layer 15 b exhibits a high trap density and a Frenkel-Poole type electric conductive characteristic. In this Frenkel-Poole type electric conduction, the current in a high electric field region is small, and the current becomes hard to flow through a layer containing a trap because of the carriers being trapped even when the current flows therethrough at an initial stage. Therefore, the first silicon nitride layer 15 b restrains an increase in the leak current due to the electric field enhancement at the edge taking a two-dimensional configuration of the floating gate 14 .
  • the thickness of the silicon nitride layer 15 b be over 6 nm. It is also preferable for ensuring a large capacitance coupling that the above thickness be under 10 nm, to be specific, on the order of 8 nm.
  • the second silicon nitride layer 15 c based on the JVD method functions to restrain the hole implantation from the control gate 16 .
  • the first silicon nitride layer 15 b based on the LPCVD method is easy to flow the Frenkel-Poole type Hall current. If the silicon nitride layer 15 b is contiguous directly to the control gate 6 , as described above, the large leak current flows due to the hole implantation from the control gate 16 in such an operation mode that the control gate 16 comes to have a positive bias.
  • the second silicon nitride layer 15 c based on the JVD method has an extremely low trap density and effectively restrains the hole implantation from the control gate 16 .
  • the second silicon nitride layer 15 c be over 6 nm thick. It is also preferable for ensuring a large capacitance coupling that the thickness thereof be under 10 nm.
  • the thickness of the silicon oxide layer 15 a is set to 6 nm, and the thicknesses pf the silicon nitride layers 15 a , 15 b are each set to 6 nm (3 nm in the conversion of the oxide layer), and the effective thickness of the oxide layer is 12 nm. Accordingly, the layer can be made thinner than in a case of using the conventional ONO structure, and besides the sufficient electric field relieving effect can be obtained.
  • the silicon nitride layer 15 c is the uppermost layer of the inter-layer insulating layer 15 , and therefore it is feasible to restrain the intrusion of the bird's beak when effecting the post-oxidation.
  • FIG. 2 shows, corresponding to FIG. 1B, a memory cell structure in a second embodiment of the present invention.
  • the inter-layer insulating layer 15 is double-layered including two layers, i.e., from the side of the floating gate 14 , the silicon oxide layer 15 a and the silicon nitride layer 15 c based on the JVD method which has a low trap density and a hydrogen content quantity on the order of 10 19 /cm 3 or less.
  • the silicon nitride layer 15 b based on the LPCVD method and exhibiting the Frenkel-Poole type conduction is disposed in the middle of the interlayer-insulating layer 15 . If not operated with a high electric field, however, the silicon nitride layer 15 b is not necessarily used. Namely, as shown in FIG. 2, for the purpose of blocking a defect in the lowermost silicon oxide layer 15 a , the insulating layer may take a double-layered structure consisting of the silicon oxide layer 15 a ad the silicon nitride layer 15 c based on the JVD method and exhibiting the low trap density.
  • the silicon nitride layer formed by the JVD method and having a hydrogen content quantity on the order of 10 19 /cm 3 or less is provided keeping its thickness as thin as approximately 3 nm directly on the floating gate (i.e., the lowermost layer of the inter-layer insulating layer) or just under the control gate (viz., the uppermost layer of the inter-layer insulating layer). If a layer based on the normal LPCVD method and exhibiting a high trap density is used as this silicon nitride layer, a threshold value of the memory cell might become unstable due to the trap and release of the electric charges within the layer. If the silicon nitride layer deposed by the JVD method and having a low trap density is used, however, the instability of the threshold value never occurs.
  • FIGS. 3 A- 3 D show an extraction of only the structure of the inter-layer insulating layer in the third embodiment.
  • FIG. 3A shows an example in which a silicon nitride layer 15 d based on the JVD method is added as a layer contiguous to the floating gate 14 to a structure of the inter-layer insulating layer 15 in FIG. 15.
  • a similar silicon nitride layer 15 c serving as a layer contiguous to the control gate 16 is also provided, and the silicon oxide layer 15 a is interposed between the nitride layers 15 c and 15 d , thereby structuring the inter-layer insulating layer 15 .
  • FIG. 3B shows an example in which the silicon nitride layer 15 d formed by the JVD method is likewise added as a layer contiguous to the floating gate 14 to the structure of the inter-layer insulating layer 15 in FIG. 1.
  • the similar silicon nitride layer 15 c serving as a layer contiguous to the control gate 16 is also provided, and a stacked layer of the silicon oxide layer 15 a and the silicon nitride layer 15 b formed by the LPCVD method, is interposed between the nitride layers 15 c and 15 d.
  • FIG. 3C shows an example in which the silicon nitride layer 15 d formed by the JVD method is likewise added as a layer contiguous to the floating gate 14 to a normal-ONO-structured inter-layer insulating layer 150 . More specifically, the stacked layer 150 consisting of the silicon oxide layer, the silicon nitride layer based on the LPCVD method and the silicon oxide layer, is superposed further on the silicon nitride layer 15 d.
  • FIG. 3D shows an example in which silicon nitride, layers 15 d , 15 e formed by the JVD method are stacked as layers contiguous to the floating gate 14 and the control gate 16 , on the normal NON-structured inter-layer insulating layer 150 . That is, the silicon nitride layer 15 e is superposed further on the NON structured inter-layer insulating layer 150 .
  • the third embodiment also exhibits the same effects.
  • the silicon nitride layer having the trap level that is well lower than that of the silicon nitride layer based on the normal LPCVD method is provided in the inter-layer insulating layer of the non-volatile memory cell having the stacked gate structure, whereby the large capacitance coupling between the control gate and the floating gate can be ensured by making the effective thickness of the oxide layer smaller than in the priori art while exhibiting the electric field relieving effect and the effect of reducing the leak.

Abstract

A non-volatile semiconductor memory device according to the present invention has a semiconductor substrate and a memory cell having a floating gate provided through a tunnel insulating layer on the semiconductor substrate, and a control gate provided through an inter-layer insulting layer on said floating gate. The inter-insulating layer includes a silicon oxide layer contiguous to said floating gate, a first silicon nitride layer provided by a CVD method on the silicon oxide layer and a second silicon nitride layer provided on said first silicon nitride layer and having a lower trap density than that of the first silicon nitride layer. The inter-insulating layer may includes a silicon oxide layer contiguous to said floating gate and a silicon oxide layer deposited on said silicon oxide layer and having a quantity of hydrogen content on the order of 1019/cm3 or less. The inter-insulating layer also may includes a silicon oxide layer serving as a layer contiguous to at least one of the floating gate and the control gate, and having a lower trap density than that of a silicon nitride layer formed by a CVD method.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to a non-volatile semiconductor memory device including a memory cell having a stacked gate structure. [0002]
  • 2. Description of the Background Art [0003]
  • What has hitherto been known as a non-volatile semiconductor memory device uses a memory cell structure on which a floating gate is provided through a tunnel insulating layer on a semiconductor substrate, and a control gate is stacked thereon through an inter-layer insulating layer. The inter-layer insulating layer of this memory cell normally involves the use of a so-called ONO (Oxide-Nitride-Oxide) structure composed of a silicon oxide layer, a silicon nitride layer and a silicon oxide layer. [0004]
  • FIGS. 4A and 4B show sections, taken in two directions orthogonal to each other, of the memory cell structure described above. Normally in a flash memory, the control gate of the a plurality of memory cells are consecutively arranged and serve as word lines. FIG. 4A is the section in the direction parallel to a direction of the word line. [0005]
  • An element isolation insulating layer [0006] 2 is provided on a p-type silicon substrate 1, and a floating gate 4 is provided through a tunnel insulating layer 3 on a device region defined by the element isolation insulating layer 2. Provided on the floating gate 4 is an ONO layer 5 as an inter-layer insulating layer including a silicon oxide layer 5 a, a silicon nitride layer 5 b and a silicon oxide layer 5 c which are stacked in this sequence. Further, a control gate 6 is provided on the ONO layer 5. Source/drain diffused layers 7, 8 are provided in self-alignment with the control gate 6.
  • The [0007] ONO layer 5 functions to prevent electric charges accumulated in the floating gate 3 from leaking out during a writing process to the memory cell, and, because of a necessity for confining the electric charges within the floating gate 4 over a long period of time, is required to exhibit a high insulating property. In the normal flash memory, the floating gate retains electrons. In an electron accumulating state, however, a comparatively weak electric field (a self electric field) generated by the electrons is applied to the ONO layer 5.
  • Te [0008] silicon oxide layer 5 a, on the side of the floating gate 4, of the ONO layer 5, if a layer thickness thereof is 5-6 nm, works as a Fowler-Nordheim type tunnel current conductive mechanism, wherein the electric current flowing with a low electric field is extremely small. Further, a barrier height of the silicon oxide layer 5 a with respect to silicon is as high as 3.2 eV. Accordingly, if the silicon oxide layer 5 has no defect and there is no electric field enhancement effect based on a two-dimensional configuration of the floating gate 4, only the silicon oxide layer 5 a must be capable of sufficiently retaining the electrons for a long time. In fact, however, there exist the defect and the two-dimensional electric field enhancement effect, and hence the ONO layer is used.
  • The two-dimensional electric field enhancement effect is typified by, for example, as indicated by a broken line A in FIG. 4A, an electric field enhancement at an edge which is obtained by forming the floating gate [0009] 4 in pattern. Further, there is an electric field enhancement caused by a rugged area formed on the surface of the floating gate 4 when the silicon oxide layer 5 a is formed by thermal oxidation. The silicon nitride layer 5 b of the ONO layer 5 contains much of trap level, and trapping occurs even when the electric current flows due to the electric field enhancement and acts to relieve the electric field, thereby restraining a leak of the electric charges from the oxide layer 5 a surrounding the floating gate. If the oxide layer 5 a has a defect, the same mechanism works. This is the reason why the silicon nitride layer 5 b is used.
  • Incidentally, when the memory cell operates, and when in a state of the electrons being held by the floating gate, a positive bias is applied to the [0010] control gate 6. It is known that a large leak current flows to the silicon nitride layer through the trap level by a hole conduction. Accordingly, supposing that the control gate 6 is provided directly on the silicon nitride layer 5 b, the holes from the control gate 6 are injected, and therefore an dielectric strength is unable to be kept well. The silicon oxide layer 5 c is provided upward in order to restrain the holes from being injected from the control gate 6.
  • The upper and lower [0011] silicon oxide layers 5 a, 5 c of the ONO layer 5 are each required to have a thickness of 5-6 nm for exhibiting functions of relieving the electric field and preventing the leak. The silicon nitride layer 5 b has a thickness on the order of 10 nm (converted into 5 nm in the case of the oxide layer). Hence, an equivalent oxide thickness of the ONO layer 5 is 15-16 nm thick.
  • There arise the following problems inherent in the inter-layer insulating layer based on the ONO structure described above. [0012]
  • First, it is desirable for enabling the memory cell to operate at a low voltage that a capacitance coupling between the control gate and the floating gate be large. It is desirable for attaining this that the ONO layer be as thin as possible. If the layer thickness is thinned down to a limit thereof, it can be thinned totally down to approximately 14 nm as an equivalent oxide thickness. [0013]
  • However, further thinning of the layer becomes difficult. [0014]
  • Second, in the ONO layer, in a post-oxidating step after gate definition processing, as shown in FIG. 4B., a bird's beak B intrudes in a portion between the floating gate [0015] 4 and the control gate 6 from a side surface. The bird's beak decreases the capacitance coupling between the control gate 6 and the floating gate 4. Especially when the silicon oxide layer 5 a disposed directly on the floating gate is provided by a CVD (Chemical vapor Deposition) method, a characteristic of density thereof is inferior to a thermal oxide layer, and hence oxygen diffuses fast within the layer, with the result that a large bird's beak occurs. In the case of obtaining the silicon oxide layer at a low process temperature, the silicon oxide layer formed by the CVD method might be used more often than by the thermal oxidation, and therefore, in such a case, the intrusion of the bird's beak turns out a problem.
    • SUMMARY OF THE INVENTION
  • It is therefore a primary object of the present invention to provide a non-volatile semiconductor memory device including an inter-layer insulating layer, which is capable of ensuring even a large capacitance coupling between a control gate and a floating gate while securing an electric field relieving effect and a leak preventive function. [0016]
  • According to the present invention, a silicon nitride layer having a trap level density well lower than that of a silicon nitride layer formed by a normal CVD (Chemical Vapor Deposition), especially LPCVD (Low Pressure Chemical Vapor Deposition) method, is provided in the inter-layer insulating layer, whereby a large capacitance coupling between a control gate and a floating gate can be ensured by making an effective thickness of an oxide layer smaller than in the prior art while exhibiting an electric field relieving effect and a lead reducing effect. Furthermore, if such a silicon nitride layer is disposed contiguously to the control gate or the floating gate, an intrusion of a bird's beak can be restrained from occurring in a post-oxidation step, and it is therefore feasible to ensure the large capacitance coupling between the control gate and the floating gate.[0017]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1A and 1B are sectional views each showing a memory cell structure in a first embodiment of the present invention; [0018]
  • FIG. 2 is a sectional view showing a memory cell structure in a second embodiment of the present invention; [0019]
  • FIGS. [0020] 3A-3D are sectional views showing a structure of an inter-layer insulating layer of the memory cell in a third embodiment of the present invention; and
  • FIGS. 4A and 4B are sectional views each showing a memory cell structure of a non-volatile memory in the prior art.[0021]
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Embodiments of the present invention will hereinafter be described with reference to the accompanying drawings. [0022]
  • First Embodiment [0023]
  • FIGS. 1A and 1B are sectional views taken indirection orthogonal to each other, showing a memory cell structure of a non-volatile semiconductor memory device in a first embodiment of the present invention. An element [0024] isolation insulating layer 12 is provided on a p-type silicon substrate 11, and a floating gate 14 composed of a polycrystalline silicon layer is provided through a tunnel insulating layer 13 on a device area defined by the element isolation insulating layer 12. The tunnel insulating layer 13 is classified as a silicon oxide layer. A control gate 16 composed of a polycrystalline silicon layer is stacked on the floating gate 14 via an inter-layer insulating layer 15. Source/drain diffused layers 17, 18 are so provided on the substrate as to be self-aligned with the control gate 16.
  • The [0025] inter-layer insulating layer 15 includes a silicon oxide layer 15 a contiguous to the floating gate 14, and double-layered silicon nitride layers 15 b, 15 c provided thereon. The first silicon nitride layer 15 b is provided by a normal CVD method, especially low pressure (LP) CVD method, and the second silicon nitride layer 15 c is provided by a JVD (Jet Vapor Deposition) method. The second silicon nitride layer 15 c is well lower in trap level density than the first silicon nitride layer 15 b and has a less leak current at a low electric field region.
  • Specifically, the [0026] silicon oxide layer 15 a is a thermal oxide layer obtained by thermally oxidating the floating gate 14, or a silicon oxide layer based on the LPCVD method. The first silicon nitride layer 15 b is formed by the LPCVD method, wherein dichlorosilane (SiH2Cl2) and ammonia (NH4) are used as raw gases. The second silicon nitride layer 15 c is formed such that active Si and N are generated by plasma-decomposing a silane-series gas (e.g., SiH4) supplied together with a carrier gas such as He etc. and a gas (e.g., N2) containing nitrogen by microwave electric power, and supplied and deposited by the JVD method on the surface of the substrate disposed within a chamber. It has already been reported that the silicon nitride layer exhibiting a low trap level density is obtained by the JVD method (refer to, e.g., Applied Surfaces Science 177/118 (1997) 259-267). Herein, a quantity of hydrogen content of the first silicon nitride layer 15 b deposited by the LPCVD method is 1021/cm3 or more, while a quantity of hydrogen content of the second silicon nitride layer 15 c deposited by the JVD method is 1019/cm3 or less. This difference in quantity of hydrogen content therebetween correlates to magnitudes of the trap level densities of those two layers, and, in other words, the silicon nitride layer having a less quantity of hydrogen content, which is deposited by the JVD method, exhibits a low trap level density and has a smaller leak current at the low electric field region.
  • Note that the silicon nitride layers deposited by other deposition methods may also be used on condition that those layers have a quantity of hydrogen content which is as small as the silicon nitride layer deposited by the JVD method, and exhibit a low trap level density. [0027]
  • Next, the reason why a structure of the inter-layer insulating [0028] layer 15 described above will be specifically elucidated as well as explaining a preferable thickness of each layer.
  • In the [0029] single layer 15 c of the silicon nitride layer deposited by the JVD method, Frenkel-Poole type current, though not so much as the silicon nitride layer deposited by the LPCVD method, flows across the low electric field region, and hence this layer 15 is hard to be used solely as an inter-layer insulating layer. Further, the silicon nitride layer has a lower barrier height with respect to silicon than the silicon oxide layer, and is therefore insufficient as a barrier against a release of the electrons from the floating gate. Accordingly, it is required for forming the inter-layer insulating layer that the silicon oxide layer 15 a be disposed just on, e.g., the floating gate 14. The silicon oxide layer 15 a requires a thickness on the order of 5-6 nm for keeping a sufficient dielectric strength.
  • This first [0030] silicon nitride layer 15 b provided based on the LPCVD method is needed for preventing the lead as well as for obtaining the electric field relieving effect. That is, the first silicon nitride layer 15 b exhibits a high trap density and a Frenkel-Poole type electric conductive characteristic. In this Frenkel-Poole type electric conduction, the current in a high electric field region is small, and the current becomes hard to flow through a layer containing a trap because of the carriers being trapped even when the current flows therethrough at an initial stage. Therefore, the first silicon nitride layer 15 b restrains an increase in the leak current due to the electric field enhancement at the edge taking a two-dimensional configuration of the floating gate 14. It is preferable for exhibiting the sufficient electric field relieving effect that the thickness of the silicon nitride layer 15 b be over 6 nm. It is also preferable for ensuring a large capacitance coupling that the above thickness be under 10 nm, to be specific, on the order of 8 nm.
  • The second [0031] silicon nitride layer 15 c based on the JVD method functions to restrain the hole implantation from the control gate 16. Namely, the first silicon nitride layer 15 b based on the LPCVD method is easy to flow the Frenkel-Poole type Hall current. If the silicon nitride layer 15 b is contiguous directly to the control gate 6, as described above, the large leak current flows due to the hole implantation from the control gate 16 in such an operation mode that the control gate 16 comes to have a positive bias. The second silicon nitride layer 15 c based on the JVD method has an extremely low trap density and effectively restrains the hole implantation from the control gate 16. It is preferable for exhibiting this function that the second silicon nitride layer 15 c be over 6 nm thick. It is also preferable for ensuring a large capacitance coupling that the thickness thereof be under 10 nm. Specifically, for example, the thickness of the silicon oxide layer 15 a is set to 6 nm, and the thicknesses pf the silicon nitride layers 15 a, 15 b are each set to 6 nm (3 nm in the conversion of the oxide layer), and the effective thickness of the oxide layer is 12 nm. Accordingly, the layer can be made thinner than in a case of using the conventional ONO structure, and besides the sufficient electric field relieving effect can be obtained. Further, the silicon nitride layer 15 c is the uppermost layer of the inter-layer insulating layer 15, and therefore it is feasible to restrain the intrusion of the bird's beak when effecting the post-oxidation.
  • Second Embodiment [0032]
  • FIG. 2 shows, corresponding to FIG. 1B, a memory cell structure in a second embodiment of the present invention. [0033]
  • In the second embodiment of the present invention, the inter-layer insulating [0034] layer 15 is double-layered including two layers, i.e., from the side of the floating gate 14, the silicon oxide layer 15 a and the silicon nitride layer 15 c based on the JVD method which has a low trap density and a hydrogen content quantity on the order of 1019/cm3 or less.
  • In the first embodiment, the [0035] silicon nitride layer 15 b based on the LPCVD method and exhibiting the Frenkel-Poole type conduction, is disposed in the middle of the interlayer-insulating layer 15. If not operated with a high electric field, however, the silicon nitride layer 15 b is not necessarily used. Namely, as shown in FIG. 2, for the purpose of blocking a defect in the lowermost silicon oxide layer 15 a, the insulating layer may take a double-layered structure consisting of the silicon oxide layer 15 a ad the silicon nitride layer 15 c based on the JVD method and exhibiting the low trap density.
  • In the case of the silicon nitride layer formed by the normal LPCVD method and containing much of trap, the effect produced by use of the silicon nitride layer can not be expected due to a large quantity of holes injected from the control gate only with the double-layered structure of the silicon oxide layer and the silicon nitride layer. When using the silicon nitride layer based on, e.g., the JVD method, there is almost no hole conduction, and hence the above effect can be sufficiently obtained even with the double-layered structure. [0036]
  • Third embodiment [0037]
  • For preventing the bird's beak from intruding into the inter-layer insulting layer due to the post-oxidation, the silicon nitride layer formed by the JVD method and having a hydrogen content quantity on the order of 10[0038] 19/cm3 or less, is provided keeping its thickness as thin as approximately 3 nm directly on the floating gate (i.e., the lowermost layer of the inter-layer insulating layer) or just under the control gate (viz., the uppermost layer of the inter-layer insulating layer). If a layer based on the normal LPCVD method and exhibiting a high trap density is used as this silicon nitride layer, a threshold value of the memory cell might become unstable due to the trap and release of the electric charges within the layer. If the silicon nitride layer deposed by the JVD method and having a low trap density is used, however, the instability of the threshold value never occurs.
  • FIGS. [0039] 3A-3D show an extraction of only the structure of the inter-layer insulating layer in the third embodiment.
  • FIG. 3A shows an example in which a [0040] silicon nitride layer 15 d based on the JVD method is added as a layer contiguous to the floating gate 14 to a structure of the inter-layer insulating layer 15 in FIG. 15. A similar silicon nitride layer 15 c serving as a layer contiguous to the control gate 16 is also provided, and the silicon oxide layer 15 a is interposed between the nitride layers 15 c and 15 d, thereby structuring the inter-layer insulating layer 15.
  • FIG. 3B shows an example in which the [0041] silicon nitride layer 15 d formed by the JVD method is likewise added as a layer contiguous to the floating gate 14 to the structure of the inter-layer insulating layer 15 in FIG. 1. In this case also, the similar silicon nitride layer 15 c serving as a layer contiguous to the control gate 16 is also provided, and a stacked layer of the silicon oxide layer 15 a and the silicon nitride layer 15 b formed by the LPCVD method, is interposed between the nitride layers 15 c and 15 d.
  • FIG. 3C shows an example in which the [0042] silicon nitride layer 15 d formed by the JVD method is likewise added as a layer contiguous to the floating gate 14 to a normal-ONO-structured inter-layer insulating layer 150. More specifically, the stacked layer 150 consisting of the silicon oxide layer, the silicon nitride layer based on the LPCVD method and the silicon oxide layer, is superposed further on the silicon nitride layer 15 d.
  • FIG. 3D shows an example in which silicon nitride, layers [0043] 15 d, 15 e formed by the JVD method are stacked as layers contiguous to the floating gate 14 and the control gate 16, on the normal NON-structured inter-layer insulating layer 150. That is, the silicon nitride layer 15 e is superposed further on the NON structured inter-layer insulating layer 150.
  • The third embodiment also exhibits the same effects. [0044]
  • According to the present invention, the silicon nitride layer having the trap level that is well lower than that of the silicon nitride layer based on the normal LPCVD method, is provided in the inter-layer insulating layer of the non-volatile memory cell having the stacked gate structure, whereby the large capacitance coupling between the control gate and the floating gate can be ensured by making the effective thickness of the oxide layer smaller than in the priori art while exhibiting the electric field relieving effect and the effect of reducing the leak. [0045]

Claims (18)

What is claimed is:
1. A non-volatile semiconductor memory device comprising:
a semiconductor substrate; and
a memory cell having a floating gate provided through a tunnel insulating layer on said semiconductor substrate, and a control gate provided through an inter-layer insulting layer on said floating gate,
wherein said inter-insulating layer includes:
a silicon oxide layer contiguous to said floating gate;
a first silicon nitride layer provided by a CVD method on said silicon oxide layer; and
a second silicon nitride layer provided on said first silicon nitride layer and having a lower trap density than that of said first silicon nitride layer.
2. A non-volatile semiconductor memory device according to claim 1, wherein said second silicon nitride layer is formed by carrying, over a surface of said substrate, active Si and N obtained by plasma-decomposing at least a silane-series gas and a gas containing nitrogen.
3. A non-volatile semiconductor memory device according to claim 1, wherein a quantity of hydrogen content of said first silicon nitride layer is 1021/cm3 or more.
4. A non-volatile semiconductor memory device according to claim 1, wherein a quantity of hydrogen content of said second silicon nitride layer is 1019/cm3 or less.
5. A non-volatile semiconductor memory device comprising:
a semiconductor substrate; and
a memory cell having a floating gate provided through a tunnel insulating layer on said semiconductor substrate, and a control gate provided through an inter-layer insulting layer on said floating gate,
wherein said inter-insulating layer includes:
a silicon oxide layer contiguous to said floating gate; and
a silicon nitride layer deposited on said silicon oxide layer and having a lower trap density than that of said silicon nitride layer formed by a CVD method.
6. A non-volatile semiconductor memory device according to claim 5, wherein said silicon oxide layer is deposited by carrying, over-a surface of said substrate, active Si and N obtained by plasma-decomposing at least a silane-series gas and a gas containing nitrogen.
7. A non-volatile semiconductor memory device comprising:
a semiconductor substrate; and
a memory cell having a floating gate provided through a tunnel insulating layer on said semiconductor substrate, and a control gate provided through an inter-layer insulting layer on said floating gate,
wherein said inter-insulating layer includes:
a silicon oxide layer contiguous to said floating gate; and
a silicon oxide layer deposited on said silicon oxide layer and having a quantity of hydrogen content on the order of 1019/cm3 or less.
8. A non-volatile semiconductor memory device according to claim 7, wherein said silicon oxide layer is deposited by carrying, over a surface of said substrate, active Si and N obtained by plasma-decomposing at least a silane-series gas and a gas containing nitrogen.
9. A non-volatile semiconductor memory device comprising:
a semiconductor substrate; and
a memory cell having a floating gate provided through a tunnel insulating layer on said semiconductor substrate, and a control gate provided through an inter-layer insulting layer on said floating gate,
wherein said inter-insulating layer includes:
a silicon oxide layer serving as a layer contiguous to at least one of said floating gate and said control gate, and having a lower trap density than that of a silicon nitride layer formed by a CVD method.
10. A non-volatile semiconductor memory device according to claim 9, wherein said silicon nitride layer is formed by carrying, over a surface of said substrate, active Si and N obtained by plasma-decomposing at least a silane-series gas and a gas containing nitrogen.
11. A non-volatile semiconductor memory device according to claim 9, wherein said silicon nitride layers are so double-layered as to be contiguous to both of said floating gate and said control gate, and
a silicon oxide layer is interposed in between said double-layered silicon nitride layers.
12. A non-volatile semiconductor memory device according to claim 9, wherein said silicon nitride layers are so double-layered as to be contiguous to both of said floating gate and said control gate, and
a stacked layer consisting of a silicon oxide layer and a silicon nitride layer formed by a CVD method is interposed in between said double-layered silicon nitride layers.
13. A non-volatile semiconductor memory device according to claim 9, wherein said silicon nitride layer is provided only on the side contiguous to said floating gate, and
a silicon oxide layer and a stacked layer consisting of a silicon nitride layer and a silicon oxide layer which are formed by the CVD method, are provided on said silicon nitride layer.
14. A non-volatile semiconductor memory device comprising:
a semiconductor substrate; and
a memory cell having a floating gate provided through a tunnel insulating layer on said semiconductor substrate, and a control gate provided through an inter-layer insulting layer on said floating gate,
wherein said inter-insulating layer includes:
a silicon oxide layer serving as a layer contiguous to at least one of said floating gate and said control gate, and having a quantity of hydrogen content on the order of 1019/cm3 or less.
15. A non-volatile semiconductor memory device according to claim 14, wherein said silicon nitride layer is formed by carrying, over a surface of said substrate, active Si and N obtained by plasma-decomposing at least a silane-series gas and a gas containing nitrogen.
16. A non-volatile semiconductor memory device according to claim 14, wherein said silicon nitride layers are so double-layered as to be contiguous to both of said floating gate and said control gate, and
a silicon oxide layer is interposed in between said double-layered silicon nitride layers.
17. A non-volatile semiconductor memory device according to claim 14, wherein said silicon nitride layers are so double-layered as to be contiguous to both of said floating gate and said control gate, and
a stacked layer consisting of a silicon oxide layer and a silicon nitride layer formed by a CVD method is interposed in between said double-layered silicon nitride layers.
18. A non-volatile semiconductor memory device according to claim 14, wherein said silicon nitride layer is provided only on the side contiguous to said floating gate, and
a silicon oxide layer and a stacked layer consisting of a silicon nitride layer and a silicon oxide layer which are formed by the CVD method, are provided on said silicon nitride layer.
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US11/458,330 US20060244046A1 (en) 1998-12-09 2006-07-18 Non-Volatile Semiconductor Memory Device
US11/458,324 US20060249781A1 (en) 1998-12-09 2006-07-18 Non-Volatile Semiconductor Memory Device
US11/458,317 US20060249780A1 (en) 1998-12-09 2006-07-18 Non-Volatile Semiconductor Memory Device
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