KR930009482B1 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

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Description

Semiconductor device and manufacturing method

1 is a cross-sectional view showing the vicinity of a tunnel insulating film when the present invention is applied to an E ² PROM.

2 shows an impurity profile in a depth direction of a tunnel insulating film in the E ² PROM of FIG.

3A to 3D are cross-sectional views showing a case where the manufacturing method of the present invention is applied to a memory transistor of an E ² PROM.

4A to 4D are cross-sectional views showing a case where the manufacturing method of the present invention is applied to a logic transistor.

5 is a cross-sectional view showing a case where the present invention is applied to a semiconductor device having a twin well structure.

6 is a sectional view showing an E ² PROM of a conventional two-layer polysilicon structure.

7 shows the tradeoff curves of cumulative failure rate of tunnel insulation film and breakdown voltage of poly-poly insulation film with respect to diffusion time to floating gate.

8 shows an impurity profile in a depth direction of an oxide film in a conventional E ² PROM.

* Explanation of symbols for main parts of the drawings

1, 11: p-type silicon substrate 2: n-type diffusion region

3, 4, 14: silicon oxide film 5, 15: silicon oxynitride film

6, 8, 16: polysilicon film 7: poly-poly insulation film

[Industrial use]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device of a polysilicon gate having a very thin (? 100kV) gate oxide film or a tunnel oxide film. In particular, the present invention has a two-layer polysilicon layer structure (FLOTOX type), which enables data to be recorded electrically changed. A volatile memory device and a method of manufacturing the same.

[Traditional Technology and Problems]

A conventional memory device, such as an E ² PROM, having a two-layer polysilicon structure capable of electrically altering and recording data, has a cross-sectional structure as shown in FIG. 6, where reference numeral 21 is a p-type. The silicon substrate, 22 is an n-type impurity region, 23 is a gate oxide film, 24 is a tunnel oxide film, 25 is a selection gate, 26 is a floating gate, 27 is a poly-poly insulation film, and 28 is a control gate.

In the E ² PROM, a conductive polysilicon film doped with an impurity is usually used as the floating gate 26, and a method of doping n-type impurities with the polysilicon film is thermal diffusion using POCl ₃ gas (hereinafter, “ Diffusion ”is common. It is also known that the reliability of the tunnel oxide film 24 and the breakdown voltage of the poly-poly insulation film 27 are in a trade-off relationship with respect to the phosphorus diffusion time.

Specifically, as shown in FIG. 7, when the diffusion time to the floating gate 26 is short, many protrusions are generated on the floating gate 26, so that the poly-poly insulating film 27 (floating gate 26) is formed. ) And the interlayer insulating film between the control gate 28 decreases (curve a). On the other hand, in the case where the phosphorus diffusion time to the floating gate 26 is long, the phosphorus from the floating gate 26 diffuses into the tunnel oxide film 24, so that its reliability is low. That is, the cumulative defective rate (or Weibull distribution) of the tunnel oxide film 24 becomes high (curve b). Therefore, conventionally, a diffusion time for satisfying both the reliability of the tunnel oxide film 24 and the breakdown voltage of the poly-poly insulation film 27, for example, t ₁ is selected in FIG.

However, the optimization of the phosphorus diffusion time can satisfy the internal pressure of the poly-poly insulation film 27 and the reliability of the tunnel oxide film 24 when the thickness of the tunnel oxide film 24 is about 100 kPa. In this regard, in the future, thinning of the tunnel oxide film 24 due to high integration will be essential, and it is easily expected that optimization of phosphorus diffusion time alone will not be able to meet such a demand.

In addition, conventionally, a thermal nitriding method for nitriding the tunnel oxide film 24 has been considered for the damage caused by the thinning of the tunnel oxide film 24. However, this thermal nitriding method uses a diffusion furnace to carry out long annealing in an NH ₃ atmosphere to incorporate nitrogen atoms N into the tunnel oxide film 24. For this reason, it is known that nitrogen atoms mixed into the tunnel oxide film 24 pile up (that is, accumulate in the boundary region with the semiconductor substrate). That is, as shown in the impurity profile of FIG. 8, nitrogen atoms in the tunnel oxide film 24 are detected in the interface region of each of the floating gate 26 and the semiconductor substrate 21. As shown in FIG. Therefore, Si-N groups are formed in the boundary region with the semiconductor substrate 21 to increase the static charge or increase the Nss. As a result, there are drawbacks such as a decrease in channel mobility and poor breakdown voltage of the tunnel oxide film.

As described above, the conventional semiconductor device has a drawback that the internal pressure of the poly-poly insulating film and the reliability of the tunnel oxide film cannot be satisfied at the same time by thinning the tunnel oxide film due to the high integration.

[Purpose of invention]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described aspects, and a polysilicon gate semiconductor device and a method for manufacturing the same, which can maintain the reliability of the gate oxide film or the tunnel oxide film in the future without depending on the diffusion time, are disclosed. The purpose is to provide.

[Configuration of Invention]

The present invention for achieving the above object is, for example, in a polysilicon gate transistor having a gate insulating film of 100 kΩ or less, for example, a silicon oxide film formed on a semiconductor substrate, and an interface between the silicon oxide film and the polysilicon gate. While forming in the region, the composition is provided with a silicon nitride film whose composition is represented by SixNyOz.

Further, for example, in a nonvolatile memory device having a tunnel insulating film of 100 占 퐉 or less and capable of changing data electrically, the tunnel insulating film is formed on a semiconductor substrate, for example, a silicon oxide film, and a silicon oxide film and a floating gate electrode. It is formed on the interface region and has a silicon nitride oxide film whose composition is represented by SixNyOz.

The silicon nitride oxide film may be formed not only at the interface area between the silicon oxide film and the semiconductor substrate but at least at the interface area between the silicon oxide film and the polysilicon gate.

In addition, the method of manufacturing the silicon nitride oxide film is a gate insulating film or a tunnel insulating film, for example, after forming a silicon nitride film, RTA (Rapid Thermal Anneal) in a gas atmosphere containing nitrogen atoms such as N ₂ , NH ₃ , N ₂ H _4, etc. It is supposed to do.

[Action]

According to the present invention configured as described above, the dense silicon nitride film is present at least directly under the polysilicon gate. In other words, even when the gate insulating film or the tunnel insulating film is expected to be thinned in the future, the polysilicon gate can be doped with impurities by the current diffusion processor. Furthermore, since the silicon oxynitride film is not formed at the interface region between the silicon oxide film and the semiconductor substrate, the reliability of the gate insulating film or the tunnel insulating film can be maintained. In addition, by optimizing the diffusion time, the reliability of the tunnel insulation film and the breakdown voltage of the poly-poly insulation film can be simultaneously satisfied.

According to the above method, the silicon nitride oxide film is formed by RTA in a gas atmosphere containing nitrogen atoms such as N ₂ , NH ₃ , N ₂ H _4, and the like, since the RTA does not require long-term annealing. Nitrogen atom pile up can be prevented. As a result, it is possible to prevent a decrease in channel mobility and a poor penetration of the gate insulating film or the tunnel oxide film.

EXAMPLE

Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a cross sectional view showing the vicinity of a tunnel insulating film as an embodiment in which the semiconductor device of the present invention is applied to an E ² PROM.

In this embodiment, an n-type diffusion region 2 is formed in the surface region of the p-type silicon substrate 1, and a silicon oxide film 3 is formed on the substrate 1 as a gate insulating film. 3) Tunnel window is opened. As a result, a silicon oxide film 4 is formed on the exposed n-type diffusion region 2. On the silicon oxide films 3 and 4, a silicon nitride oxide film 5 having an undetermined stoichiometric ratio is formed while its composition is represented by SixOyNz, and a floating gate is formed on the silicon nitride oxide film 5. A polysilicon film 6 is formed. A tunnel insulating film is formed by the silicon oxide film 4 and the silicon nitride oxide film 5, and the film thickness thereof is thinned to about 100 GPa or less. Here, the silicon nitride oxide film 5 is not formed in the interface region between the silicon oxide films 3 and 4 and the substrate 1 but at least in the interface region between the silicon oxide films 3 and 4 and the polysilicon film 6. In this case, it refers to a film capable of mixing and accumulating nitrogen atoms in the silicon oxide films 3 and 4.

FIG. 2 shows profiles of silicon atoms (Si), oxygen atoms (O) and nitrogen atoms (N) in the depth direction of the tunnel insulating film (I-I 'direction in FIG. 1) in the E ² PROM. It is.

Nitrogen atoms mixed in the tunnel insulating film are not accumulated in the interface region with the semiconductor substrate but in the interface region with the floating gate. That is, the conventional pile-up is the same in that the tunnel insulation film, for example, the silicon oxide film is nitrided, but is structurally completely different from the atomic level. In addition, this nitrogen atom converts a pure silicon oxide film into a silicon nitride oxide film. Specifically, the film is changed to a finer film than a pure silicon oxide film. Therefore, the infiltration of phosphorus from the floating gate can be prevented by the nitride oxide film.

Next, a manufacturing method for realizing the above E ² PROM will be described with reference to FIGS. 3A to 3D by taking a memory transistor as an example. In the same drawings, the same reference numerals are used to denote the same parts as in the first drawing.

First, as shown in FIG. 3A, an isolation region (not shown) is formed in the p-type silicon substrate 1, and then the ions for threshold control of the memory transistor are implanted. After the ion implantation is performed to form the n-type diffusion region 2, a silicon oxide film 3 as a gate insulating film is formed on the substrate 1.

Subsequently, as shown in FIG. 3B, NH ₄ F etching is performed using a conventional photolithography technique to form a hole reaching the n-type diffusion region 2 at a predetermined position of the siliconyl oxide film 3. Thereafter, a very thin silicon oxide film 4 is formed on the n-type diffusion region 2 exposed by the hole.

Subsequently, as shown in FIG. 3C, RTA (Rapid Thermal Anneal) for about 1 minute is performed at 1000 ° C. to 1200 ° C. in an NH ₃ atmosphere to mix nitrogen atoms into the surface region of the silicon oxide film 4. A silicon nitride oxide film 5 having a composition of SixOyNz and an indeterminate stoichiometric ratio is formed on the silicon oxide film 4. Since this RTA does not require long annealing, it is possible to improve the controllability of the film thickness of the nitride oxide film 5 at each stage as compared with the SiN film by the CVD method or the like. Further, pile-up of nitrogen atoms at the interface between the substrate 1 and the silicon oxide film 4 can be prevented (that is, an impurity profile as shown in FIG. 2 can be realized).

Subsequently, a first polysilicon film 6 serving as a floating gate is deposited on the silicon nitride oxide film 5, and the first polysilicon film 6 is made conductive by phosphorus diffusion. At this time, the infiltration of phosphorus from the first polysilicon film 6 into the silicon oxide film 4 can be prevented by the silicon nitride oxide film 5.

Subsequently, as shown in FIG. 3D, a cell slit (not shown) is drilled through the first polysilicon film 6, followed by thermal oxidation to form a poly-poly insulation film 7. Further, a second polysilicon film 8 is deposited on this poly-poly insulating film 7 and made into conductive by phosphorus diffusion. Next, the memory transistors are patterned using conventional photolithography techniques.

By using such a nitriding method by the RTA technique, the long-term annealing is not necessary, so that pile-up of nitrogen atoms at the interface between the substrate 1 and the silicon oxide film 4 can be prevented.

However, since the barrier height of the silicon oxide film 5 is lower than that of the pure thermal oxide film, the withdrawal of electrons from the floating gate becomes substantially easy. In addition, the charge holding characteristic (Retention) does not deteriorate because a bulk oxide film (referred to as silicon oxide films 3 and 4 not nitrided by RAT) exists. In addition, the current transport mechanism of the tunnel insulation film can be described as a Fowler-Nordheim-type tunnel like a pure silicon oxide film.

On the other hand, the poly-poly insulating film 7 of the above embodiment may have a three-layer structure of an oxide film / nitride film / oxide film.

Next, in the case where the present invention is applied to a logic transistor having a CMOS structure, a manufacturing method for realizing the same will be described with reference to FIGS. 4A to d.

First, as shown in FIG. 4A, the n well region 12 is formed in the p-type silicon substrate 11. In addition, the element active region and the field region 13 are formed using conventional element isolation techniques. Subsequently, as shown in FIG. 4B, after the implantation control ions of the transistor are implanted, the silicon oxide film 14 is formed on the substrate 1 by thermal oxidation as a gate insulating film.

Next, as shown in FIG. 4C, nitrogen atoms are mixed in the surface region of the silicon oxide film 14 by RTA in an NH ₃ atmosphere. A silicon nitride oxide film 15 having a composition represented by SixOyNz is formed on the silicon oxide film 14. Further, a first polysilicon film 16 serving as a gate electrode is deposited on the silicon nitride oxide film 15. In addition, phosphorus is diffused into the first polysilicon film 16 to make conductivity. At this time, phosphorus penetration into the silicon oxide film 14 from the first polysilicon film 16 is prevented by the silicon nitride oxide film 15.

Next, as shown in FIG. 4D, the logic transistor is patterned.

In the logic transistor according to the above-described manufacturing method, a dense silicon nitride oxide film 15 is formed at least directly under the gate electrode 16. Therefore, when doping impurities into the gate electrode 16, a conventional phosphorus diffusion process can be used without lowering the reliability of the gate oxide film 14.

The present invention can also be applied to a semiconductor device having a twin well structure in which transistors having different polarities are surrounded by respective wells as shown in FIG. In FIG. 5, the same reference numerals are used for the same parts as those in FIG. In the figure, reference numeral 17 denotes a p well, 18 denotes a low concentration n-type impurity region, 19 denotes a high concentration p-type impurity region, and 20 denotes a highly concentrated n-type impurity region.

In the above embodiment, the reaction gas for performing RTA is not limited to NH ₃ and may be a gas containing nitrogen atoms such as N ₂ , N ₂ H _4, and the like. Further, the conductive properties of the substrates 1, 11, the wells 12, 17, the diffusion regions 2, 18, 19, 20, and the like may be reverse conductive type as in the above embodiment. If necessary, the amount of nitrogen atoms deposited between the semiconductor substrate and the insulating film can be reduced by performing a dry oxidation treatment of, for example, 100 ° C. or more for about 10 minutes after the RTA treatment of converting a part of the oxide film into a silicon nitride oxide film.

On the other hand, reference numerals denoted in the components of the claims of the present application to facilitate the understanding of the present invention, not intended to limit the technical scope of the present invention to the embodiments shown in the drawings.

[Effects of the Invention]

According to the semiconductor device and the manufacturing method thereof according to the present invention as described above, a dense silicon nitride oxide film can be formed at least directly under the polysilicon gate by nitriding the thin filmed gate insulating film or tunnel insulating film by RTA technology. That is, a conventional phosphorus diffusion process may be used when doping impurities with the polysilicon gate. Further, since the silicon nitride oxide film is not formed in the interface region between the gate insulating film or the tunnel insulating film and the semiconductor substrate, the reliability of the gate insulating film or the tunnel insulating film is not degraded. In addition, by optimizing the diffusion time, the reliability of the tunnel insulation film and the breakdown voltage of the poly-poly insulation film can be satisfied at the same time.

Furthermore, the silicon nitride oxide film is formed by RTA in a gas atmosphere containing nitrogen atoms such as N ₂ , NH ₃ , N ₂ H _4, and the like, since the RTA does not require long annealing, so that the substrate and the gate insulating film or tunnel Nitrogen atoms at the interface between the insulating films can be prevented from being piled up. Therefore, it is possible to prevent a decrease in channel mobility and a breakdown voltage failure of the gate insulating film or the tunnel insulating film, and contribute to a significant improvement in the manufacturing technology.

Claims (6)

A semiconductor device having a semiconductor substrate 1, oxide films 3 and 4 formed on the semiconductor substrate 1, and a polysilicon layer 6 formed on the oxide films 3 and 4 containing impurities. The semiconductor device according to claim 1, wherein a silicon nitride oxide film (5) is formed between the oxide films (3, 4) and the polysilicon layer (6). The semiconductor device according to claim 1, wherein the oxide film is composed of a thick film portion (3) and a thin film portion (4), and the polysilicon layer 6 is in an electrically floating state. . The semiconductor device according to claim 1, wherein the impurity of the polysilicon layer (6) is phosphorus (P). A semiconductor device having a semiconductor substrate 1, oxide films 3 and 4 formed on the semiconductor substrate 1, and a polysilicon layer 6 formed on the oxide films 3 and 4 containing impurities. In the method for producing the oxide films 3 and 4, heat treatment is performed in a gas atmosphere containing nitrogen atoms, and silicon nitride oxide films 5 are formed on a part of the surface of the oxide films 3 and 4. A method of manufacturing a semiconductor device, characterized in that. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the step of forming the oxide films (3, 4) comprises a step of forming a thick film portion (3) and a thin film portion (4). . The method of manufacturing a semiconductor device according to claim 4, wherein the step of forming the polysilicon layer (6) containing the impurity includes a step of diffusing phosphorus.

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