US20030201925A1 - A/d converter with noise elimination function - Google Patents
A/d converter with noise elimination function Download PDFInfo
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- US20030201925A1 US20030201925A1 US10/326,055 US32605502A US2003201925A1 US 20030201925 A1 US20030201925 A1 US 20030201925A1 US 32605502 A US32605502 A US 32605502A US 2003201925 A1 US2003201925 A1 US 2003201925A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0845—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of power supply variations, e.g. ripple
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
Definitions
- the present invention relates to an A/D converter with noise elimination function in a semiconductor device.
- FIG. 10 is a block diagram showing a configuration of a conventional A/D converter.
- the reference numeral 1 designates an A/D conversion reference voltage Vref
- 2 designates a noise filtering module for removing noise from the A/D conversion reference voltage Vref 1
- 3 designates an A/D conversion module for converting an analog input Ain to a digital output with reference to the A/D conversion reference voltage Vref 1
- 4 designates an A/D controller for controlling the A/D conversion module 3 .
- FIGS. 11A and 11B are tables illustrating a setting method of the A/D conversion reference voltage Vref of the A/D converter.
- the noise filtering module 2 removes the noise of the A/D conversion reference voltage Vref 1 , and supplies its output to the A/D conversion module 3 .
- FIG. 11A gives expressions of the relationships between the A/D conversion reference voltage Vref 1 and the reference voltage VREF in the A/D conversion module 3 ; and FIG. 11B illustrates the variations in the content of the A/D conversion register in the A/D conversion module 3 during the A/D conversion.
- the A/D conversion register is placed at “0 . . . 0”. Subsequently, the most significant bit of the A/D conversion register is placed at “1”, and the A/D conversion reference voltage Vref 1 is supplied to the comparator in the A/D conversion module 3 , which compares the A/D conversion reference voltage Vref 1 with the analog input Ain. If the compared result is Vref ⁇ Ain, the most significant bit of the A/D conversion register is maintained at “1”, whereas if Vref>Ain, the most significant bit of the A/D conversion register is placed at “0”.
- the A/D conversion module 3 Carrying out the foregoing operation down to the least significant bit of the A/D conversion register, the A/D conversion module 3 stores into the A/D conversion register the digital value obtained by converting the analog input Ain.
- the conventional A/D converter cannot obtain accurate A/D conversion data when the A/D conversion reference voltage Vref 1 includes noise.
- it includes the noise filtering module 2 for removing noise from the A/D conversion reference voltage Vref 1 so as to supply the noise reduced A/D conversion reference voltage Vref 1 to the A/D conversion module 3 .
- the conventional A/D converter has a problem of being unable to obtain the accurate A/D conversion data if the A/D conversion reference voltage Vref 1 includes noise that cannot be removed by the noise filtering module 2 .
- it has a problem of increasing the circuit scale because of the noise filtering module 2 .
- the present invention is implemented to solve the foregoing problems. It is therefore an object of the present invention to provide an A/D converter capable of obtaining reliable A/D conversion data without increasing the circuit scale so much even if the A/D conversion reference voltage includes noise.
- an A/D converter including: an A/D operation controller for generating a bit-shift signal in response to a detection signal fed from a detector; and an A/D conversion module for carrying out A/D conversion with reference to an A/D conversion reference voltage, for discarding an A/D conversion resultant bit affected by noise in response to the bit-shift signal, for holding remaining A/D conversion resultant bits, and for restarting the A/D conversion from the discarded A/D conversion resultant bit after the noise becomes negligible. It offers an advantage of being able to improve the reliability of the A/D conversion data by discarding the A/D conversion resultant bit affected by sudden noise or crosstalk noise during the USB communication.
- an A/D converter including: an A/D conversion module for generating A/D conversion resultant data by carrying out A/D conversion of an analog input signal with reference to an A/D conversion reference voltage; and an A/D operation controller for deciding an A/D conversion resultant bit affected by noise in response to the detection signal and to the A/D conversion resultant data, and for outputting reliability information together with the A/D conversion resultant data. It can learn the reliability of the A/D conversion resultant data affected by the sudden noise or crosstalk noise during the USB communication. As a result, it offers an advantage of being able to improve the reliability of the A/D conversion data by discarding the A/D conversion resultant data with the reliability less than a certain level.
- FIG. 1 is a block diagram showing a configuration of an embodiment 1 of the A/D converter in accordance with the present invention
- FIG. 2 is a block diagram showing a configuration of an embodiment 2 of the A/D converter in accordance with the present invention
- FIG. 3 is a block diagram showing a configuration of an embodiment 3 of the A/D converter in accordance with the present invention.
- FIG. 4 is a block diagram showing a configuration of an embodiment 4 of the A/D converter in accordance with the present invention.
- FIG. 5 is a block diagram showing a configuration of a semiconductor device with a USB function associated with an embodiment 5 in accordance with the present invention:
- FIG. 6 is a block diagram showing a configuration of the embodiment 5 of the A/D converter in accordance with the present invention.
- FIG. 7 is a block diagram showing a configuration of an embodiment 6 of the A/D converter in accordance with the present invention.
- FIG. 8 is a block diagram showing a configuration of an embodiment 7 of the A/D converter in accordance with the present invention.
- FIG. 9 is a block diagram showing a configuration of an embodiment 8 of the A/D converter in accordance with the present invention.
- FIG. 10 is a block diagram showing a configuration of a conventional A/D converter.
- FIGS. 11A and 11B are tables illustrating a setting method of the A/D conversion reference voltage of the conventional A/D converter.
- FIG. 1 is a block diagram showing a configuration of an embodiment 1 of the A/D converter in accordance with the present invention.
- the reference numeral 1 designates an A/D conversion reference voltage Vref.
- the reference numeral 11 designates a noise detector for generating a noise detection signal 14 when it detects noise in the A/D conversion reference voltage Vref 1 .
- the noise detector 11 includes a constant voltage source 12 and a comparator 13 .
- the reference numeral 15 designates an A/D operation controller composed of SR flip-flops and the like, for generating a bit-shift signal 16 in response to the noise detection signal 14 fed from the noise detector 11 .
- the reference numeral 17 designates an A/D conversion module for converting an analog input Ain to a digital output with reference to the A/D conversion reference voltage Vref 1 ; and 18 designates an A/D controller that discards an A/D conversion resultant bit affected by noise in response to the bit-shift signal 16 fed from the A/D operation controller 15 , holds the remaining A/D conversion resultant bits, and restarts the A/D conversion from the discarded A/D conversion resultant bit after the noise becomes negligible.
- the noise detector 11 detects the noise, and supplies the noise detection signal 14 to the A/D operation controller 15 .
- the A/D operation controller 15 In response to the noise detection signal 14 , the A/D operation controller 15 generates the bit-shift signal 16 for removing the A/D conversion resultant bit affected by the noise using the SR flip-flops and the like.
- the A/D controller 18 discards the A/D conversion resultant bit affected by the noise in response to the bit-shift signal 16 fed from the A/D operation controller 15 . Then, the A/D conversion module 17 , which holds the remaining A/D conversion resultant bits, restarts the A/D conversion from the discarded A/D conversion resultant bit after the noise becomes negligible.
- the present embodiment 1 can improved the reliability of the A/D conversion data by discarding the A/D conversion resultant bit affected by sudden noise.
- the present embodiment does not require any general-purpose counter, and can perform the A/D conversion with simpler operation without interrupting the A/D conversion.
- the present embodiment 1 can improve the reliability of the A/D conversion data by using simple circuits such as the noise detector 11 and A/D operation controller 15 without increasing the circuit scale.
- FIG. 2 is a block diagram showing a configuration of an embodiment 2 of the A/D converter in accordance with the present invention.
- the reference numeral 21 designates an A/D operation controller composed of SR flip-flops and the like.
- the A/D operation controller 21 generates a start signal 22 in response to the noise detection signal 14 fed from the noise detector 11 , and generates an asserted A/D-stop_bit-shift signal 25 from the generation of the start signal 22 to the reception of an end signal 24 fed from a general-purpose counter 23 .
- the general-purpose counter 23 starts counting a fixed time period in response to the start signal 22 fed from the A/D operation controller 21 , and generates the end signal 24 at the end of the counting.
- the reference numeral 26 designates an A/D controller for discarding an A/D conversion resultant bit affected by the noise in response to the asserted A/D-stop_bit-shift signal 25 fed from the A/D operation controller 21 , and for holding the remaining A/D conversion resultant bits.
- the A/D controller 26 restarts A/D conversion from the A/D conversion resultant bit in response to an unasserted A/D-stop_bit-shift signal 25 fed from the A/D operation controller 21 .
- the remaining configuration is the same as that of FIG. 1.
- the A/D operation controller 21 in FIG. 2 interrupts the A/D conversion in response to the noise detection signal 14 using the SR flip-flops and the like, generates the asserted A/D-stop_bit-shift signal 25 for removing the A/D conversion resultant bit affected by noise, and supplies it to the A/D controller 26 .
- the A/D operation controller 21 also generates the start signal 22 , and supplies it to the general-purpose counter 23 .
- the A/D controller 26 discards the A/D conversion resultant bit affected by noise in response to the asserted A/D-stop_bit-shift signal 25 fed from the A/D operation controller 21 .
- the A/D controller 26 holds the remaining A/D conversion resultant bits.
- the general-purpose counter 23 starts counting the fixed time period in response to the start signal 22 , and supplies the end signal 24 to the A/D operation controller 21 at the end of the counting.
- the fixed time period of the general-purpose counter 23 is determined considering the pulse width of the noise at such a value that the effect of the noise on the A/D conversion can be avoided.
- the A/D operation controller 21 In response to the input of the end signal 24 , the A/D operation controller 21 , ensuring that the noise detector 11 does not generate the noise detection signal 14 , changes the A/D-stop_bit-shift signal 25 from the asserted to unasserted signal and supplies it to the A/D controller 26 .
- the A/D controller 26 restarts the A/D conversion from the discarded A/D conversion resultant bit in response to the unasserted A/D-stop_bit-shift signal 25 .
- the present embodiment 2 can improve the reliability of the A/D conversion data by discarding the A/D conversion resultant bit affected by the sudden noise.
- the present embodiment 2 can prevent the adverse effect of the noise on the A/D conversion data.
- FIG. 3 is a block diagram showing a configuration of an embodiment 3 of the A/D converter in accordance with the present invention.
- the reference numeral 27 designates a CPU that starts counting a fixed time period on software in response to the start signal 22 fed from the A/D operation controller 21 , and generates the end signal 24 at the end of the counting.
- the remaining configuration is the same as that of FIG. 2.
- the present embodiment 3 replaces the general-purpose counter 23 of the foregoing embodiment 2 by the CPU 27 .
- the CPU 27 starts counting the fixed time period on the software in response to the start signal 22 fed from the A/D operation controller 21 , and supplies the end signal 24 to the A/D operation controller 21 at the end of the counting.
- the remaining operation is the same as that of the foregoing embodiment 2.
- the present embodiment 3 can improve the reliability of the A/D conversion data by discarding the A/D conversion resultant bit affected by sudden noise.
- the A/D conversion module 17 halts the A/D conversion only for the fixed time period counted by the CPU 27 from the detection of the noise, it can prevent the adverse effect of the noise on the A/D conversion data.
- FIG. 4 is a block diagram showing a configuration of an embodiment 4 of the A/D converter in accordance with the present invention.
- the reference numeral 3 designates an A/D conversion module for converting the analog input Ain to the digital output in accordance with the A/D conversion reference voltage Vref 1 ; and 4 designates an A/D controller for controlling the A/D conversion module 3 .
- the reference numeral 28 designates A/D conversion resultant data output from the A/D conversion module 3 .
- the reference numeral 29 designates an A/D operation controller that decides an A/D conversion resultant bit affected by noise in response to the noise detection signal 14 fed from the noise detector 11 and to the A/D conversion resultant data 28 fed from the A/D conversion module 3 , and outputs A/D data 30 including the A/D conversion resultant data 28 and its reliability information.
- the reference numeral 31 designates a CPU for making a decision from the A/D data 30 as to whether to adopt the A/D conversion resultant data 28 or not in response to the reliability information.
- the remaining configuration is the same as that of FIG. 1.
- the A/D conversion module 3 converts the analog input Ain to the digital output with reference to the A/D conversion reference voltage Vref 1 , and outputs the A/D conversion resultant data 28 .
- the A/D operation controller 29 decides an A/D conversion resultant bit affected by noise in response to the noise detection signal 14 fed from the noise detector 11 and to the A/D conversion resultant data 28 fed from the A/D conversion module 3 , and decides the reliability of the A/D conversion resultant data 28 . Then, the A/D operation controller 29 outputs the A/D data 30 including the A/D conversion resultant data 28 and its reliability information.
- the CPU 31 makes a decision from the A/D data 30 as to whether to adopt the A/D conversion resultant data 28 or not in response to the reliability information.
- the present embodiment 4 can learn the reliability of the A/D conversion resultant data 28 affected by the sudden noise. As an example of using the reliability information, the present embodiment 4 can discard the A/D conversion resultant data 28 with the reliability below a certain level, thereby being able to improve the reliability of the A/D conversion data.
- FIG. 5 is a block diagram showing a configuration of a semiconductor device with a USB (Universal Serial Bus) function associated with an embodiment 5 in accordance with the present invention.
- the reference numeral 41 designates a USB device including a power supply terminal Vcc, an A/D conversion reference voltage terminal Vref, USB communication signal terminals D+ and D ⁇ , and a ground terminal GND.
- the reference numeral 42 designates a USB cable; and 43 designates a USB host including a power supply terminal Vcc, USB communication signal terminals D+ and D ⁇ , and a ground terminal GND.
- FIG. 6 is a block diagram showing a configuration of an embodiment 5 of the A/D converter in accordance with the present invention.
- the reference numeral 51 designates a USB communication signal D ⁇ ; and 52 designates an edge detector for detecting an edge of the USB communication signal D ⁇ , and for generating an edge detection signal 55 when it detects the occurrence of the USB communication.
- the edge detector 52 includes a constant voltage source 53 and a comparator 54 .
- the reference numeral 15 designates an A/D operation controller that is composed of SR flip-flops and the like, and generates a bit-shift signal 16 in response to the edge detection signal 55 fed from the edge detector 52 .
- the reference numeral 56 designates an A/D conversion reference voltage Vref provided by the USB communication.
- the reference numeral 17 designates an A/D conversion module for converting the analog input Ain to the digital output with reference to the A/D conversion reference voltage Vref 56 provided by the USB communication; and 18 designates an A/D controller that discards an A/D conversion resultant bit affected by noise in response to the bit-shift signal 16 fed from the A/D operation controller 15 , holds the remaining A/D conversion resultant bits, and restarts the A/D conversion from the discarded A/D conversion resultant bit after the noise becomes negligible.
- the present embodiment 5 has the USB (Universal Serial Bus) function associated with the USB device 41 , USB cable 42 and USB host 43 , and has a mode of supplying the power supply Vcc and A/D conversion reference voltage Vref from the USB host 43 to the USB device 41 through the USB cable 42 .
- the USB cable 42 has crosstalk noise occurring therein.
- the A/D conversion in accordance with the A/D conversion reference voltage Vref provided by the USB communication will degrade the A/D conversion accuracy.
- the present embodiment 5 is implemented to circumvent the degradation in the A/D conversion accuracy.
- the edge detector 52 detects the edge of the USB communication signal D ⁇ , and generates the edge detection signal 55 .
- the A/D operation controller 15 In response to the edge detection signal 55 , the A/D operation controller 15 generates the bit-shift signal 16 for removing the A/D conversion resultant bit affected by the noise using the SR flip-flops and the like.
- the A/D conversion module 17 which carries out the A/D conversion of the analog input Ain in accordance with the A/D conversion reference voltage Vref 56 provided by the USB communication, the A/D controller 18 discards the A/D conversion resultant bit affected by the noise in response to the bit-shift signal 16 fed from the A/D operation controller 15 . Then, the A/D conversion module 17 holds the remaining A/D conversion resultant bits, and restarts the A/D conversion from the discarded A/D conversion resultant bit after the noise becomes negligible.
- the present embodiment 5 can improved the reliability of the A/D conversion data by discarding the A/D conversion resultant bit affected by the crosstalk noise occurring during the USB communication.
- the present embodiment does not require any general-purpose counter, and can perform the A/D conversion with simpler operation without interrupting the A/D conversion.
- the present embodiment 5 can improve the reliability of the A/D conversion data by using simple circuits such as the edge detector 52 and A/D operation controller 15 without increasing the circuit scale.
- FIG. 7 is a block diagram showing a configuration of an embodiment 6 of the A/D converter in accordance with the present invention.
- the reference numeral 21 designates an A/D operation controller composed of SR flip-flops and the like.
- the A/D operation controller 21 generates a start signal 22 in response to the edge detection signal 55 fed from the edge detector 52 , and continues to generate an asserted A/D-stop_bit-shift signal 25 during the time from the generation of the start signal 22 to the reception of an end signal 24 from a general-purpose counter 23 .
- the general-purpose counter 23 starts counting of the fixed time period in response to the start signal 22 fed from the A/D operation controller 21 , and generates the end signal 24 at the end of the counting.
- the reference numeral 26 designates an A/D controller for discarding an A/D conversion resultant bit affected by the noise in response to the asserted A/D-stop_bit-shift signal 25 fed from the A/D operation controller 21 , and for holding the remaining A/D conversion resultant bits.
- the A/D controller 26 restarts A/D conversion from the A/D conversion resultant bit in response to the unasserted A/D-stop_bit-shift signal 25 fed from the A/D operation controller 21 .
- the remaining configuration is the same as that of FIG. 6.
- the A/D operation controller 21 in FIG. 7 interrupts the A/D conversion in response to the edge detection signal 55 using the SR flip-flops and the like, generates the asserted A/D-stop_bit-shift signal 25 for removing the A/D conversion resultant bit affected by noise, and supplies it to the A/D controller 26 .
- the A/D operation controller 21 also generates the start signal 22 , and supplies it to the general-purpose counter 23 .
- the A/D controller 26 discards the A/D conversion resultant bit affected by noise in response to the asserted A/D-stop_bit-shift signal 25 fed from the A/D operation controller 21 .
- the A/D controller 26 holds the remaining A/D conversion resultant bits.
- the general-purpose counter 23 starts counting the fixed time period in response to the start signal 22 , and supplies the end signal 24 to the A/D operation controller 21 at the end of the counting.
- the fixed time period of the general-purpose counter 23 is determined considering the pulse width of the noise at such a value that the effect of the noise on the A/D conversion can be avoided.
- the A/D operation controller 21 In response to the input of the end signal 24 , the A/D operation controller 21 , ensuring that the edge detector 52 does not generate the edge detection signal 55 , changes the A/D-stop_bit-shift signal 25 from the asserted to unasserted signal and supplies it to the A/D controller 26 .
- the A/D controller 26 restarts the A/D conversion from the discarded A/D conversion resultant bit in response to the unasserted A/D-stop_bit-shift signal 25 .
- the present embodiment 6 can improve the reliability of the A/D conversion data by discarding the A/D conversion resultant bit affected by the crosstalk noise occurring during the USB communication.
- the present embodiment 6 can prevent the adverse effect of the crosstalk noise on the A/D conversion data.
- FIG. 8 is a block diagram showing a configuration of an embodiment 7 of the A/D converter in accordance with the present invention.
- the reference numeral 27 designates a CPU that starts counting of the fixed time period on software in response to the start signal 22 fed from the A/D operation controller 21 , and generates the end signal 24 at the end of the counting.
- the remaining configuration is the same as that of FIG. 7.
- the present embodiment 7 replaces the general-purpose counter 23 of the foregoing embodiment 6 by the CPU 27 .
- the CPU 27 starts counting the fixed time period on the software in response to the start signal 22 , and supplies the end signal 24 to the A/D operation controller 21 at the end of the counting.
- the remaining operation is the same as that of the foregoing embodiment 6.
- the present embodiment 7 can improve the reliability of the A/D conversion data by discarding the A/D conversion resultant bit affected by the crosstalk noise occurring during the USB communication.
- the A/D conversion module 17 halts the A/D conversion only for the fixed time period counted by the CPU 27 from the detection of the USB communication, it can prevent the adverse effect of the crosstalk noise on the A/D conversion data.
- FIG. 9 is a block diagram showing a configuration of an embodiment 8 of the A/D converter in accordance with the present invention.
- the reference numeral 3 designates an A/D conversion module for converting the analog input Ain to the digital output in accordance with the A/D conversion reference voltage Vref 56 ; and 4 designates an A/D controller for controlling the A/D conversion module 3 .
- the reference numeral 28 designates A/D conversion resultant data output from the A/D conversion module 3 .
- the reference numeral 29 designates an A/D operation controller that decides an A/D conversion resultant bit affected by noise in response to the edge detection signal 55 fed from the edge detector 52 and to the A/D conversion resultant data 28 fed from the A/D conversion module 3 , and outputs A/D data 30 including the A/D conversion resultant data 28 and its reliability information.
- the reference numeral 31 designates a CPU for making a decision from the A/D data 30 as to whether to adopt the A/D conversion resultant data 28 or not in response to the reliability information.
- the remaining configuration is the same as that of FIG. 6.
- the A/D conversion module 3 converts the analog input Ain to the digital output with reference to the A/D conversion reference voltage Vref 56 provided through the USB communication, and outputs the A/D conversion resultant data 28 .
- the A/D operation controller 29 decides an A/D conversion resultant bit affected by noise in response to the edge detection signal 55 fed from the edge detector 52 and to the A/D conversion resultant data 28 fed from the A/D conversion module 3 , and decides the reliability of the A/D conversion resultant data 28 . Then, the A/D operation controller 29 outputs the A/D data 30 including the A/D conversion resultant data 28 and its reliability information.
- the CPU 31 makes a decision from the A/D data 30 as to whether to adopt the A/D conversion resultant data 28 or not in response to the reliability information.
- the present embodiment 8 can learn the reliability of the A/D conversion resultant data 28 affected by the crosstalk noise occurring during the USB communication. As an example of using the reliability information, the present embodiment 8 can discard the A/D conversion resultant data 28 with the reliability below a certain level, thereby being able to improve the reliability of the A/D conversion data.
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Abstract
Description
- 1. Field of the Invention
- The present invention relates to an A/D converter with noise elimination function in a semiconductor device.
- 2. Description of Related Art
- FIG. 10 is a block diagram showing a configuration of a conventional A/D converter. In FIG. 10, the
reference numeral 1 designates an A/D conversion reference voltage Vref; 2 designates a noise filtering module for removing noise from the A/D conversionreference voltage Vref 1; 3 designates an A/D conversion module for converting an analog input Ain to a digital output with reference to the A/D conversionreference voltage Vref 1; and 4 designates an A/D controller for controlling the A/D conversion module 3. - FIGS. 11A and 11B are tables illustrating a setting method of the A/D conversion reference voltage Vref of the A/D converter.
- Next, the operation of the conventional A/D converter will be described.
- In FIG. 10, the
noise filtering module 2 removes the noise of the A/D conversionreference voltage Vref 1, and supplies its output to the A/D conversion module 3. - FIG. 11A gives expressions of the relationships between the A/D conversion
reference voltage Vref 1 and the reference voltage VREF in the A/D conversion module 3; and FIG. 11B illustrates the variations in the content of the A/D conversion register in the A/D conversion module 3 during the A/D conversion. - When the A/D conversion is started, the A/D conversion register is placed at “0 . . . 0”. Subsequently, the most significant bit of the A/D conversion register is placed at “1”, and the A/D conversion
reference voltage Vref 1 is supplied to the comparator in the A/D conversion module 3, which compares the A/D conversionreference voltage Vref 1 with the analog input Ain. If the compared result is Vref<Ain, the most significant bit of the A/D conversion register is maintained at “1”, whereas if Vref>Ain, the most significant bit of the A/D conversion register is placed at “0”. - Carrying out the foregoing operation down to the least significant bit of the A/D conversion register, the A/
D conversion module 3 stores into the A/D conversion register the digital value obtained by converting the analog input Ain. - With the foregoing configuration, the conventional A/D converter cannot obtain accurate A/D conversion data when the A/D conversion
reference voltage Vref 1 includes noise. Thus, it includes thenoise filtering module 2 for removing noise from the A/D conversionreference voltage Vref 1 so as to supply the noise reduced A/D conversionreference voltage Vref 1 to the A/D conversion module 3. - However, the conventional A/D converter has a problem of being unable to obtain the accurate A/D conversion data if the A/D conversion
reference voltage Vref 1 includes noise that cannot be removed by thenoise filtering module 2. In addition, it has a problem of increasing the circuit scale because of thenoise filtering module 2. - The present invention is implemented to solve the foregoing problems. It is therefore an object of the present invention to provide an A/D converter capable of obtaining reliable A/D conversion data without increasing the circuit scale so much even if the A/D conversion reference voltage includes noise.
- According to a first aspect of the present invention, there is provided an A/D converter including: an A/D operation controller for generating a bit-shift signal in response to a detection signal fed from a detector; and an A/D conversion module for carrying out A/D conversion with reference to an A/D conversion reference voltage, for discarding an A/D conversion resultant bit affected by noise in response to the bit-shift signal, for holding remaining A/D conversion resultant bits, and for restarting the A/D conversion from the discarded A/D conversion resultant bit after the noise becomes negligible. It offers an advantage of being able to improve the reliability of the A/D conversion data by discarding the A/D conversion resultant bit affected by sudden noise or crosstalk noise during the USB communication.
- According to a second aspect of the present invention, there is provided an A/D converter including: an A/D conversion module for generating A/D conversion resultant data by carrying out A/D conversion of an analog input signal with reference to an A/D conversion reference voltage; and an A/D operation controller for deciding an A/D conversion resultant bit affected by noise in response to the detection signal and to the A/D conversion resultant data, and for outputting reliability information together with the A/D conversion resultant data. It can learn the reliability of the A/D conversion resultant data affected by the sudden noise or crosstalk noise during the USB communication. As a result, it offers an advantage of being able to improve the reliability of the A/D conversion data by discarding the A/D conversion resultant data with the reliability less than a certain level.
- FIG. 1 is a block diagram showing a configuration of an
embodiment 1 of the A/D converter in accordance with the present invention; - FIG. 2 is a block diagram showing a configuration of an
embodiment 2 of the A/D converter in accordance with the present invention; - FIG. 3 is a block diagram showing a configuration of an
embodiment 3 of the A/D converter in accordance with the present invention; - FIG. 4 is a block diagram showing a configuration of an
embodiment 4 of the A/D converter in accordance with the present invention; - FIG. 5 is a block diagram showing a configuration of a semiconductor device with a USB function associated with an
embodiment 5 in accordance with the present invention: - FIG. 6 is a block diagram showing a configuration of the
embodiment 5 of the A/D converter in accordance with the present invention; - FIG. 7 is a block diagram showing a configuration of an
embodiment 6 of the A/D converter in accordance with the present invention; - FIG. 8 is a block diagram showing a configuration of an
embodiment 7 of the A/D converter in accordance with the present invention; - FIG. 9 is a block diagram showing a configuration of an
embodiment 8 of the A/D converter in accordance with the present invention; - FIG. 10 is a block diagram showing a configuration of a conventional A/D converter; and
- FIGS. 11A and 11B are tables illustrating a setting method of the A/D conversion reference voltage of the conventional A/D converter.
- The invention will now be described with reference to the accompanying drawings.
-
Embodiment 1 - FIG. 1 is a block diagram showing a configuration of an
embodiment 1 of the A/D converter in accordance with the present invention. In this figure, thereference numeral 1 designates an A/D conversion reference voltage Vref. Thereference numeral 11 designates a noise detector for generating anoise detection signal 14 when it detects noise in the A/D conversionreference voltage Vref 1. Thenoise detector 11 includes aconstant voltage source 12 and acomparator 13. Thereference numeral 15 designates an A/D operation controller composed of SR flip-flops and the like, for generating a bit-shift signal 16 in response to thenoise detection signal 14 fed from thenoise detector 11. Thereference numeral 17 designates an A/D conversion module for converting an analog input Ain to a digital output with reference to the A/D conversionreference voltage Vref 1; and 18 designates an A/D controller that discards an A/D conversion resultant bit affected by noise in response to the bit-shift signal 16 fed from the A/D operation controller 15, holds the remaining A/D conversion resultant bits, and restarts the A/D conversion from the discarded A/D conversion resultant bit after the noise becomes negligible. - Next, the operation of the
present embodiment 1 will be described. - In FIG. 1, when any noise occurs in the A/D conversion
reference voltage Vref 1, thenoise detector 11 detects the noise, and supplies thenoise detection signal 14 to the A/D operation controller 15. In response to thenoise detection signal 14, the A/D operation controller 15 generates the bit-shift signal 16 for removing the A/D conversion resultant bit affected by the noise using the SR flip-flops and the like. In the A/D conversion module 17 which carries out the A/D conversion of the analog input Ain in accordance with the A/D conversionreference voltage Vref 1, the A/D controller 18 discards the A/D conversion resultant bit affected by the noise in response to the bit-shift signal 16 fed from the A/D operation controller 15. Then, the A/D conversion module 17, which holds the remaining A/D conversion resultant bits, restarts the A/D conversion from the discarded A/D conversion resultant bit after the noise becomes negligible. - As described above, the
present embodiment 1 can improved the reliability of the A/D conversion data by discarding the A/D conversion resultant bit affected by sudden noise. - In addition, the present embodiment does not require any general-purpose counter, and can perform the A/D conversion with simpler operation without interrupting the A/D conversion.
- Furthermore, the
present embodiment 1 can improve the reliability of the A/D conversion data by using simple circuits such as thenoise detector 11 and A/D operation controller 15 without increasing the circuit scale. -
Embodiment 2 - FIG. 2 is a block diagram showing a configuration of an
embodiment 2 of the A/D converter in accordance with the present invention. In this figure, thereference numeral 21 designates an A/D operation controller composed of SR flip-flops and the like. The A/D operation controller 21 generates astart signal 22 in response to thenoise detection signal 14 fed from thenoise detector 11, and generates an asserted A/D-stop_bit-shift signal 25 from the generation of thestart signal 22 to the reception of anend signal 24 fed from a general-purpose counter 23. The general-purpose counter 23 starts counting a fixed time period in response to thestart signal 22 fed from the A/D operation controller 21, and generates theend signal 24 at the end of the counting. Thereference numeral 26 designates an A/D controller for discarding an A/D conversion resultant bit affected by the noise in response to the asserted A/D-stop_bit-shift signal 25 fed from the A/D operation controller 21, and for holding the remaining A/D conversion resultant bits. The A/D controller 26 restarts A/D conversion from the A/D conversion resultant bit in response to an unasserted A/D-stop_bit-shift signal 25 fed from the A/D operation controller 21. The remaining configuration is the same as that of FIG. 1. - Next, the operation of the
present embodiment 2 will be described. - The A/
D operation controller 21 in FIG. 2 interrupts the A/D conversion in response to thenoise detection signal 14 using the SR flip-flops and the like, generates the asserted A/D-stop_bit-shift signal 25 for removing the A/D conversion resultant bit affected by noise, and supplies it to the A/D controller 26. The A/D operation controller 21 also generates thestart signal 22, and supplies it to the general-purpose counter 23. - In the A/
D conversion module 17 which is carrying out the A/D conversion of the analog input Ain in response to the A/D conversionreference voltage Vref 1, the A/D controller 26 discards the A/D conversion resultant bit affected by noise in response to the asserted A/D-stop_bit-shift signal 25 fed from the A/D operation controller 21. The A/D controller 26 holds the remaining A/D conversion resultant bits. - On the other hand, the general-
purpose counter 23 starts counting the fixed time period in response to thestart signal 22, and supplies theend signal 24 to the A/D operation controller 21 at the end of the counting. The fixed time period of the general-purpose counter 23 is determined considering the pulse width of the noise at such a value that the effect of the noise on the A/D conversion can be avoided. - In response to the input of the
end signal 24, the A/D operation controller 21, ensuring that thenoise detector 11 does not generate thenoise detection signal 14, changes the A/D-stop_bit-shift signal 25 from the asserted to unasserted signal and supplies it to the A/D controller 26. The A/D controller 26 restarts the A/D conversion from the discarded A/D conversion resultant bit in response to the unasserted A/D-stop_bit-shift signal 25. - As described above, the
present embodiment 2 can improve the reliability of the A/D conversion data by discarding the A/D conversion resultant bit affected by the sudden noise. - In addition, since the A/
D conversion module 17 halts the A/D conversion only for the fixed time period counted by the general-purpose counter 23 from the noise detection, thepresent embodiment 2 can prevent the adverse effect of the noise on the A/D conversion data. -
Embodiment 3 - FIG. 3 is a block diagram showing a configuration of an
embodiment 3 of the A/D converter in accordance with the present invention. In this figure, thereference numeral 27 designates a CPU that starts counting a fixed time period on software in response to thestart signal 22 fed from the A/D operation controller 21, and generates theend signal 24 at the end of the counting. The remaining configuration is the same as that of FIG. 2. - Next, the operation of the
present embodiment 3 will be described. - The
present embodiment 3 replaces the general-purpose counter 23 of the foregoingembodiment 2 by theCPU 27. - In FIG. 3, the
CPU 27 starts counting the fixed time period on the software in response to thestart signal 22 fed from the A/D operation controller 21, and supplies theend signal 24 to the A/D operation controller 21 at the end of the counting. The remaining operation is the same as that of the foregoingembodiment 2. - As described above, the
present embodiment 3 can improve the reliability of the A/D conversion data by discarding the A/D conversion resultant bit affected by sudden noise. - In addition, since the A/
D conversion module 17 halts the A/D conversion only for the fixed time period counted by theCPU 27 from the detection of the noise, it can prevent the adverse effect of the noise on the A/D conversion data. - Furthermore, using the
CPU 27 can obviate the need for the general-purpose counter 23. -
Embodiment 4 - FIG. 4 is a block diagram showing a configuration of an
embodiment 4 of the A/D converter in accordance with the present invention. In this figure, thereference numeral 3 designates an A/D conversion module for converting the analog input Ain to the digital output in accordance with the A/D conversionreference voltage Vref 1; and 4 designates an A/D controller for controlling the A/D conversion module 3. Thereference numeral 28 designates A/D conversion resultant data output from the A/D conversion module 3. - The
reference numeral 29 designates an A/D operation controller that decides an A/D conversion resultant bit affected by noise in response to thenoise detection signal 14 fed from thenoise detector 11 and to the A/D conversionresultant data 28 fed from the A/D conversion module 3, and outputs A/D data 30 including the A/D conversionresultant data 28 and its reliability information. Thereference numeral 31 designates a CPU for making a decision from the A/D data 30 as to whether to adopt the A/D conversionresultant data 28 or not in response to the reliability information. The remaining configuration is the same as that of FIG. 1. - Next, the operation of the
present embodiment 4 will be described. - The A/
D conversion module 3 converts the analog input Ain to the digital output with reference to the A/D conversionreference voltage Vref 1, and outputs the A/D conversionresultant data 28. - The A/
D operation controller 29 decides an A/D conversion resultant bit affected by noise in response to thenoise detection signal 14 fed from thenoise detector 11 and to the A/D conversionresultant data 28 fed from the A/D conversion module 3, and decides the reliability of the A/D conversionresultant data 28. Then, the A/D operation controller 29 outputs the A/D data 30 including the A/D conversionresultant data 28 and its reliability information. - The
CPU 31 makes a decision from the A/D data 30 as to whether to adopt the A/D conversionresultant data 28 or not in response to the reliability information. - As described above, the
present embodiment 4 can learn the reliability of the A/D conversionresultant data 28 affected by the sudden noise. As an example of using the reliability information, thepresent embodiment 4 can discard the A/D conversionresultant data 28 with the reliability below a certain level, thereby being able to improve the reliability of the A/D conversion data. -
Embodiment 5 - FIG. 5 is a block diagram showing a configuration of a semiconductor device with a USB (Universal Serial Bus) function associated with an
embodiment 5 in accordance with the present invention. In this figure, thereference numeral 41 designates a USB device including a power supply terminal Vcc, an A/D conversion reference voltage terminal Vref, USB communication signal terminals D+ and D−, and a ground terminal GND. Thereference numeral 42 designates a USB cable; and 43 designates a USB host including a power supply terminal Vcc, USB communication signal terminals D+ and D−, and a ground terminal GND. - FIG. 6 is a block diagram showing a configuration of an
embodiment 5 of the A/D converter in accordance with the present invention. In this figure, thereference numeral 51 designates a USB communication signal D−; and 52 designates an edge detector for detecting an edge of the USB communication signal D−, and for generating anedge detection signal 55 when it detects the occurrence of the USB communication. Theedge detector 52 includes aconstant voltage source 53 and acomparator 54. Thereference numeral 15 designates an A/D operation controller that is composed of SR flip-flops and the like, and generates a bit-shift signal 16 in response to theedge detection signal 55 fed from theedge detector 52. - The
reference numeral 56 designates an A/D conversion reference voltage Vref provided by the USB communication. Thereference numeral 17 designates an A/D conversion module for converting the analog input Ain to the digital output with reference to the A/D conversionreference voltage Vref 56 provided by the USB communication; and 18 designates an A/D controller that discards an A/D conversion resultant bit affected by noise in response to the bit-shift signal 16 fed from the A/D operation controller 15, holds the remaining A/D conversion resultant bits, and restarts the A/D conversion from the discarded A/D conversion resultant bit after the noise becomes negligible. - Next, the operation of the
present embodiment 5 will be described. - In FIG. 5, the
present embodiment 5 has the USB (Universal Serial Bus) function associated with theUSB device 41,USB cable 42 andUSB host 43, and has a mode of supplying the power supply Vcc and A/D conversion reference voltage Vref from theUSB host 43 to theUSB device 41 through theUSB cable 42. In the USB communication using the USB communication signals D+ and D−, theUSB cable 42 has crosstalk noise occurring therein. As a result, the A/D conversion in accordance with the A/D conversion reference voltage Vref provided by the USB communication will degrade the A/D conversion accuracy. Thepresent embodiment 5 is implemented to circumvent the degradation in the A/D conversion accuracy. - In FIG. 6, when the USB communication takes place using the USB communication signal D−, the
edge detector 52 detects the edge of the USB communication signal D−, and generates theedge detection signal 55. In response to theedge detection signal 55, the A/D operation controller 15 generates the bit-shift signal 16 for removing the A/D conversion resultant bit affected by the noise using the SR flip-flops and the like. In the A/D conversion module 17 which carries out the A/D conversion of the analog input Ain in accordance with the A/D conversionreference voltage Vref 56 provided by the USB communication, the A/D controller 18 discards the A/D conversion resultant bit affected by the noise in response to the bit-shift signal 16 fed from the A/D operation controller 15. Then, the A/D conversion module 17 holds the remaining A/D conversion resultant bits, and restarts the A/D conversion from the discarded A/D conversion resultant bit after the noise becomes negligible. - As described above, the
present embodiment 5 can improved the reliability of the A/D conversion data by discarding the A/D conversion resultant bit affected by the crosstalk noise occurring during the USB communication. - In addition, the present embodiment does not require any general-purpose counter, and can perform the A/D conversion with simpler operation without interrupting the A/D conversion.
- Furthermore, the
present embodiment 5 can improve the reliability of the A/D conversion data by using simple circuits such as theedge detector 52 and A/D operation controller 15 without increasing the circuit scale. -
Embodiment 6 - FIG. 7 is a block diagram showing a configuration of an
embodiment 6 of the A/D converter in accordance with the present invention. In this figure, thereference numeral 21 designates an A/D operation controller composed of SR flip-flops and the like. The A/D operation controller 21 generates astart signal 22 in response to theedge detection signal 55 fed from theedge detector 52, and continues to generate an asserted A/D-stop_bit-shift signal 25 during the time from the generation of thestart signal 22 to the reception of anend signal 24 from a general-purpose counter 23. The general-purpose counter 23 starts counting of the fixed time period in response to thestart signal 22 fed from the A/D operation controller 21, and generates theend signal 24 at the end of the counting. Thereference numeral 26 designates an A/D controller for discarding an A/D conversion resultant bit affected by the noise in response to the asserted A/D-stop_bit-shift signal 25 fed from the A/D operation controller 21, and for holding the remaining A/D conversion resultant bits. The A/D controller 26 restarts A/D conversion from the A/D conversion resultant bit in response to the unasserted A/D-stop_bit-shift signal 25 fed from the A/D operation controller 21. The remaining configuration is the same as that of FIG. 6. - Next, the operation of the
present embodiment 6 will be described. - The A/
D operation controller 21 in FIG. 7 interrupts the A/D conversion in response to theedge detection signal 55 using the SR flip-flops and the like, generates the asserted A/D-stop_bit-shift signal 25 for removing the A/D conversion resultant bit affected by noise, and supplies it to the A/D controller 26. The A/D operation controller 21 also generates thestart signal 22, and supplies it to the general-purpose counter 23. - In the A/
D conversion module 17 which is carrying out the A/D conversion of the analog input Ain in response to the A/D conversionreference voltage Vref 1, the A/D controller 26 discards the A/D conversion resultant bit affected by noise in response to the asserted A/D-stop_bit-shift signal 25 fed from the A/D operation controller 21. The A/D controller 26 holds the remaining A/D conversion resultant bits. - On the other hand, the general-
purpose counter 23 starts counting the fixed time period in response to thestart signal 22, and supplies theend signal 24 to the A/D operation controller 21 at the end of the counting. The fixed time period of the general-purpose counter 23 is determined considering the pulse width of the noise at such a value that the effect of the noise on the A/D conversion can be avoided. - In response to the input of the
end signal 24, the A/D operation controller 21, ensuring that theedge detector 52 does not generate theedge detection signal 55, changes the A/D-stop_bit-shift signal 25 from the asserted to unasserted signal and supplies it to the A/D controller 26. The A/D controller 26 restarts the A/D conversion from the discarded A/D conversion resultant bit in response to the unasserted A/D-stop_bit-shift signal 25. - As described above, the
present embodiment 6 can improve the reliability of the A/D conversion data by discarding the A/D conversion resultant bit affected by the crosstalk noise occurring during the USB communication. - In addition, since the A/
D conversion module 17 halts the A/D conversion only for the fixed time period counted by the general-purpose counter 23 from the detection of the USB communication, thepresent embodiment 6 can prevent the adverse effect of the crosstalk noise on the A/D conversion data. -
Embodiment 7 - FIG. 8 is a block diagram showing a configuration of an
embodiment 7 of the A/D converter in accordance with the present invention. In this figure, thereference numeral 27 designates a CPU that starts counting of the fixed time period on software in response to thestart signal 22 fed from the A/D operation controller 21, and generates theend signal 24 at the end of the counting. The remaining configuration is the same as that of FIG. 7. - Next, the operation of the
present embodiment 7 will be described. - The
present embodiment 7 replaces the general-purpose counter 23 of the foregoingembodiment 6 by theCPU 27. - In FIG. 8, the
CPU 27 starts counting the fixed time period on the software in response to thestart signal 22, and supplies theend signal 24 to the A/D operation controller 21 at the end of the counting. The remaining operation is the same as that of the foregoingembodiment 6. - As described above, the
present embodiment 7 can improve the reliability of the A/D conversion data by discarding the A/D conversion resultant bit affected by the crosstalk noise occurring during the USB communication. - In addition, since the A/
D conversion module 17 halts the A/D conversion only for the fixed time period counted by theCPU 27 from the detection of the USB communication, it can prevent the adverse effect of the crosstalk noise on the A/D conversion data. - Furthermore, using the
CPU 27 can obviate the need for the general-purpose counter 23. -
Embodiment 8 - FIG. 9 is a block diagram showing a configuration of an
embodiment 8 of the A/D converter in accordance with the present invention. In this figure, thereference numeral 3 designates an A/D conversion module for converting the analog input Ain to the digital output in accordance with the A/D conversionreference voltage Vref 56; and 4 designates an A/D controller for controlling the A/D conversion module 3. Thereference numeral 28 designates A/D conversion resultant data output from the A/D conversion module 3. - The
reference numeral 29 designates an A/D operation controller that decides an A/D conversion resultant bit affected by noise in response to theedge detection signal 55 fed from theedge detector 52 and to the A/D conversionresultant data 28 fed from the A/D conversion module 3, and outputs A/D data 30 including the A/D conversionresultant data 28 and its reliability information. Thereference numeral 31 designates a CPU for making a decision from the A/D data 30 as to whether to adopt the A/D conversionresultant data 28 or not in response to the reliability information. The remaining configuration is the same as that of FIG. 6. - Next, the operation of the
present embodiment 8 will be described. - The A/
D conversion module 3 converts the analog input Ain to the digital output with reference to the A/D conversionreference voltage Vref 56 provided through the USB communication, and outputs the A/D conversionresultant data 28. - The A/
D operation controller 29 decides an A/D conversion resultant bit affected by noise in response to theedge detection signal 55 fed from theedge detector 52 and to the A/D conversionresultant data 28 fed from the A/D conversion module 3, and decides the reliability of the A/D conversionresultant data 28. Then, the A/D operation controller 29 outputs the A/D data 30 including the A/D conversionresultant data 28 and its reliability information. - The
CPU 31 makes a decision from the A/D data 30 as to whether to adopt the A/D conversionresultant data 28 or not in response to the reliability information. - As described above, the
present embodiment 8 can learn the reliability of the A/D conversionresultant data 28 affected by the crosstalk noise occurring during the USB communication. As an example of using the reliability information, thepresent embodiment 8 can discard the A/D conversionresultant data 28 with the reliability below a certain level, thereby being able to improve the reliability of the A/D conversion data.
Claims (8)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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JP2002124722A JP3889659B2 (en) | 2002-04-25 | 2002-04-25 | A / D converter |
JP2002-124722 | 2002-04-25 |
Publications (2)
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US6639540B1 US6639540B1 (en) | 2003-10-28 |
US20030201925A1 true US20030201925A1 (en) | 2003-10-30 |
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US10/326,055 Expired - Fee Related US6639540B1 (en) | 2002-04-25 | 2002-12-23 | A/D converter with noise elimination function |
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US (1) | US6639540B1 (en) |
JP (1) | JP3889659B2 (en) |
KR (1) | KR20030084580A (en) |
Cited By (1)
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JP2013191976A (en) * | 2012-03-13 | 2013-09-26 | Renesas Electronics Corp | Integrated circuit |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
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DE102004025300A1 (en) * | 2004-05-19 | 2005-12-15 | Micronas Gmbh | Device and method for noise suppression |
JP4629542B2 (en) * | 2005-09-27 | 2011-02-09 | ジーイー・メディカル・システムズ・グローバル・テクノロジー・カンパニー・エルエルシー | Sudden noise removal device |
JP5531797B2 (en) * | 2010-06-15 | 2014-06-25 | ソニー株式会社 | Solid-state imaging device and camera system |
JP2015133631A (en) * | 2014-01-14 | 2015-07-23 | 三菱電機株式会社 | Analog-digital converter |
JP2016128967A (en) * | 2015-01-09 | 2016-07-14 | 住友電気工業株式会社 | Electronic apparatus |
JP6225240B2 (en) * | 2016-12-20 | 2017-11-01 | ルネサスエレクトロニクス株式会社 | Integrated circuit |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP3288694B2 (en) * | 1990-06-11 | 2002-06-04 | 沖電気工業株式会社 | Microcomputer |
JP2777291B2 (en) * | 1991-04-30 | 1998-07-16 | 株式会社東芝 | Analog / digital mixed circuit |
WO1992022060A1 (en) * | 1991-05-29 | 1992-12-10 | Pacific Microsonics, Inc. | Improved signal encode/decode system |
JPH0895710A (en) * | 1994-09-26 | 1996-04-12 | Fujitsu Ltd | Unit and method for controlling ad converter |
JP2001111422A (en) | 1999-10-13 | 2001-04-20 | Meidensha Corp | Comparing type a/d conversion circuit |
-
2002
- 2002-04-25 JP JP2002124722A patent/JP3889659B2/en not_active Expired - Fee Related
- 2002-12-23 US US10/326,055 patent/US6639540B1/en not_active Expired - Fee Related
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2003
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2013191976A (en) * | 2012-03-13 | 2013-09-26 | Renesas Electronics Corp | Integrated circuit |
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KR20030084580A (en) | 2003-11-01 |
JP2003318733A (en) | 2003-11-07 |
JP3889659B2 (en) | 2007-03-07 |
US6639540B1 (en) | 2003-10-28 |
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