US20030141567A1 - Method of improving copper interconnects of semiconductor devices for bonding - Google Patents
Method of improving copper interconnects of semiconductor devices for bonding Download PDFInfo
- Publication number
- US20030141567A1 US20030141567A1 US10/383,042 US38304203A US2003141567A1 US 20030141567 A1 US20030141567 A1 US 20030141567A1 US 38304203 A US38304203 A US 38304203A US 2003141567 A1 US2003141567 A1 US 2003141567A1
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- layer
- metal
- semiconductor device
- copper
- bond pad
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present invention relates to improved bonding of conductors with the bond pads of semiconductor devices, such as the bonding of wires to the bond pads of semiconductor devices and lead frames associated therewith or the bonding of the conductor leads in TAB tape bonding to the bond pads of semiconductor devices. More specifically, the present invention relates to improved bonds with copper bond pads of semiconductor devices, such as wire bonding or improved conductor lead bonding of TAB tape to the copper bond pads of semiconductor devices.
- a single semiconductor die (or chip) is typically mounted within a sealed package.
- the package protects the semiconductor die from damage and from contaminants in the surrounding environment.
- the package provides a substantial lead system for connection the electrical devices formed on the die to a printed circuit board or any other desired suitable external circuitry.
- Each semiconductor die comprises a substrate having a lower surface (commonly referred to as the back of the die) that is devoid of circuitry, and an upper surface (commonly referred to as the active surface or face of the die) having integrated circuitry constructed thereon.
- the integrated circuitry is electrically accessible via bond pads located on the active surface of the semiconductor die which may be arranged in a wide variety of patterns, such as around the periphery of the semiconductor die, the center of the semiconductor die, both, etc.
- One of the problems associated with the decreasing size of the semiconductor die and the increasing amount of circuitry included in the semiconductor die is the need to, at least, maintain the speed at which the semiconductor die operates and, if possible, to increase the operating speed of the semiconductor die. Since aluminum is typically used as the material for the connecting circuits of the semiconductor die, with smaller circuit line widths of aluminum it is difficult to maintain or increase the speed of the semiconductor die. Further, it is necessary to connect an ever increasing number of bond pads on the active surface of the semiconductor die with an ever increasing number of lead fingers of the lead frame or other type conductors, such as the conductor leads of TAB tape. In each instance, the use of a more conductive material for the connecting circuits of the semiconductor die connecting to the bond pads on the active surface of the semiconductor die is required.
- the initial component in the packaging process is a leadframe.
- the leadframe is a metal frame which supports the semiconductor die for packaging and provides the leads for the final semiconductor package.
- a typical leadframe strip is produced from metal sheet stock (usually a copper, copper alloy, alloy 42 , etc.) and is adapted to mount the semiconductor die.
- a conventional leadframe has the semiconductor die adhesively mounted on a die paddle of the leadframe while the lead fingers (leads) extend around the periphery of the semiconductor die (the edges) terminating adjacent thereto. Subsequently, wire bonds are made to connect the bond pads on the active surface of the semiconductor die to the appropriate lead finger of the leadframe. After the wire bonding operation, the lead frame and semiconductor die are encapsulated in a transfer die molding process. After encapsulation, the lead frame is trimmed with the remainder of the individual lead fingers being formed into the desired packaging configuration.
- the lead fingers of the lead frame extend over the active surface of the semiconductor die being insulated therefrom by tape which is adhesively bonded to the active surface of the semiconductor die and the bottom of the lead fingers. In this manner, the semiconductor die is supported directly from the lead fingers of the leadframe. Electrical connections are made between the lead finger of the lead frame and the bond pads on the active surface of the semiconductor die by way of wire bonds extending therebetween. After wire bonding, the leadframe and semiconductor die are encapsulated in suitable plastic material. Subsequently, the lead fingers are trimmed and formed to the desired configuration to complete the packaged semiconductor device assembly.
- LOC Leads-Over-Chip
- the tape used to bond to the lead fingers of the leadframe does not adequately lock the lead fingers in position for the wire bonding process.
- the adhesive on the tape is not strong enough to fix or lock the lead fingers in position for wire bonding as the lead fingers pull away from the tape before wire bonding.
- the lead fingers will pull away from the tape after wire bonding of the semiconductor die but before encapsulation of the semiconductor die and leadframe either causing shorts between adjacent wire bonds or causing the wire bonds to pull loose from either the bond pads of the semiconductor die or lead finger of the leadframe.
- the present invention relates to improved wire bonds with the bond pads of semiconductor devices and either the lead fingers of lead frames or the conductor leads of TAB tape. More specifically, the present invention relates to improved wire bonds and improved conductor lead bonds of TAB tape to the bond pads of a semiconductor device wherein the bond pads comprise a copper layer and at least one layer of metal covering a portion of the copper layer.
- FIG. 1 is a cross-sectional view of a portion of a semiconductor die having a plurality of copper bond pads thereon having one or more layers metal thereon;
- FIGS. 2A through 2F are views of a portion of a semiconductor device having a bond pad of the present invention located thereon having a wire bond formed thereon;
- FIGS. 3A through 3C are view of a portion of a semiconductor device illustrating the formation of a bond pad thereon of the present invention having a wire bond formed thereon;
- FIGS. 4A through 4D are views of a portion of a semiconductor device having a bond pad of the present invention located thereon with a conductor lead of a TAB tape bonded thereto;
- FIGS. 5A through 5J are drawings illustrating processes of forming a bond pad of the present invention on a semiconductor device and a subsequent wire bond and bond of a conductor lead of a TAB tape therewith.
- a portion of a semiconductor die 10 is illustrated having a plurality of bond pads 12 located on the active surface 14 thereof having a layer of insulating material 13 , and a passivation layer, thereon.
- the semiconductor device 10 may be of any desired type having any desired configuration of bond pads 12 connected to the active circuitry therein.
- bond pads 12 include a copper metal layer base 12 ′ and one or more additional metal layers 12 ′′ thereon to facilitate the formation of an acceptable wire bonds using well known alloys of metal for the wire to the bond pads 12 .
- the wire bond may be formed or secured to the bond pads 12 by any desired well known wire bonding apparatus used in the industry using any desired type of wire, such as aluminum, copper, copper alloy, aluminum-copper alloy, gold, silver, gold-silver alloy, platinum, etc., although gold wire is preferred to be used as gold does not form an oxide after the deposition thereof on the bond pad 12 as would aluminum, silver, etc.
- the bond pad 12 may be comprised of layers of different metals to enhance bonding characteristics.
- layer 12 ′ is of copper metal such as used for the circuits of the semiconductor device 10 , i.e., copper metal, a copper alloy, etc.
- the layer 12 ′′ would be of gold, gold alloy, silver, silver alloy, palladium and alloys thereof, noble metals and alloys thereof, nickel and alloys thereof, nickel and gold alloys, zincated copper, etc.
- the layer 12 ′′ may further include an additional intermediate layer of metal or other materials to help prevent intermetallic compounds from forming between the copper layer 12 ′ and layer 12 ′′ and or for adhesion purposes.
- the layer 12 ′′ may commonly comprise a layer of TaN, TiN, Ni alloys, etc. If a gold wire is used for wire bonding, the metal layer 12 ′′ may typically by a gold or gold alloy metal layer. In this manner by forming the bond pad 12 of multiple layers of metal, a strong bond between the wire used for wire bonding and the copper metal layer 12 ′ of the bond pad 12 may be formed, particularly since gold does not form an oxide coating after the deposition thereof to affect any subsequent bond of material thereto.
- one layer of the metal layer 12 ′′ of multiple metal layers 12 ′′ may be a layer of metal forming a barrier to prevent any copper from the layer 12 ′ migrating therethrough or any metal of the metal layer 12 ′′ from migrating to the copper layer 12 ′. Additionally, one layer of the metal layer 12 ′′ may be a layer of metal for adhesion promoting purposes to either the copper layer 12 ′ or the metal layer 12 ′′.
- FIGS. 2A through 2C a process for forming multi-layer bond pads 12 on the active surface 14 is illustrated.
- a portion of a semiconductor device 10 is shown in drawing FIG. 2A having a copper layer 12 ′ forming a portion of the bond pad 12 .
- Illustrated in drawing FIG. 2B is a layer of metal 12 ′′ overlying the layer 12 ′ of the bond pad 12 .
- the layer of metal 12 ′′ may be selectively plated by well known techniques over the copper layer 12 ′.
- the layer of metal 12 ′′ having good properties for the wire bonding of a wire 20 to the bond pad 12 .
- a wire 20 is bonded by well known wire bonding apparatus to the layer of metal 12 ′′ of the bond pad 12 using a wire bond ball 22 .
- a portion of a semiconductor device 10 is shown having a bond pad 12 thereon with the copper layer 12 ′ located thereon having the upper surface thereof located at approximately the same level as the active surface 14 to the device 10 , the surface 14 having a layer of insulation (typically a passivation layer of an insulating oxide or insulating nitride) 13 thereon.
- the copper layer 12 ′ of bond pad 12 has a suitable metal layer 12 ′′ selectively plated thereon using well known plating processes. The function of the metal layer 12 ′′ being to provide a good metal to which an effective wire bond may be formed using well known wire bonding apparatus.
- a wire 20 is wire bonded to metal layer 12 ′′ using a ball 22 formed on the end of the wire 20 using any well known suitable wire bonding apparatus.
- the portion of the metal layer 12 ′′ on the bond pad 12 located under ball 22 of the wire 20 of the wire bond thereto may be consumed during the wire bonding process thereby allowing the ball 22 of the wire 20 of the wire bond to make direct contact with the copper layer 12 ′ of the bond pad 12 .
- the metal layer 12 ′′ is gold and the ball 22 of wire 20 is gold wire
- the metal layer 12 ′′ located under the ball 22 will become part of the ball 22 during the wire bonding process with the ball 22 being bonded to the copper layer 12 ′ of the bond pad 12 .
- a wire 20 is wired bonded to copper layer 12 ′ with the ball 22 on the end of wire 20 consuming or adding part of the metal layer 12 ′′ during the bonding process forming the ball 22 on the end of wire 20 connecting the wire 20 to the copper layer 12 ′.
- a portion of a semiconductor device 10 is shown having a bond pad 12 thereon with the copper layer 12 ′ located thereon having the upper surface thereof located at approximately the same level as the active surface 14 to the device 10 , the surface 14 having a layer of insulation (typically a passivation layer of an insulating oxide or insulating nitride) 13 thereon.
- the copper layer 12 ′ of bond pad 12 has a barrier layer 12 ′′′ formed of a suitable material having a suitable metal layer 12 ′′ selectively plated thereon using well known plating processes.
- barrier layer 12 ′′′ being to help prevent interaction between the copper layer 12 ′ and the suitable metal layer 12 ′′ of the bond pad 12 and/or to help prevent or decrease the growth of intermetallics between the metal layer 12 ′ and the metal layer 12 ′′.
- barrier materials such as titanium, tungsten, tantalum, nickel, tantalum-nickel alloys, titanium-nickel alloys, titanium-tungsten alloys, etc. are frequently used in conjunction with aluminum alloy interconnects.
- a barrier layer of nickel between copper and tin will decrease the growth of tin-copper intermetallics.
- the layers of metal forming the bond pads 12 also occasionally are silicided, or have a refractory interconnect material, such as molybdenum, tungsten, or tungsten silicide as part thereof.
- the function of the metal layer 12 ′′ being to provide a good metal to which an effective wire bond may be formed using well known wire bonding apparatus, such as a metal layer 12 ′′ of gold when gold wire 20 is being used for wire bonding.
- a wire 20 is wired bonded to barrier layer 12 ′′′ with the ball 22 on the end of wire 20 consuming part of the metal layer 12 ′′ during the bonding process forming the ball 22 on the end of wire 20 connecting the wire 20 to the barrier layer 12 ′′′.
- FIGS. 3A through 3C a portion of a semiconductor device 10 is shown wherein a layer of copper 12 ′ is deposited on the substrate 11 using any desired well known process having a thin layer of metal 12 ′′, as described hereinbefore, deposited thereon.
- the thin layer of metal 12 ′′ may be deposited on the copper layer 12 ′ be any well known process, such a sputter deposition, electrodeposited, electroless deposition, etc.
- the portion of the semiconductor device 10 is shown after the copper layer 12 ′ and layer of metal 12 ′′ deposited thereon have been patterned using well known techniques to apply a photoresist in a desired pattern with the subsequent etching of the copper layer 12 ′ and layer of metal 12 ′′ to form a bond pad 12 on the substrate 11 of the semiconductor device 10 .
- the copper layer 12 ′ and layer of metal 12 ′′ deposited thereon may be any desired shape, size, and number for the desired number of bond pads 12 on the substrate 11 .
- the copper layer 12 ′ may include at least two or more layers of metal with the upper layer being a copper layer thereby forming a stack of layers of differing metal with the upper layer being a copper layer.
- FIG. 3C a portion of the semiconductor device 10 is shown having a wire 20 bonded to the layer of metal 12 ′′ of the bond pad 12 using a ball type bond 22 thereto for wire bonding using any desired well known wire bonding apparatus.
- the semiconductor substrate 11 includes a layer of insulating material 13 , as described hereinbefore, on active surface 14 thereof surrounding the bond pad 12 .
- FIG. 4A a portion of a semiconductor device 10 is shown having a bond pad 12 thereon with the copper layer 12 ′ located thereon having the upper surface thereof located at approximately the same level as the active surface 14 to the device 10 , the surface 14 having a layer of insulation (typically a passivation layer of an insulating oxide or insulating nitride) 13 thereon.
- the copper layer 12 ′ of bond pad 12 has a suitable metal layer 12 ′′ selectively plated thereon using well known plating processes. The function of the metal layer 12 ′′ being to provide a good metal to which an effective wire bond may be formed using well known wire bonding apparatus.
- the copper layer 12 ′ of bond pad 12 has a suitable barrier layer 12 ′′′ located between the copper layer 12 ′ and the suitable metal layer 12 ′′, such as described hereinbefore.
- FIG. 4C a portion of a semiconductor device 10 is shown having a bond pad 12 thereon having a copper layer 12 ′ located thereon having a portion bonded thereto of a conductor lead 22 (numeral 22 previously referred to as “ball 22 ”) located on a portion of a substrate 24 of a portion of a TAB tape 21 .
- the surface 14 of substrate 11 of the semiconductor device 10 has a layer of insulation (typically a passivation layer of an insulating oxide or insulating nitride) 13 thereon. Also illustrated in drawing FIG.
- the function of the metal layer 12 ′′ is to provide a good metal to which an effective bond may be formed using well known bonding apparatus to the conductive lead 22 of the TAB tape 20 .
- the conductive lead 22 of the TAB tape may be of any suitable metal, such as copper, copper alloys, etc.
- the metal layer 12 ′′ may be of any suitable metal, such as described herein.
- FIG. 4D a portion of a semiconductor device 10 is shown having a bond pad 12 thereon having a copper layer 12 ′ located thereon having a barrier layer 12 ′′′ located thereon having, in turn, a metal layer 12 ′′ located thereon.
- the metal layer 12 ′′ of the bond pad 12 is bonded to a portion of a conductor lead 22 located on a portion of a substrate 24 of a portion of a TAB tape 20 .
- the conductor lead 22 of the portion of the TAB tape 21 including a layer 26 of suitable metal located thereon for the bonding of the conductor lead 22 to the metal layer 12 ′′ of the bond pad 12 of the semiconductor device 10 .
- the surface 14 of substrate 11 of the semiconductor device 10 has a layer of insulation (typically a passivation layer of an insulating oxide or insulating nitride) 13 thereon.
- the function of the metal layer 12 ′′ is to provide a good metal to which an effective bond may be formed using well known bonding apparatus to the metal layer 26 of the conductive lead 22 of the TAB tape 20 .
- the substrate 24 and metal layer 26 may be of any suitable metal for bonding purposes, such as gold, alloys of gold, etc.
- the conductive lead 22 of the TAB tape may be of any suitable metal, such as copper, copper alloys, etc.
- the metal layer 12 ′′ may be of any suitable metal, such as described herein.
- the barrier layer 12 ′′′ may be of any suitable metal or material, such as described herein.
- FIGS. 5A through 5J various differing processes for the formation of the bond pad 12 including a copper layer 12 ′ and a layer of metal 12 ′′ and, if desired, a barrier layer 12 ′′′ are illustrated.
- a process 100 for the formation of a bond pad 12 including a copper layer 12 ′ and a layer of metal 12 ′′ thereon for wire bonding purposes as described hereinbefore is illustrated.
- a substrate 11 as described hereinbefore for a semiconductor device 10 has a layer of copper or copper alloy 12 ′ deposited thereon using any desired deposition process.
- a layer of metal 12 ′′ is deposited on the copper layer 12 ′ using any well known deposition process for deposition.
- step 106 the copper layer 12 ′ and layer of metal 12 ′ is patterned and etched to form the desired shape, number, and pattern for the bond pads 12 on the active surface 14 of the substrate 11 of the semiconductor device 10 .
- a layer of insulation 13 is typically applied to the active surface 14 of the substrate 11 to protect the circuitry formed thereon of the semiconductor device 10 .
- the semiconductor device may be assembled to a lead frame (not shown) for wire bonding a wire 20 to the bond pad 12 of the semiconductor device 10 using any suitable wire bonding process 108 and apparatus.
- a process 200 for the formation of a bond pad 12 including a copper layer 12 ′ and a layer of metal 12 ′′ thereon for wire bonding purposes as described hereinbefore is illustrated.
- a substrate 11 as described hereinbefore for a semiconductor device 10 has a layer of copper or copper alloy 12 ′ deposited thereon using any desired deposition process.
- the copper layer 12 ′ is patterned and etched to form the desired shape, number, and pattern for the bond pads 12 on the active surface 14 of the substrate 11 of the semiconductor device 10 .
- the layer of metal 12 ′′ is deposited on the copper layer 12 ′ using any desired deposition process, as described hereinbefore, such as electrodepositon, electroless deposition, etc. to form the bond pad 12 having a copper layer 12 ′ and layer of metal 12 ′′ thereon for good wire bonding properties.
- a layer of insulation 13 is typically applied to the active surface 14 of the substrate 11 to protect the circuitry formed thereon of the semiconductor device 10 .
- the semiconductor device may be assembled to a lead frame (not shown) for wire bonding a wire 20 to the bond pad 12 of the semiconductor device 10 using any suitable wire bonding process 208 and apparatus.
- a process 300 for the formation of a bond pad 12 including a copper layer 12 ′, a barrier layer 12 ′′′, and a layer of metal 12 ′′ thereon for wire bonding purposes as described hereinbefore is illustrated.
- a substrate 11 as described hereinbefore for a semiconductor device 10 has a layer of copper or copper alloy 12 ′ deposited thereon using any desired deposition process.
- a barrier layer 12 ′′′ of suitable material is deposited on the copper layer 12 ′ using any well known deposition process for deposition.
- step 306 the copper layer 12 ′ and barrier layer 12 ′′′ are patterned and etched to form the desired shape, number, and pattern for the bond pads 12 on the active surface 14 of the substrate 11 of the semiconductor device 10 .
- a metal layer 12 ′′ is deposited in step 308 over the barrier layer 12 ′′′ and subsequently patterned in step 310 .
- a layer of insulation 13 is typically applied to the active surface 14 of the substrate 11 to protect the circuitry formed thereon of the semiconductor device 10 .
- the semiconductor device may be assembled to a lead frame (not shown) for wire bonding a wire 20 to the bond pad 12 of the semiconductor device 10 using any suitable wire bonding process 312 and apparatus.
- a process 400 for the formation of a bond pad 12 including a copper layer 12 ′, a barrier layer 12 ′′′, and a layer of metal 12 ′′ thereon for wire bonding purposes as described hereinbefore is illustrated.
- a substrate 11 as described hereinbefore for a semiconductor device 10 has a layer of copper or copper alloy 12 ′ deposited thereon using any desired deposition process.
- a barrier layer 12 ′′′ of suitable material is deposited on the copper layer 12 ′ using any well known deposition process for deposition.
- a metal layer 12 ′′ is deposited on the barrier layer 12 ′′′.
- the copper layer 12 ′, barrier layer 12 ′′′, and metal layer 12 ′′ are patterned and etched to form the desired shape, number, and pattern for the bond pads 12 on the active surface 14 of the substrate 11 of the semiconductor device 10 .
- a layer of insulation 13 is typically applied to the active surface 14 of the substrate 11 to protect the circuitry formed thereon of the semiconductor device 10 .
- the semiconductor device may be assembled to a lead frame (not shown) for wire bonding a wire 20 to the bond pad 12 of the semiconductor device 10 using any suitable wire bonding process 410 and apparatus.
- a process 500 for the formation of a bond pad 12 including a copper layer 12 ′ and a layer of metal 12 ′′ thereon for wire bonding purposes as described hereinbefore is illustrated.
- a substrate 11 as described hereinbefore for a semiconductor device 10 has a layer of copper or copper alloy 12 ′ deposited thereon using any desired deposition process.
- at least two barrier layers 12 ′′′ are deposited on the copper layer.
- a metal layer 12 ′′ is deposited on the barrier layer 12 ′′′ using any desired deposition process, as described hereinbefore, such as electrodeposition, electroless deposition, etc.
- the copper layer 12 ′, barrier layer 12 ′′′, and metal layer 12 ′′ are patterned to form the bond pad 12 having a copper layer 12 ′, barrier layer 12 ′′′, and layer of metal 12 ′′ thereon for good wire bonding properties.
- a layer of insulation 13 is typically applied to the active surface 14 of the substrate 11 to protect the circuitry formed thereon of the semiconductor device 10 .
- the semiconductor device may be assembled to a lead frame (not shown) for wire bonding a wire 20 to the bond pad 12 of the semiconductor device 10 using any suitable wire bonding process 510 and apparatus.
- a process 600 for the formation of a bond pad 12 including a copper layer 12 ′ and a layer of metal 12 ′′ thereon for conductor lead of TAB tape bonding purposes as described hereinbefore is illustrated.
- a substrate 11 as described hereinbefore for a semiconductor device 10 has a layer of copper or copper alloy 12 ′ deposited thereon using any desired deposition process.
- a layer of metal 12 ′′ is deposited on the copper layer 12 ′ using any well known deposition process for deposition.
- step 606 the copper layer 12 ′ and layer of metal 12 ′′ is patterned and etched to form the desired shape, number, and pattern for the bond pads 12 on the active surface 14 of the substrate 11 of the semiconductor device 10 .
- a layer of insulation 13 is typically applied to the active surface 14 of the substrate 11 to protect the circuitry formed thereon of the semiconductor device 10 .
- the semiconductor device may be assembled to a conductor lead of a TAB tape (not shown) for bonding a conductor lead to the bond pad 12 of the semiconductor device 10 using any suitable bonding process 608 and apparatus.
- a process 700 for the formation of a bond pad 12 including a copper layer 12 ′ and a layer of metal 12 ′′ thereon for conductor lead of TAB tape bonding purposes as described hereinbefore is illustrated.
- a substrate 11 as described hereinbefore for a semiconductor device 10 has a layer of copper or copper alloy 12 ′ deposited thereon using any desired deposition process.
- the copper layer 12 ′ is patterned and etched to form the desired shape, number, and pattern for the bond pads 12 on the active surface 14 of the substrate 11 of the semiconductor device 10 .
- step 706 the layer of metal 12 ′′ is deposited on the copper layer 12 ′ using any desired deposition process, as described hereinbefore, such as electrodepositon, electroless deposition, etc. to form the bond pad 12 having a copper layer 12 ′ and layer of metal 12 ′′ thereon for good wire bonding properties.
- a layer of insulation 13 is typically applied to the active surface 14 of the substrate 11 to protect the circuitry formed thereon of the semiconductor device 10 .
- the semiconductor device may be assembled to a conductor lead of a TAB tape (not shown) for wire bonding a conductor lead to the bond pad 12 of the semiconductor device 10 using any suitable bonding process 708 and apparatus.
- a process 800 for the formation of a bond pad 12 including a copper layer 12 ′, a barrier layer 12 ′′′, and a layer of metal 12 ′′ thereon for conductor lead of TAB tape bonding purposes as described hereinbefore is illustrated.
- a substrate 11 as described hereinbefore for a semiconductor device 10 has a layer of copper or copper alloy 12 ′ deposited thereon using any desired deposition process.
- a barrier layer 12 ′′′ of suitable material is deposited on the copper layer 12 ′ using any well known deposition process for deposition.
- step 806 the copper layer 12 ′ and barrier layer 12 ′′′ are patterned and etched to form the desired shape, number, and pattern for the bond pads 12 on the active surface 14 of the substrate 11 of the semiconductor device 10 .
- a metal layer 12 ′′ is deposited in step 808 over the barrier layer 12 ′′′ and subsequently patterned in step 810 .
- a layer of insulation 13 is typically applied to the active surface 14 of the substrate 11 to protect the circuitry formed thereon of the semiconductor device 10 .
- the semiconductor device may be assembled to a conductor lead of a TAB tape (not shown) for bonding a conductor lead to the bond pad 12 of the semiconductor device 10 using any suitable bonding process 812 and apparatus.
- a process 900 for the formation of a bond pad 12 including a copper layer 12 ′, a barrier layer 12 ′′′, and a layer of metal 12 ′′ thereon for conductor lead of TAB tape bonding purposes as described hereinbefore is illustrated.
- a substrate 11 as described hereinbefore for a semiconductor device 10 has a layer of copper or copper alloy 12 ′ deposited thereon using any desired deposition process.
- a barrier layer 12 ′′′ of suitable material is deposited on the copper. layer 12 ′ using any well known deposition process for deposition.
- a metal layer 12 ′′ is deposited on the barrier layer 12 ′′′.
- the copper layer 12 ′, barrier layer 12 ′′′, and metal layer 12 ′′ are patterned and etched to form the desired shape, number, and pattern for the bond pads 12 on the active surface 14 of the substrate 11 of the semiconductor device 10 .
- a layer of insulation 13 is typically applied to the active surface 14 of the substrate 11 to protect the circuitry formed thereon of the semiconductor device 10 .
- the semiconductor device may be assembled to a conductor lead of a TAB tape (not shown) for bonding a conductor lead to the bond pad 12 of the semiconductor device 10 using any suitable bonding process 910 and apparatus.
- a process 1000 for the formation of a bond pad 12 including a copper layer 12 ′ and a layer of metal 12 ′′ thereon for conductor lead of TAB tape bonding purposes as described hereinbefore is illustrated.
- a substrate 11 as described hereinbefore for a semiconductor device 10 has a layer of copper or copper alloy 12 ′ deposited thereon using any desired deposition process.
- at least two barrier layers 12 ′′′ are deposited on the copper layer.
- a metal layer 12 ′′ is deposited on the barrier layer 12 ′′′ using any desired deposition process, as described hereinbefore, such as electrodeposition, electroless deposition, etc.
- the copper layer 12 ′, barrier layer 12 ′′′, and metal layer 12 ′′ are patterned to form the bond pad 12 having a copper layer 12 ′, barrier layers 12 ′′′, and layer of metal 12 ′′ thereon for good wire bonding properties.
- a layer of insulation 13 is typically applied to the active surface 14 of the substrate 11 to protect the circuitry formed thereon of the semiconductor device 10 .
- the semiconductor device may be assembled to a conductor lead of a TAB tape (not shown) for wire bonding a conductor lead to the bond pad 12 of the semiconductor device 10 using any suitable bonding process 1010 and apparatus.
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Abstract
An improved wire bond with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductor lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond wherein the bond pad on a surface of the semiconductor device comprises a layer of copper and at least one layer of metal and/or at least a barrier layer of material between the copper layer and one layer of metal on the copper layer to form a bond pad.
Description
- This application is a divisional of application Ser. No. 09/332,665, filed Jun. 14, 1999, pending.
- Field of the Invention: The present invention relates to improved bonding of conductors with the bond pads of semiconductor devices, such as the bonding of wires to the bond pads of semiconductor devices and lead frames associated therewith or the bonding of the conductor leads in TAB tape bonding to the bond pads of semiconductor devices. More specifically, the present invention relates to improved bonds with copper bond pads of semiconductor devices, such as wire bonding or improved conductor lead bonding of TAB tape to the copper bond pads of semiconductor devices.
- State of the Art: In semiconductor device manufacture, a single semiconductor die (or chip) is typically mounted within a sealed package. In general, the package protects the semiconductor die from damage and from contaminants in the surrounding environment. In addition, the package provides a substantial lead system for connection the electrical devices formed on the die to a printed circuit board or any other desired suitable external circuitry.
- Each semiconductor die comprises a substrate having a lower surface (commonly referred to as the back of the die) that is devoid of circuitry, and an upper surface (commonly referred to as the active surface or face of the die) having integrated circuitry constructed thereon. The integrated circuitry is electrically accessible via bond pads located on the active surface of the semiconductor die which may be arranged in a wide variety of patterns, such as around the periphery of the semiconductor die, the center of the semiconductor die, both, etc.
- One of the problems associated with the decreasing size of the semiconductor die and the increasing amount of circuitry included in the semiconductor die is the need to, at least, maintain the speed at which the semiconductor die operates and, if possible, to increase the operating speed of the semiconductor die. Since aluminum is typically used as the material for the connecting circuits of the semiconductor die, with smaller circuit line widths of aluminum it is difficult to maintain or increase the speed of the semiconductor die. Further, it is necessary to connect an ever increasing number of bond pads on the active surface of the semiconductor die with an ever increasing number of lead fingers of the lead frame or other type conductors, such as the conductor leads of TAB tape. In each instance, the use of a more conductive material for the connecting circuits of the semiconductor die connecting to the bond pads on the active surface of the semiconductor die is required.
- In an effort to increase the operating speeds of semiconductor die using small width circuit lines, improved techniques and processes have been developed to substitute the metal copper for aluminum in the circuit lines of the semiconductor die. However, the use of copper for circuit lines and bond pads of semiconductor die causes problems when wire bonds are used to connect the copper bond pads of the semiconductor die to the leads of a lead frame or the lead conductors of TAB tape. It is difficult to form wire bond connections using standard or conventional wire bonding equipment when forming wire bonds to connect the copper bond pads of a semiconductor die to the leads of a lead frame.
- Typically, the initial component in the packaging process is a leadframe. The leadframe is a metal frame which supports the semiconductor die for packaging and provides the leads for the final semiconductor package. A typical leadframe strip is produced from metal sheet stock (usually a copper, copper alloy, alloy42, etc.) and is adapted to mount the semiconductor die.
- A conventional leadframe has the semiconductor die adhesively mounted on a die paddle of the leadframe while the lead fingers (leads) extend around the periphery of the semiconductor die (the edges) terminating adjacent thereto. Subsequently, wire bonds are made to connect the bond pads on the active surface of the semiconductor die to the appropriate lead finger of the leadframe. After the wire bonding operation, the lead frame and semiconductor die are encapsulated in a transfer die molding process. After encapsulation, the lead frame is trimmed with the remainder of the individual lead fingers being formed into the desired packaging configuration.
- One of the problems associated with conventional leadframe configurations is that with the decreasing size of the semiconductor die and the increasing amount of circuitry included in the semiconductor die it is necessary to connect an ever increasing number of bond pads on the active surface of the semiconductor die with an ever increasing number of lead fingers of the lead frame. This requires that the bond pads on the semiconductor die be located on smaller pitch spacings and the width of the lead fingers be smaller. This, in turn, leads to smaller wire bonds on both the bond pads of the semiconductor die and the lead fingers of the leadframe which causes the wire bonds to be more highly stressed by the forces placed on them. This stress placed on the wire bonds requires that the metal of the bond pad, to which the wire bond is to be made, be highly susceptible to wire bonding and the formation of high strength wire bonds therewith when using well known wire material, such as gold, etc. and standard or conventional wire bonding equipment.
- In a Leads-Over-Chip (LOC) type lead frame configuration for an integrated circuit semiconductor device the lead fingers of the lead frame extend over the active surface of the semiconductor die being insulated therefrom by tape which is adhesively bonded to the active surface of the semiconductor die and the bottom of the lead fingers. In this manner, the semiconductor die is supported directly from the lead fingers of the leadframe. Electrical connections are made between the lead finger of the lead frame and the bond pads on the active surface of the semiconductor die by way of wire bonds extending therebetween. After wire bonding, the leadframe and semiconductor die are encapsulated in suitable plastic material. Subsequently, the lead fingers are trimmed and formed to the desired configuration to complete the packaged semiconductor device assembly.
- One of the shortcomings of the prior art LOC semiconductor die assemblies is that the tape used to bond to the lead fingers of the leadframe does not adequately lock the lead fingers in position for the wire bonding process. At times, the adhesive on the tape is not strong enough to fix or lock the lead fingers in position for wire bonding as the lead fingers pull away from the tape before wire bonding. Alternately, the lead fingers will pull away from the tape after wire bonding of the semiconductor die but before encapsulation of the semiconductor die and leadframe either causing shorts between adjacent wire bonds or causing the wire bonds to pull loose from either the bond pads of the semiconductor die or lead finger of the leadframe. As before with conventional leadframes, with the decreasing size of the semiconductor die and the increasing amount of circuitry included in the semiconductor die it is necessary to connect an ever increasing number bond pads on the active surface of the semiconductor die with an ever increasing number of lead fingers of the lead frame. This requires that the bond pads on the semiconductor die be located on smaller pitch spacings and the width of the lead fingers be smaller. This, in turn, leads to smaller wire bonds on both the bond pads and the lead fingers of the leadframe which cause the wire bonds to be more highly stressed by the forces placed on them.
- Therefore, when using copper as the metal for the formation of circuits and bond pads of a semiconductor die, a need exists for increased strength wire bonds between the lead fingers of a leadframe and the bond pads of a semiconductor die or between the conductor leads of TAB tape and the bond pads of a semiconductor die, particularly, as the size of the semiconductor die, size of the bond pads thereon, the size of the lead fingers connected by wire bonds to bond pads, and the pitch thereof, all decrease.
- It is known in the art to form bumps on the bond pads of a semiconductor die using wire bonding apparatus for subsequent bond Tape Automated Bonding (TAB) or flip-chip (face-down) assembly of bare chip die to a substrate. Such is illustrated in U.S. Pat. Nos. 4,750,666 and 5,058,798. It is also known to repair defective or broken wire bonds to bond pads of semiconductor die by forming a flattened pad over the remaining portion of the wire and, subsequently, bonding the end of another wire thereover. Such is illustrated in U.S. Pat. No. 5,550,083. Other types of wire bonding operations on the bond pads of a semiconductor die are illustrated in U.S. Pat. Nos. 5,235,212, 5,298,793, 5,343,064, 5,371,654, and 5,492,863. However, such Patents use aluminum for the circuits and bond pads of the semiconductor die rather than use copper which is difficult to make effective bonds thereto using conventional processes and equipment.
- The present invention relates to improved wire bonds with the bond pads of semiconductor devices and either the lead fingers of lead frames or the conductor leads of TAB tape. More specifically, the present invention relates to improved wire bonds and improved conductor lead bonds of TAB tape to the bond pads of a semiconductor device wherein the bond pads comprise a copper layer and at least one layer of metal covering a portion of the copper layer.
- FIG. 1 is a cross-sectional view of a portion of a semiconductor die having a plurality of copper bond pads thereon having one or more layers metal thereon;
- FIGS. 2A through 2F are views of a portion of a semiconductor device having a bond pad of the present invention located thereon having a wire bond formed thereon;
- FIGS. 3A through 3C are view of a portion of a semiconductor device illustrating the formation of a bond pad thereon of the present invention having a wire bond formed thereon;
- FIGS. 4A through 4D are views of a portion of a semiconductor device having a bond pad of the present invention located thereon with a conductor lead of a TAB tape bonded thereto; and
- FIGS. 5A through 5J are drawings illustrating processes of forming a bond pad of the present invention on a semiconductor device and a subsequent wire bond and bond of a conductor lead of a TAB tape therewith.
- The present invention will be better understood when the drawings are taken in conjunction with the following description of the invention.
- Referring to drawing FIG. 1, a portion of a
semiconductor die 10 is illustrated having a plurality ofbond pads 12 located on theactive surface 14 thereof having a layer of insulatingmaterial 13, and a passivation layer, thereon. Thesemiconductor device 10 may be of any desired type having any desired configuration ofbond pads 12 connected to the active circuitry therein. As illustrated,bond pads 12 include a coppermetal layer base 12′ and one or moreadditional metal layers 12″ thereon to facilitate the formation of an acceptable wire bonds using well known alloys of metal for the wire to thebond pads 12. The wire bond may be formed or secured to thebond pads 12 by any desired well known wire bonding apparatus used in the industry using any desired type of wire, such as aluminum, copper, copper alloy, aluminum-copper alloy, gold, silver, gold-silver alloy, platinum, etc., although gold wire is preferred to be used as gold does not form an oxide after the deposition thereof on thebond pad 12 as would aluminum, silver, etc. - As necessary, the
bond pad 12 may be comprised of layers of different metals to enhance bonding characteristics. For instance,layer 12′ is of copper metal such as used for the circuits of thesemiconductor device 10, i.e., copper metal, a copper alloy, etc. Typically, thelayer 12″ would be of gold, gold alloy, silver, silver alloy, palladium and alloys thereof, noble metals and alloys thereof, nickel and alloys thereof, nickel and gold alloys, zincated copper, etc. Thelayer 12″ may further include an additional intermediate layer of metal or other materials to help prevent intermetallic compounds from forming between thecopper layer 12′ andlayer 12″ and or for adhesion purposes. For instance, thelayer 12″ may commonly comprise a layer of TaN, TiN, Ni alloys, etc. If a gold wire is used for wire bonding, themetal layer 12″ may typically by a gold or gold alloy metal layer. In this manner by forming thebond pad 12 of multiple layers of metal, a strong bond between the wire used for wire bonding and thecopper metal layer 12′ of thebond pad 12 may be formed, particularly since gold does not form an oxide coating after the deposition thereof to affect any subsequent bond of material thereto. If desired, one layer of themetal layer 12″ ofmultiple metal layers 12″ may be a layer of metal forming a barrier to prevent any copper from thelayer 12′ migrating therethrough or any metal of themetal layer 12″ from migrating to thecopper layer 12′. Additionally, one layer of themetal layer 12″ may be a layer of metal for adhesion promoting purposes to either thecopper layer 12′ or themetal layer 12″. - Referring to drawing FIGS. 2A through 2C, a process for forming
multi-layer bond pads 12 on theactive surface 14 is illustrated. A portion of asemiconductor device 10 is shown in drawing FIG. 2A having acopper layer 12′ forming a portion of thebond pad 12. Illustrated in drawing FIG. 2B, is a layer ofmetal 12″ overlying thelayer 12′ of thebond pad 12. The layer ofmetal 12″ may be selectively plated by well known techniques over thecopper layer 12′. The layer ofmetal 12″ having good properties for the wire bonding of awire 20 to thebond pad 12. Illustrated in drawing FIG. 2C, awire 20 is bonded by well known wire bonding apparatus to the layer ofmetal 12″ of thebond pad 12 using awire bond ball 22. - Still referring to drawing FIGS. 2A through 2C, a portion of a
semiconductor device 10 is shown having abond pad 12 thereon with thecopper layer 12′ located thereon having the upper surface thereof located at approximately the same level as theactive surface 14 to thedevice 10, thesurface 14 having a layer of insulation (typically a passivation layer of an insulating oxide or insulating nitride) 13 thereon. As illustrated in drawing FIG. 2B, thecopper layer 12′ ofbond pad 12 has asuitable metal layer 12″ selectively plated thereon using well known plating processes. The function of themetal layer 12″ being to provide a good metal to which an effective wire bond may be formed using well known wire bonding apparatus. - Illustrated in drawing FIG. 2C, a
wire 20 is wire bonded tometal layer 12″ using aball 22 formed on the end of thewire 20 using any well known suitable wire bonding apparatus. In the wire bonding process, the portion of themetal layer 12″ on thebond pad 12 located underball 22 of thewire 20 of the wire bond thereto may be consumed during the wire bonding process thereby allowing theball 22 of thewire 20 of the wire bond to make direct contact with thecopper layer 12′ of thebond pad 12. For example, when themetal layer 12″ is gold and theball 22 ofwire 20 is gold wire, themetal layer 12″ located under theball 22 will become part of theball 22 during the wire bonding process with theball 22 being bonded to thecopper layer 12′ of thebond pad 12. - Referring to drawing FIG. 2D, a
wire 20 is wired bonded tocopper layer 12′ with theball 22 on the end ofwire 20 consuming or adding part of themetal layer 12″ during the bonding process forming theball 22 on the end ofwire 20 connecting thewire 20 to thecopper layer 12′. - Referring to drawing FIG. 2E, a portion of a
semiconductor device 10 is shown having abond pad 12 thereon with thecopper layer 12′ located thereon having the upper surface thereof located at approximately the same level as theactive surface 14 to thedevice 10, thesurface 14 having a layer of insulation (typically a passivation layer of an insulating oxide or insulating nitride) 13 thereon. As illustrated in drawing FIG. 2E, thecopper layer 12′ ofbond pad 12 has abarrier layer 12′″ formed of a suitable material having asuitable metal layer 12″ selectively plated thereon using well known plating processes. The function of thebarrier layer 12′″ being to help prevent interaction between thecopper layer 12′ and thesuitable metal layer 12″ of thebond pad 12 and/or to help prevent or decrease the growth of intermetallics between themetal layer 12′ and themetal layer 12″. For instance, barrier materials, such as titanium, tungsten, tantalum, nickel, tantalum-nickel alloys, titanium-nickel alloys, titanium-tungsten alloys, etc. are frequently used in conjunction with aluminum alloy interconnects. In other instances, a barrier layer of nickel between copper and tin will decrease the growth of tin-copper intermetallics. The layers of metal forming thebond pads 12 also occasionally are silicided, or have a refractory interconnect material, such as molybdenum, tungsten, or tungsten silicide as part thereof. The function of themetal layer 12″ being to provide a good metal to which an effective wire bond may be formed using well known wire bonding apparatus, such as ametal layer 12″ of gold whengold wire 20 is being used for wire bonding. - Referring to drawing FIG. 2F, a
wire 20 is wired bonded tobarrier layer 12′″ with theball 22 on the end ofwire 20 consuming part of themetal layer 12″ during the bonding process forming theball 22 on the end ofwire 20 connecting thewire 20 to thebarrier layer 12′″. - Referring to drawing FIGS. 3A through 3C, a portion of a
semiconductor device 10 is shown wherein a layer ofcopper 12′ is deposited on thesubstrate 11 using any desired well known process having a thin layer ofmetal 12″, as described hereinbefore, deposited thereon. The thin layer ofmetal 12″ may be deposited on thecopper layer 12′ be any well known process, such a sputter deposition, electrodeposited, electroless deposition, etc. - Referring to drawing FIG. 3B, the portion of the
semiconductor device 10 is shown after thecopper layer 12′ and layer ofmetal 12″ deposited thereon have been patterned using well known techniques to apply a photoresist in a desired pattern with the subsequent etching of thecopper layer 12′ and layer ofmetal 12″ to form abond pad 12 on thesubstrate 11 of thesemiconductor device 10. Thecopper layer 12′ and layer ofmetal 12″ deposited thereon may be any desired shape, size, and number for the desired number ofbond pads 12 on thesubstrate 11. Further, thecopper layer 12′ may include at least two or more layers of metal with the upper layer being a copper layer thereby forming a stack of layers of differing metal with the upper layer being a copper layer. - Referring to drawing FIG. 3C, a portion of the
semiconductor device 10 is shown having awire 20 bonded to the layer ofmetal 12″ of thebond pad 12 using aball type bond 22 thereto for wire bonding using any desired well known wire bonding apparatus. Thesemiconductor substrate 11 includes a layer of insulatingmaterial 13, as described hereinbefore, onactive surface 14 thereof surrounding thebond pad 12. - Referring to drawing FIGS. 4A through 4D, in drawing FIG. 4A, a portion of a
semiconductor device 10 is shown having abond pad 12 thereon with thecopper layer 12′ located thereon having the upper surface thereof located at approximately the same level as theactive surface 14 to thedevice 10, thesurface 14 having a layer of insulation (typically a passivation layer of an insulating oxide or insulating nitride) 13 thereon. Also illustrated in drawing FIG. 4A, thecopper layer 12′ ofbond pad 12 has asuitable metal layer 12″ selectively plated thereon using well known plating processes. The function of themetal layer 12″ being to provide a good metal to which an effective wire bond may be formed using well known wire bonding apparatus. - Illustrated in drawing FIG. 4B, the
copper layer 12′ ofbond pad 12 has asuitable barrier layer 12′″ located between thecopper layer 12′ and thesuitable metal layer 12″, such as described hereinbefore. - Referring to drawing FIG. 4C, a portion of a
semiconductor device 10 is shown having abond pad 12 thereon having acopper layer 12′ located thereon having a portion bonded thereto of a conductor lead 22 (numeral 22 previously referred to as “ball 22”) located on a portion of asubstrate 24 of a portion of aTAB tape 21. Thesurface 14 ofsubstrate 11 of thesemiconductor device 10 has a layer of insulation (typically a passivation layer of an insulating oxide or insulating nitride) 13 thereon. Also illustrated in drawing FIG. 4C, the function of themetal layer 12″ is to provide a good metal to which an effective bond may be formed using well known bonding apparatus to theconductive lead 22 of theTAB tape 20. Theconductive lead 22 of the TAB tape may be of any suitable metal, such as copper, copper alloys, etc. Themetal layer 12″ may be of any suitable metal, such as described herein. - Referring to drawing FIG. 4D, a portion of a
semiconductor device 10 is shown having abond pad 12 thereon having acopper layer 12′ located thereon having abarrier layer 12′″ located thereon having, in turn, ametal layer 12″ located thereon. Themetal layer 12″ of thebond pad 12 is bonded to a portion of aconductor lead 22 located on a portion of asubstrate 24 of a portion of aTAB tape 20. Theconductor lead 22 of the portion of theTAB tape 21 including alayer 26 of suitable metal located thereon for the bonding of theconductor lead 22 to themetal layer 12″ of thebond pad 12 of thesemiconductor device 10. Thesurface 14 ofsubstrate 11 of thesemiconductor device 10 has a layer of insulation (typically a passivation layer of an insulating oxide or insulating nitride) 13 thereon. Also illustrated in drawing FIG. 4D, the function of themetal layer 12″ is to provide a good metal to which an effective bond may be formed using well known bonding apparatus to themetal layer 26 of theconductive lead 22 of theTAB tape 20. Thesubstrate 24 andmetal layer 26 may be of any suitable metal for bonding purposes, such as gold, alloys of gold, etc. Theconductive lead 22 of the TAB tape may be of any suitable metal, such as copper, copper alloys, etc. Themetal layer 12″ may be of any suitable metal, such as described herein. Thebarrier layer 12′″ may be of any suitable metal or material, such as described herein. - Referring to drawing FIGS. 5A through 5J, various differing processes for the formation of the
bond pad 12 including acopper layer 12′ and a layer ofmetal 12″ and, if desired, abarrier layer 12′″ are illustrated. - Referring to drawing FIG. 5A, a
process 100 for the formation of abond pad 12 including acopper layer 12′ and a layer ofmetal 12″ thereon for wire bonding purposes as described hereinbefore is illustrated. As illustrated instep 102, asubstrate 11 as described hereinbefore for asemiconductor device 10 has a layer of copper orcopper alloy 12′ deposited thereon using any desired deposition process. Subsequently, instep 104, a layer ofmetal 12″ is deposited on thecopper layer 12′ using any well known deposition process for deposition. Then, instep 106, thecopper layer 12′ and layer ofmetal 12′ is patterned and etched to form the desired shape, number, and pattern for thebond pads 12 on theactive surface 14 of thesubstrate 11 of thesemiconductor device 10. A layer ofinsulation 13 is typically applied to theactive surface 14 of thesubstrate 11 to protect the circuitry formed thereon of thesemiconductor device 10. After the completion of thesemiconductor device 10 havingbond pads 12 including acopper layer 12′ and. layer ofmetal 12″ thereon, the semiconductor device may be assembled to a lead frame (not shown) for wire bonding awire 20 to thebond pad 12 of thesemiconductor device 10 using any suitablewire bonding process 108 and apparatus. - Referring to drawing FIG. 5B, a
process 200 for the formation of abond pad 12 including acopper layer 12′ and a layer ofmetal 12″ thereon for wire bonding purposes as described hereinbefore is illustrated. As illustrated instep 202, asubstrate 11 as described hereinbefore for asemiconductor device 10 has a layer of copper orcopper alloy 12′ deposited thereon using any desired deposition process. Subsequently, instep 204, thecopper layer 12′ is patterned and etched to form the desired shape, number, and pattern for thebond pads 12 on theactive surface 14 of thesubstrate 11 of thesemiconductor device 10. Then, instep 206, the layer ofmetal 12″ is deposited on thecopper layer 12′ using any desired deposition process, as described hereinbefore, such as electrodepositon, electroless deposition, etc. to form thebond pad 12 having acopper layer 12′ and layer ofmetal 12″ thereon for good wire bonding properties. A layer ofinsulation 13 is typically applied to theactive surface 14 of thesubstrate 11 to protect the circuitry formed thereon of thesemiconductor device 10. After the completion of thesemiconductor device 10 havingbond pads 12 including acopper layer 12′ and layer ofmetal 12″ thereon, the semiconductor device may be assembled to a lead frame (not shown) for wire bonding awire 20 to thebond pad 12 of thesemiconductor device 10 using any suitablewire bonding process 208 and apparatus. - Referring to drawing FIG. 5C, a
process 300 for the formation of abond pad 12 including acopper layer 12′, abarrier layer 12′″, and a layer ofmetal 12″ thereon for wire bonding purposes as described hereinbefore is illustrated. As illustrated instep 302, asubstrate 11 as described hereinbefore for asemiconductor device 10 has a layer of copper orcopper alloy 12′ deposited thereon using any desired deposition process. Subsequently, instep 304, abarrier layer 12′″ of suitable material is deposited on thecopper layer 12′ using any well known deposition process for deposition. Then, instep 306, thecopper layer 12′ andbarrier layer 12′″ are patterned and etched to form the desired shape, number, and pattern for thebond pads 12 on theactive surface 14 of thesubstrate 11 of thesemiconductor device 10. Then ametal layer 12″ is deposited instep 308 over thebarrier layer 12′″ and subsequently patterned instep 310. A layer ofinsulation 13 is typically applied to theactive surface 14 of thesubstrate 11 to protect the circuitry formed thereon of thesemiconductor device 10. After the completion of thesemiconductor device 10 havingbond pads 12 including acopper layer 12′,barrier layer 12′″, and layer ofmetal 12″ thereon, the semiconductor device may be assembled to a lead frame (not shown) for wire bonding awire 20 to thebond pad 12 of thesemiconductor device 10 using any suitablewire bonding process 312 and apparatus. - Referring to drawing FIG. 5D, a
process 400 for the formation of abond pad 12 including acopper layer 12′, abarrier layer 12′″, and a layer ofmetal 12″ thereon for wire bonding purposes as described hereinbefore is illustrated. As illustrated instep 402, asubstrate 11 as described hereinbefore for asemiconductor device 10 has a layer of copper orcopper alloy 12′ deposited thereon using any desired deposition process. Subsequently, instep 404, abarrier layer 12′″ of suitable material is deposited on thecopper layer 12′ using any well known deposition process for deposition. Then, instep 406, ametal layer 12″ is deposited on thebarrier layer 12′″. Instep 408, thecopper layer 12′,barrier layer 12′″, andmetal layer 12″ are patterned and etched to form the desired shape, number, and pattern for thebond pads 12 on theactive surface 14 of thesubstrate 11 of thesemiconductor device 10. A layer ofinsulation 13 is typically applied to theactive surface 14 of thesubstrate 11 to protect the circuitry formed thereon of thesemiconductor device 10. After the completion of thesemiconductor device 10 havingbond pads 12 including acopper layer 12′,barrier layer 12′″, and layer ofmetal 12″ thereon, the semiconductor device may be assembled to a lead frame (not shown) for wire bonding awire 20 to thebond pad 12 of thesemiconductor device 10 using any suitablewire bonding process 410 and apparatus. - Referring to drawing FIG. 5E, a
process 500 for the formation of abond pad 12 including acopper layer 12′ and a layer ofmetal 12″ thereon for wire bonding purposes as described hereinbefore is illustrated. As illustrated instep 502, asubstrate 11 as described hereinbefore for asemiconductor device 10 has a layer of copper orcopper alloy 12′ deposited thereon using any desired deposition process. Subsequently, instep 504, at least twobarrier layers 12′″ are deposited on the copper layer. Instep 506, ametal layer 12″ is deposited on thebarrier layer 12′″ using any desired deposition process, as described hereinbefore, such as electrodeposition, electroless deposition, etc. Instep 508, thecopper layer 12′,barrier layer 12′″, andmetal layer 12″ are patterned to form thebond pad 12 having acopper layer 12′,barrier layer 12′″, and layer ofmetal 12″ thereon for good wire bonding properties. A layer ofinsulation 13 is typically applied to theactive surface 14 of thesubstrate 11 to protect the circuitry formed thereon of thesemiconductor device 10. After the completion of thesemiconductor device 10 havingbond pads 12 including acopper layer 12′, at least twobarrier layers 12′″, and layer ofmetal 12″ thereon, the semiconductor device may be assembled to a lead frame (not shown) for wire bonding awire 20 to thebond pad 12 of thesemiconductor device 10 using any suitablewire bonding process 510 and apparatus. - Referring to drawing FIGS. 5F through 5J, the processes set forth therein are similar to those described regarding those illustrated in drawing FIGS. 5A through 5E, except that a conductor lead of a TAB tape is bonded to the
bond pad 12 of thesemiconductor device 10, rather than a wire bond being made to thebond pad 12 of asemiconductor device 10. - Referring to drawing FIG. 5F, a
process 600 for the formation of abond pad 12 including acopper layer 12′ and a layer ofmetal 12″ thereon for conductor lead of TAB tape bonding purposes as described hereinbefore is illustrated. As illustrated instep 602, asubstrate 11 as described hereinbefore for asemiconductor device 10 has a layer of copper orcopper alloy 12′ deposited thereon using any desired deposition process. Subsequently, instep 604, a layer ofmetal 12″ is deposited on thecopper layer 12′ using any well known deposition process for deposition. Then, instep 606, thecopper layer 12′ and layer ofmetal 12″ is patterned and etched to form the desired shape, number, and pattern for thebond pads 12 on theactive surface 14 of thesubstrate 11 of thesemiconductor device 10. A layer ofinsulation 13 is typically applied to theactive surface 14 of thesubstrate 11 to protect the circuitry formed thereon of thesemiconductor device 10. After the completion of thesemiconductor device 10 havingbond pads 12 including acopper layer 12′ and layer ofmetal 12″ thereon, the semiconductor device may be assembled to a conductor lead of a TAB tape (not shown) for bonding a conductor lead to thebond pad 12 of thesemiconductor device 10 using anysuitable bonding process 608 and apparatus. - Referring to drawing FIG. 5G, a
process 700 for the formation of abond pad 12 including acopper layer 12′ and a layer ofmetal 12″ thereon for conductor lead of TAB tape bonding purposes as described hereinbefore is illustrated. As illustrated instep 702, asubstrate 11 as described hereinbefore for asemiconductor device 10 has a layer of copper orcopper alloy 12′ deposited thereon using any desired deposition process. Subsequently, instep 704, thecopper layer 12′ is patterned and etched to form the desired shape, number, and pattern for thebond pads 12 on theactive surface 14 of thesubstrate 11 of thesemiconductor device 10. Then, instep 706, the layer ofmetal 12″ is deposited on thecopper layer 12′ using any desired deposition process, as described hereinbefore, such as electrodepositon, electroless deposition, etc. to form thebond pad 12 having acopper layer 12′ and layer ofmetal 12″ thereon for good wire bonding properties. A layer ofinsulation 13 is typically applied to theactive surface 14 of thesubstrate 11 to protect the circuitry formed thereon of thesemiconductor device 10. After the completion of thesemiconductor device 10 havingbond pads 12 including acopper layer 12′ and layer ofmetal 12″ thereon, the semiconductor device may be assembled to a conductor lead of a TAB tape (not shown) for wire bonding a conductor lead to thebond pad 12 of thesemiconductor device 10 using anysuitable bonding process 708 and apparatus. - Referring to drawing FIG. 5H, a
process 800 for the formation of abond pad 12 including acopper layer 12′, abarrier layer 12′″, and a layer ofmetal 12″ thereon for conductor lead of TAB tape bonding purposes as described hereinbefore is illustrated. As illustrated instep 802, asubstrate 11 as described hereinbefore for asemiconductor device 10 has a layer of copper orcopper alloy 12′ deposited thereon using any desired deposition process. Subsequently, instep 804, abarrier layer 12′″ of suitable material is deposited on thecopper layer 12′ using any well known deposition process for deposition. Then, instep 806, thecopper layer 12′ andbarrier layer 12′″ are patterned and etched to form the desired shape, number, and pattern for thebond pads 12 on theactive surface 14 of thesubstrate 11 of thesemiconductor device 10. Then ametal layer 12″ is deposited instep 808 over thebarrier layer 12′″ and subsequently patterned instep 810. A layer ofinsulation 13 is typically applied to theactive surface 14 of thesubstrate 11 to protect the circuitry formed thereon of thesemiconductor device 10. After the completion of thesemiconductor device 10 havingbond pads 12 including acopper layer 12′,barrier layer 12′″, and layer ofmetal 12″ thereon, the semiconductor device may be assembled to a conductor lead of a TAB tape (not shown) for bonding a conductor lead to thebond pad 12 of thesemiconductor device 10 using anysuitable bonding process 812 and apparatus. - Referring to drawing FIG. 5I, a
process 900 for the formation of abond pad 12 including acopper layer 12′, abarrier layer 12′″, and a layer ofmetal 12″ thereon for conductor lead of TAB tape bonding purposes as described hereinbefore is illustrated. As illustrated instep 902, asubstrate 11 as described hereinbefore for asemiconductor device 10 has a layer of copper orcopper alloy 12′ deposited thereon using any desired deposition process. Subsequently, instep 904, abarrier layer 12′″ of suitable material is deposited on the copper.layer 12′ using any well known deposition process for deposition. Then, instep 906, ametal layer 12″ is deposited on thebarrier layer 12′″. Instep 908, thecopper layer 12′,barrier layer 12′″, andmetal layer 12″ are patterned and etched to form the desired shape, number, and pattern for thebond pads 12 on theactive surface 14 of thesubstrate 11 of thesemiconductor device 10. A layer ofinsulation 13 is typically applied to theactive surface 14 of thesubstrate 11 to protect the circuitry formed thereon of thesemiconductor device 10. After the completion of thesemiconductor device 10 havingbond pads 12 including acopper layer 12′,barrier layer 12′″, and layer ofmetal 12″ thereon, the semiconductor device may be assembled to a conductor lead of a TAB tape (not shown) for bonding a conductor lead to thebond pad 12 of thesemiconductor device 10 using anysuitable bonding process 910 and apparatus. - Referring to drawing FIG. 5J, a
process 1000 for the formation of abond pad 12 including acopper layer 12′ and a layer ofmetal 12″ thereon for conductor lead of TAB tape bonding purposes as described hereinbefore is illustrated. As illustrated instep 1002, asubstrate 11 as described hereinbefore for asemiconductor device 10 has a layer of copper orcopper alloy 12′ deposited thereon using any desired deposition process. Subsequently, instep 1004, at least twobarrier layers 12′″ are deposited on the copper layer. Instep 1006, ametal layer 12″ is deposited on thebarrier layer 12′″ using any desired deposition process, as described hereinbefore, such as electrodeposition, electroless deposition, etc. Instep 1008, thecopper layer 12′,barrier layer 12′″, andmetal layer 12″ are patterned to form thebond pad 12 having acopper layer 12′, barrier layers 12′″, and layer ofmetal 12″ thereon for good wire bonding properties. A layer ofinsulation 13 is typically applied to theactive surface 14 of thesubstrate 11 to protect the circuitry formed thereon of thesemiconductor device 10. After the completion of thesemiconductor device 10 havingbond pads 12 including acopper layer 12′,barrier layer 12′, and layer ofmetal 12″ thereon, the semiconductor device may be assembled to a conductor lead of a TAB tape (not shown) for wire bonding a conductor lead to thebond pad 12 of thesemiconductor device 10 using anysuitable bonding process 1010 and apparatus. - It will be understood that changes, additions, deletions, and modifications may be made to be present invention which are intended to be within the scope of the claimed invention. Such are the use of a more than a single layer of metal over the copper layer to form a bond pad, the copper layer being a multi-layer of differing materials, the barrier layer being multiple layers of differing materials, the metal layer being multi-layers of differing materials, etc.
Claims (33)
1. A semiconductor device assembly comprising:
a semiconductor device having an active surface with at least one bond pad located thereon, the bond pad including:
a copper layer; and
at least one layer of metal covering a portion of the copper layer; and
one end of a wire connected to the at least one layer of metal covering a portion of the copper layer of the bond pad.
2. The semiconductor device assembly of claim 1 , wherein the bond pad includes at least two layers of metal, one layer comprising the at least one layer of metal covering a portion of the copper layer of the bond pad and at least one other layer of metal covering a portion of the at least one layer of metal.
3. The semiconductor device of claim 1 , wherein the at least one layer of metal comprises one of silver metal, gold metal, a silver alloy metal, a gold alloy metal, a silver and gold alloy metal, a palladium metal, a noble metal, a noble metal alloy, a nickel metal, and a nickel metal alloy.
4. The semiconductor device of claim 2 , wherein the at least one layer of metal comprises a silver metal alloy and wherein the at least one other layer of metal comprises a nickel metal alloy.
5. The semiconductor device of claim 2 , wherein the at least one layer of metal comprises a nickel metal alloy and wherein the at least one other layer of metal comprises a silver metal alloy.
6. The semiconductor device of claim 2 , wherein the at least one layer of metal comprises silver metal and wherein the at least one other layer of metal comprises nickel metal.
7. The semiconductor device of claim 2 , wherein the at least one layer of metal comprises nickel metal and wherein the at least one other layer of metal comprises a silver metal.
8. The semiconductor device of claim 1 , wherein the copper layer comprises a zincated copper layer.
9. The semiconductor device of claim 2 , wherein the at least one layer of metal comprises a barrier layer of metal and the at least one other layer of metal comprises an adhesion promoting layer of metal for wire bonding thereto.
10. The semiconductor device of claim 1 , further comprising:
an insulative coating on a portion of the active surface of the semiconductor device.
11. A semiconductor device assembly comprising:
a semiconductor device having an active surface with at least one bond pad located thereon, the bond pad including:
a copper layer;
a barrier layer over at least a portion of the copper layer; and
at least one layer of metal covering a portion of the copper layer and the barrier layer; and
one end of a wire connected to the at least one layer of metal covering a portion of the copper layer of the bond pad.
12. The semiconductor device assembly of claim 11 , wherein the bond pad includes at least two layers of metal, one layer comprising the at least one layer of metal covering a portion of the copper layer of the bond pad and at least one other layer of metal covering a portion of the at least one layer of metal.
13. The semiconductor device of claim 11 , wherein the at least one layer of metal comprises one of silver metal, gold metal, a silver alloy metal, a gold alloy metal, a silver and gold alloy metal, a palladium metal, a noble metal, a noble metal alloy, a nickel metal, and
a nickel metal alloy.
14. The semiconductor device of claim 20 , wherein the barrier layer comprises one of TaN, TiN, TiW, WN, nickel, nickel alloys, tantalum alloys, and titanium alloys.
15. The semiconductor device of claim 11 , wherein the at least one layer of metal comprises a silver metal alloy and wherein the at least one other layer of metal comprises a nickel metal alloy.
16. The semiconductor device of claim 11 , wherein the at least one layer of metal comprises a nickel metal alloy and wherein the at least one other layer of metal comprises a silver metal alloy.
17. The semiconductor device of claim 11 , wherein the at least one layer of metal comprises silver metal and wherein the at least one other layer of metal comprises nickel metal.
18. The semiconductor device of claim 11 , wherein the at least one layer of metal comprises nickel metal and wherein the at least one other layer of metal comprises a silver metal.
19. The semiconductor device of claim 11 , wherein the copper layer comprises a zincated copper layer.
20. The semiconductor device of claim 11 , wherein the at least one layer of metal comprises a barrier layer of metal and the at least one other layer of metal comprises an adhesion promoting layer of metal for wire bonding thereto.
21. The semiconductor device of claim 11 , further comprising:
an insulative coating on a portion of the active surface of the semiconductor device.
22. A semiconductor device assembly comprising:
a semiconductor device having an active surface with at least one bond pad located thereon, the bond pad including:
a copper layer; and
at least one layer of gold metal covering a portion of the copper layer; and
one end of a gold wire connected to the at least one layer of gold metal covering a portion of the copper layer of the bond pad.
23. The semiconductor device assembly of claim 22 , wherein the bond pad includes at least two layers of metal, one layer comprising the at least one layer of gold metal covering a portion of the copper layer of the bond pad and at least one other layer of metal covering a portion of the at least one layer of metal.
24. A semiconductor device assembly comprising:
a semiconductor device having an active surface with at least one bond pad located thereon, the bond pad including:
a copper layer; and
at least one layer of gold metal covering a portion of the copper layer; and
one end of a gold wire connected to the copper layer having at least one layer of gold metal over a portion thereof of the bond pad.
25. The semiconductor device assembly of claim 24 , wherein the bond pad includes at least two layers of metal, one layer comprising the at least one layer of gold metal covering a portion of the copper layer of the bond pad and at least one other layer of metal covering a portion of the at least one layer of gold metal.
26. A semiconductor device assembly comprising:
a semiconductor device having an active surface with at least one bond pad located thereon, the bond pad including:
a copper layer;
a barrier layer over at least a portion of the copper layer; and
at least one layer of gold metal covering a portion of the copper layer and the barrier layer; and
one end of a gold wire connected to the barrier layer of the bond pad having at least one layer of
27. The semiconductor device assembly of claim 26 , wherein the bond pad includes at least two layers of metal, one layer comprising the at least layer of metal covering a portion of the barrier layer of the bond pad and at least one other layer of metal covering a portion of the at least one layer of metal.
28. A method of forming a semiconductor device assembly, said method comprising:
providing a substrate having an upper surface and a lower surface;
depositing a layer of copper on one surface of the upper surface and the lower surface of the substrate;
patterning the layer of copper on one surface of the upper surface and the lower surface of the substrate to form at least one bond pad thereon;
depositing at least one layer of metal on at least a portion of the layer of copper; and
connecting one end of a conductor lead of a TAB tape to the at least one layer of metal.
29. The method of claim 28 , further comprising:
connecting one end of conductor lead of a TAB tape to the at least one layer of gold metal using a wire bond.
30. A method of forming a semiconductor device assembly, said method comprising:
providing a substrate having an upper surface and a lower surface;
depositing a layer of copper on one surface of the upper surface and the lower surface of the substrate;
patterning the layer of copper on one surface of the upper surface and the lower surface of the substrate to form at least one bond pad thereon;
depositing at least one layer of gold metal on at least a portion of the layer of copper; and
connecting one end of a conductor lead of a TAB tape to the at least one layer of gold metal.
31. A semiconductor device assembly comprising:
a semiconductor device having an active surface with at least one bond pad located thereon, the bond pad including:
a copper layer;
a barrier layer; and
at least one layer of metal covering a portion of the copper layer; and
one end of a wire connected to the at least one layer of metal covering a portion of the copper layer of the bond pad.
32. The semiconductor device assembly of claim 31 , wherein the bond pad includes at least two layers of metal and the barrier layer includes at least two layers of material.
33. The semiconductor device of claim 31 , wherein the one layer of metal includes at least two layers of material.
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US11/266,836 Expired - Fee Related US7345358B2 (en) | 1999-06-14 | 2005-11-04 | Copper interconnect for semiconductor device |
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Also Published As
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US7511363B2 (en) | 2009-03-31 |
US20040171246A1 (en) | 2004-09-02 |
US7592246B2 (en) | 2009-09-22 |
US7489041B2 (en) | 2009-02-10 |
US20060055060A1 (en) | 2006-03-16 |
US20090309222A1 (en) | 2009-12-17 |
US7569934B2 (en) | 2009-08-04 |
US20050098888A1 (en) | 2005-05-12 |
US20050212128A1 (en) | 2005-09-29 |
US6544880B1 (en) | 2003-04-08 |
US7345358B2 (en) | 2008-03-18 |
US20060138660A1 (en) | 2006-06-29 |
US20060055058A1 (en) | 2006-03-16 |
US20060055059A1 (en) | 2006-03-16 |
US20060071336A1 (en) | 2006-04-06 |
US20050218483A1 (en) | 2005-10-06 |
US20060055057A1 (en) | 2006-03-16 |
US8759970B2 (en) | 2014-06-24 |
US7338889B2 (en) | 2008-03-04 |
US20030143830A1 (en) | 2003-07-31 |
US6835643B2 (en) | 2004-12-28 |
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Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |