US20030129834A1 - Semiconductor wafer with crystal lattice defects, and process for producing this semiconductor wafer - Google Patents
Semiconductor wafer with crystal lattice defects, and process for producing this semiconductor wafer Download PDFInfo
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- US20030129834A1 US20030129834A1 US09/575,012 US57501200A US2003129834A1 US 20030129834 A1 US20030129834 A1 US 20030129834A1 US 57501200 A US57501200 A US 57501200A US 2003129834 A1 US2003129834 A1 US 2003129834A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/21—Circular sheet or circular blank
Abstract
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor wafer with an uneven distribution of crystal lattice defects, and to a process for producing this wafer.
- 2. The Prior Art
- Silicon crystals, in particular for the production of semiconductor wafers, are preferably obtained by pulling a seed crystal from a silicon melt, which is generally provided inside a quartz glass crucible. This so-called Czochralski crucible-pulling process is described in detail in, for example, W. Zulehner and D. Huber,Czochralski-Grown Silicon, Crystals 8, Springer Verlag Berlin-Heidelberg 1982.
- Due to the reaction of the quartz glass crucible with the molten silicon during the crucible-pulling process, oxygen is included as the dominant impurity in the growing silicon crystal. The concentration of oxygen is usually so high that, after the crystal has cooled, it is in supersaturated form. In subsequent heat treatments, the oxygen is deposited in the form of oxygen precipitates. These precipitations have both advantages and disadvantages. The so-called gettering properties of the oxygen precipitates are an advantage.
- This is understood to mean that, for example, metallic impurities in the semiconductor wafer are bonded to the oxygen precipitates. Thus, they are removed from the layer which is close to the surface and is relevant for components. A drawback is that oxygen precipitates in the layer which is close to the surface. This is relevant for components and will interfere with the function of the components which are manufactured on the semiconductor wafer. Consequently, it is desired for a precipitate-free zone, PFZ, also known as a denuded zone, DZ, to be formed in the vicinity of the surface. It is also desired for a high concentration of precipitates to be formed in the interior of the semiconductor wafer, known as the bulk.
- The prior art, for example in “Oxygen in Silicon” F. Shimura, Semiconductors and Semimaterials Vol. 42, Academic Press, San Diego, 1994, has disclosed how the outdiffusion of the oxygen near the surface is achieved in a heat treatment at temperatures of preferably over 1100° C. As a result of this outdiffusion, the concentration of oxygen in the layer close to the surface falls so far that there is no longer any precipitation, and consequently a PFZ is generated. This heat treatment was in most cases directly integrated into the processes for producing components. In modern processes, however, these high temperatures are no longer used, and consequently the required outdiffusion is brought about by an additional heat-treatment step.
- The oxygen precipitation, in particular in crucible-pulled semiconductor material, takes place substantially in two steps:
- 1) formation of nucleation centers for oxygen precipitates, so-called nuclei;
- 2) growth of these centers to form detectable oxygen precipitates.
- During subsequent heat treatments, the size of these nuclei can be modified in such a way that those which have a larger radius than the so-called “critical radius” grow into oxygen precipitates. On the other hand, nuclei with a smaller radius break down (are dissolved). The growth of nuclei with a radius >rc takes place at elevated temperature and is substantially limited by the diffusion of oxygen. A generally accepted model (cf., for example, Vanhellemont et al., J. Appl. Phys. 62, p. 3960, 1987) describes the critical radius rc as a function of the temperature, the oxygen supersaturation and the concentration of vacancies. Concentration is understood to mean particles per unit volume.
- A high oxygen concentration and/or a high vacancy supersaturation simplifies or accelerates the precipitation of oxygen and leads to a higher concentration of precipitates. Furthermore, the concentration or size of the precipitates, in particular in semiconductor wafers, depends on heating and cooling rates during thermal furnace processes, in particular during the so-called RTA (rapid thermal annealing) processes. During these heat treatments, semiconductor wafers are heated to temperatures of up to 1300° C. within a few seconds and are then cooled at rates of up to 300° C./sec.
- The oxygen concentration, the vacancy concentration, the interstitial concentration, the dopant concentration and the concentration of existing precipitation nuclei, such as for example carbon atoms, also influence the precipitation of oxygen.
- WO 98/38675 has disclosed a semiconductor wafer with an uneven distribution of crystal lattice vacancies, which is obtained by means of a heat treatment. The maximum level of this vacancy profile generated in this way is situated in the bulk of the semiconductor wafer, and the profile decreases considerably toward the surfaces. During subsequent heat-treatment processes, in particular at 800° C. for 3 h and 1000° C. for 16 h, the oxygen precipitation follows this profile. The result is a PFZ without prior outdiffusion of the oxygen and oxygen precipitates in the bulk of the semiconductor wafer.
- According to WO 98/38675, the concentration of oxygen precipitates is set by means of the concentration of vacancies, and the depth of the precipitates is set by means of the cooling rate following the heat treatment. A drawback of this semiconductor wafer is that the getter centers are limited to the bulk. Furthermore, very high BMD (bulk micro defect) concentrations lead to high leakage currents from integrated circuits when these circuits are located close to the layer relevant for the components. These leakage currents can be minimized if regions with very high BMD concentrations are produced as far away from the components as possible. Furthermore, it has been found that, in particular for applications in micromechanics, high BMD concentrations in the middle of the semiconductor wafer have an adverse effect on the selective etching behavior. This is because a high variation in etching removal rates is observed in the presence of the precipitates. Consequently, it is desired to limit the oxygen precipitates as far as possible to defined layers. It is also desired to keep the back-side part of the semiconductor wafer precipitate-free, for example for the production of micromechanical structures.
- It is therefore an object of the present invention to provide a semiconductor wafer, and a process for producing the wafer, which serves as a basis for a semiconductor wafer with an improved internal gettering action.
- This above object is achieved according to the invention by means of a semiconductor wafer having a
front side 1, aback side 2, atop layer 3, abottom layer 4, an upperinner layer 5 lying below thetop layer 3, a lowerinner layer 6 lying above thebottom layer 4, acentral region 7 between thelayers central region 7 and a second maximum (max2) in thebottom layer 4. - The defects are preferably vacancies which are converted into nucleation centers for oxygen precipitates during subsequent heat treatment processes, preferably at temperatures of from 300° C. to 800° C. According to the invention, the nucleation centers follow the profile of the vacancies. Preferably, the concentration of the defects increases from the
front side 1 of the semiconductor wafer toward thecentral region 7, up to the first maximum (max1), and toward thebottom layer 4, up to the second maximum (max2). - Accordingly, the above object is also achieved by means of a semiconductor wafer with an uneven distribution of nucleation centers for oxygen precipitates.
- In particular, the object is also achieved by means of a semiconductor wafer having a
front side 1, aback side 2, atop layer 3, abottom layer 4, an upperinner layer 5 lying below thetop layer 3, a lowerinner layer 6 lying above thebottom layer 4, acentral region 7 between thelayers central region 7 and a second maximum (max2) in thebottom layer 4, and the concentration of the nucleation centers on thefront side 1 and in thetop layer 3 is so low that, in a subsequent heat treatment without outdiffusion of oxygen, a precipitate-free layer with a thickness of from 1 to 100 μm is formed on thefront side 1. - Surprisingly, it has been found that the nucleation centers are not mobile point defects, but rather immobile deposits. According to the invention, therefore, the oxygen precipitation exactly follows this profile during subsequent heat treatments, for example during a heat treatment for 3 h at 780° C. and for 16 h at 1000° C.
- Due to the variation in concentration of the nucleation centers at increasing distance from the surface of the semiconductor wafer, the subsequent heat treatment processes thus result in a depth-dependent variation in the concentration of the oxygen precipitates.
- Accordingly, a semiconductor wafer whose concentration of nucleation centers is very low on the
front side 1 and in thetop layer 3, increases toward the central region, to a first maximum (max1), and then rises again toward theback side 2, in order to reach a second maximum (max2) in thebottom layer 4, is preferred. - However, the object is also achieved by means of a semiconductor wafer having a
front side 1, aback side 2, atop layer 3, abottom layer 4, an upperinner layer 5 lying below thetop layer 3, a lowerinner layer 6 lying above thebottom layer 4, acentral region 7 between thelayers inner layer 5. - The defects are preferably vacancies which are converted into nucleation centers for oxygen precipitates during subsequent heat treatment processes, preferably at temperatures of from 300° C. to 800° C. According to the invention, the nucleation centers follow the profile of the vacancies.
- Accordingly, the object is also achieved by means of a semiconductor wafer with an uneven distribution of nucleation centers for oxygen precipitates.
- In particular, the object is also achieved by means of a semiconductor wafer having a
front side 1, aback side 2, atop layer 3, abottom layer 4, an upperinner layer 5 lying below thetop layer 3, a lowerinner layer 6 lying above thebottom layer 4, acentral region 7 between thelayers inner layer 5. The concentration of the nucleation centers on thefront side 1, theback side 2, in thetop layer 3, thebottom layer 4 and the lowerinner layer 6 is so low that, in a subsequent heat treatment without outdiffusion of oxygen, precipitate-free layers with a thickness of from 1 to 100 μm are formed on thefront side 1 and theback side 2. - According to the invention, therefore, the oxygen precipitation exactly follows this profile during subsequent heat treatments, for example during a heat treatment for 3 h at 780° C. and for 16 h at 1000° C.
- The oxygen precipitates in particular in the upper
inner layer 5 have proven advantageous, since the back-side region of precipitates remains clear and therefore offers ideal conditions for, for example, applications in micromechanics. Nevertheless, the precipitates formed in thelayer 5 and in thecentral region 7 produce a good gettering action. - Other objects and features of the present invention will become apparent from the following detailed description considered in connection with the accompanying drawings which disclose embodiments of the present invention. It should be understood, however, that the drawings are designed for the purpose of illustration only and not as a definition of the limits of the invention.
- In the drawings, wherein similar reference characters denote similar elements throughout the several views:
- FIG. 1 shows one embodiment according to the invention in which the concentration of defects has a first maximum (max1) and a second maximum (max2);
- FIG. 2 shows another embodiment according to the invention in which the concentration of defects has a maximum in the upper inner layer; and
- FIG. 3 shows a cross sectional view of a semiconductor wafer of the invention.
- According to the invention, the basis for a semiconductor wafer with improved internal gettering action is provided, in a semiconductor wafer, by a vacancy profile which has two maximums (illustrated by way of example in FIG. 1) or one maximum which is located between the
front side 1 and thecentral region 7 of the semiconductor wafer (illustrated by way of example in FIG. 2). The nucleation centers exactly follow these profiles during subsequent heat treatment processes. - FIG. 3 shows the layers defined above as well as the
front side 1, theback side 2 and thecentral region 7 between thelayers semiconductor wafer 10. Thetop layer 3 is preferably between 0 and 100 μm thick, the upperinner layer 5 is preferably between 15 and 330 μm thick, the lowerinner layer 6 is preferably between 100 and 300 μm thick, and thebottom layer 4 is preferably between 0 and 250 μm thick. - The concentration of the nucleation centers on the front side is preferably less than 104 cm−3, and ideally the concentration approaches zero. At increasing distance from the
front side 1 toward thecentral region 7, the concentration increases, then remains constant in that regions before rising again toward theback side 2, without outdiffusion of oxygen taking place (FIG. 1). The profile shown in FIG. 2 is likewise converted into a corresponding profile of nucleation centers. - The figures indicate, by way of example, BMD concentrations without units. BMDs are to be understood as meaning, in general terms, crystal defects, such as for example vacancies or nucleation centers.
- According to the invention, a precipitate-free layer with a thickness of preferably from 1 to 100 μm is obtained on that side of the semiconductor wafer which is active for the components, without complex oxygen outdiffusion steps having to be carried out.
- Preferably, oxygen precipitates are formed in the upper
inner layer 5, in the lowerinner layer 6 and in thebottom layer 4 during the component production, ensuring an improved internal gettering action. - Furthermore, this special nucleation-center profile shown in FIG. 1 brings about improved gettering properties on the back side of the semiconductor wafer, since that is where the highest concentration of precipitates is to be found.
- Preferably, oxygen precipitates form only in the upper
inner layer 5 lying below thetop layer 3. This ensures that the region with the highest precipitate concentration is situated furthest away from the layer which is relevant for components, so that the leakage current problem is minimized. This also allows any secondary defects formed from the oxygen precipitates, such as for example dislocations, to reach thefront side 1, which is relevant for the components. Therefore, on the front side of the semiconductor wafer and in the layer beneath it there are no defects which can have an adverse affect on the integrated circuits. - Accordingly, the object of the invention is also achieved by means of a process for producing a semiconductor wafer with an uneven distribution of crystal lattice defects by means of a heat treatment at a temperature of from 800° C. to 1300° C. The front side of the semiconductor wafer is exposed to a process gas (gas1) and the back side is exposed to a process gas (gas2) during the heat treatment, with the proviso that gas1 is not the same as gas2, but is different from gas2.
- The heat treatment carried out on the semiconductor wafer preferably takes place in a lamp furnace with two reactor chambers. Furnaces of this nature are known, for example, from EP 0,675,524 A1 or EP 0,476,480 B1. Lamp furnaces also ensure rapid heating and cooling of the semiconductor wafer. The profile of the crystal lattice defects is frozen in particular by suitably rapid cooling. To achieve this, the cooling rates following the heat treatment of the semiconductor wafer are preferably between 1 and 300° C./s, particularly preferably between 100° C./s and 250° C./s, and in particular between 75° C./s and 200° C./s in the temperature range from 1300° C. to 800° C.
- The concentration and depth of the defects are controlled by means of the cooling rates, temperature, duration of the heat treatment and the process gases used. For example, if the temperature increases, the concentration of defects rises, while a lowering of the cooling rate increases the PFZ width.
- In the process for producing a semiconductor wafer with an uneven distribution of crystal lattice defects, in which the defect concentration exhibits a first maximum (max1) in the
central region 7 and a second maximum (max2) in thebottom layer 4, thefront side 1 of the semiconductor wafer is exposed to a, preferably inert, process gas (gas1). This gas is preferably selected from a group of gases consisting of nitrogen, hydrogen and the inert gases, as well as any desired mixtures and any desired inert chemical compounds of the abovementioned gases. If appropriate, traces of oxygen may form up to 10% by volume. - The
back side 2 of the semiconductor wafer is exposed to a, preferably nitriding, process gas (gas2), which preferably comprises nitrogen or nitrogen compounds, such as for example ammonia, and, if appropriate, one or more inert carrier gases. - In the process for producing a semiconductor wafer with an uneven distribution of crystal lattice defects, in which the defect concentration exhibits a maximum (max1) in the upper
inner layer 5, thefront side 1 of the semiconductor wafer is exposed to a, preferably inert, process gas (gas1), which is preferably selected from a group of gases consisting of nitrogen, hydrogen and the inert gases, as well as any desired mixtures and any desired inert chemical compounds of the abovementioned gases. If appropriate, traces of oxygen may form up to 10% by volume. - The
back side 2 of the semiconductor wafer is exposed to a, preferably oxidizing, process gas (gas2), which preferably comprises oxygen or oxygen compounds, such as for example water, and, if appropriate, one or more inert carrier gases. - The semiconductor wafer with an uneven distribution of crystal lattice defects is converted into a semiconductor wafer with an uneven distribution of nucleation centers for oxygen precipitates by a subsequent heat treatment at temperatures of preferably 300 to 800° C.
- Accordingly, the object of the invention is also achieved by means of a process for producing a semiconductor wafer with an uneven distribution of nucleation centers for oxygen precipitates, wherein a semiconductor wafer with an uneven distribution of crystal lattice defects is subjected to a heat treatment at a temperature of between 300 and 800° C.
- The duration of the heat treatment is preferably between 1 and 360 min, particularly preferably between 30 and 240 min, and in particular between 60 and 180 min. The heat treatment is preferably carried out in a process gas atmosphere. The process gas is preferably selected from a group of gases consisting of oxygen, nitrogen, hydrogen and the inert gases, as well as any desired mixtures and any desired chemical compounds of the abovementioned gases.
- According to the invention, a profile of nucleation centers for oxygen precipitates which is distinguished by a concentration first maximum (max1) in the
central region 7 and a concentration second first maximum (max2) in thebottom layer 4 is generated in the semiconductor wafer. - According to the invention, a profile of nucleation centers for oxygen precipitates which is distinguished by a concentration maximum (max1) in the upper
inner layer 5 is also generated in the semiconductor wafer. - By means of profiles of this nature, a precipitate-free layer with a thickness of from 1 to 100 μm is generated on the
front side 1 during a subsequent heat treatment process, without outdiffusion of oxygen being required. The concentration of the oxygen precipitates in thelayers - Accordingly, while a few embodiments of the present invention have been shown and described, it is to be understood that many changes and modifications may be made thereunto without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (13)
Applications Claiming Priority (3)
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DE19924649 | 1999-05-28 | ||
DE19924649A DE19924649B4 (en) | 1999-05-28 | 1999-05-28 | Semiconductor wafers with crystal lattice defects and method for producing the same |
DE19924649.1 | 1999-05-28 |
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US6579589B1 US6579589B1 (en) | 2003-06-17 |
US20030129834A1 true US20030129834A1 (en) | 2003-07-10 |
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JP (1) | JP3578396B2 (en) |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040077185A1 (en) * | 2000-10-10 | 2004-04-22 | Koji Dairiki | Semiconductor device manufacturing method, heat treatment apparatus, and heat treatment method |
US20050280122A1 (en) * | 2004-06-16 | 2005-12-22 | Sharp Kabushiki Kaisha | Semiconductor device, and fabrication method of semiconductor device |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6503594B2 (en) * | 1997-02-13 | 2003-01-07 | Samsung Electronics Co., Ltd. | Silicon wafers having controlled distribution of defects and slip |
DE10205084B4 (en) | 2002-02-07 | 2008-10-16 | Siltronic Ag | Process for the thermal treatment of a silicon wafer and silicon wafer produced thereby |
JP2003257984A (en) * | 2002-03-05 | 2003-09-12 | Sumitomo Mitsubishi Silicon Corp | Silicon wafer and its manufacturing method |
EP2259294B1 (en) * | 2006-04-28 | 2017-10-18 | Semiconductor Energy Laboratory Co, Ltd. | Semiconductor device and manufacturing method thereof |
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US5284521A (en) * | 1990-09-21 | 1994-02-08 | Anelva Corporation | Vacuum film forming apparatus |
IT1242014B (en) * | 1990-11-15 | 1994-02-02 | Memc Electronic Materials | PROCEDURE FOR THE TREATMENT OF SILICON SLICES TO OBTAIN IN IT CONTROLLED PRECIPITATION PROFILES FOR THE PRODUCTION OF ELECTRONIC COMPONENTS. |
US5551982A (en) * | 1994-03-31 | 1996-09-03 | Applied Materials, Inc. | Semiconductor wafer process chamber with susceptor back coating |
US5994761A (en) * | 1997-02-26 | 1999-11-30 | Memc Electronic Materials Spa | Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor |
-
1999
- 1999-05-28 DE DE19924649A patent/DE19924649B4/en not_active Expired - Lifetime
-
2000
- 2000-05-19 US US09/575,012 patent/US6579589B1/en not_active Expired - Lifetime
- 2000-05-25 JP JP2000155229A patent/JP3578396B2/en not_active Expired - Lifetime
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040077185A1 (en) * | 2000-10-10 | 2004-04-22 | Koji Dairiki | Semiconductor device manufacturing method, heat treatment apparatus, and heat treatment method |
US7566625B2 (en) * | 2000-10-10 | 2009-07-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device manufacturing method, heat treatment apparatus, and heat treatment method |
US20050280122A1 (en) * | 2004-06-16 | 2005-12-22 | Sharp Kabushiki Kaisha | Semiconductor device, and fabrication method of semiconductor device |
EP1610370A3 (en) * | 2004-06-16 | 2006-06-28 | Sharp Kabushiki Kaisha | Semiconductor device, and fabrication method of semiconductor device |
Also Published As
Publication number | Publication date |
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JP3578396B2 (en) | 2004-10-20 |
DE19924649B4 (en) | 2004-08-05 |
JP2001028372A (en) | 2001-01-30 |
US6579589B1 (en) | 2003-06-17 |
DE19924649A1 (en) | 2000-11-30 |
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