US20030072927A1 - Method for manufacturing solder mask of printed circuit board - Google Patents
Method for manufacturing solder mask of printed circuit board Download PDFInfo
- Publication number
- US20030072927A1 US20030072927A1 US10/155,026 US15502602A US2003072927A1 US 20030072927 A1 US20030072927 A1 US 20030072927A1 US 15502602 A US15502602 A US 15502602A US 2003072927 A1 US2003072927 A1 US 2003072927A1
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- Prior art keywords
- solder mask
- circuit board
- substrate
- printed circuit
- conductor pattern
- Prior art date
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0191—Dielectric layers wherein the thickness of the dielectric plays an important role
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0376—Etching temporary metallic carrier substrate
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0548—Masks
- H05K2203/0554—Metal used as mask for etching vias, e.g. by laser ablation
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
- H05K2203/066—Transfer laminating of insulating material, e.g. resist as a whole layer, not as a pattern
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1152—Replicating the surface structure of a sacrificial layer, e.g. for roughening
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49149—Assembling terminal to base by metal fusion bonding
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
- Y10T29/49151—Assembling terminal to base by deforming or shaping
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
Definitions
- the present invention relates generally to a method for manufacturing a printed circuit board (PCB), and more particularly to a method for manufacturing the solder mask of the printed circuit board.
- PCB printed circuit board
- solder mask protective treatment has to be applied to the conductor pattern so as to prevent oxidation of the conductor pattern or solder connection short circuit.
- solder mask manufacturing process for the conventional printed circuit board, a solder mask paint is applied to the surface of the circuit board by halftone printing, roller type coating, screen coating or electrostatic spray coating, etc. After pre-baking, drying and cooling, exposure is employed to display images. The method of imaging removes unnecessary paint, and the resin in the remaining paint is completely cured by high-temperature baking in the final step to form a solder mask covered on the surface of the PCB to protect the conductor pattern.
- the thickness of the solder mask paint layer is not easy to control, resulting in electric instability of the circuit board.
- Air bubbles can easily get in during the process of coating the solder mask paint to result in poor reliability quality of the solder mask and shortened life of the solder mask layer.
- the primary object of the present invention is to provide a solder mask manufacturing method for a printed circuit board that has good quality and that will not cause bend of the circuit board.
- the present invention is to provide a solder mask manufacturing method adapted to apply a solder mask on a surface of a substrate of a circuit board, said surface is provided with a conductor pattern having an unsheltered portion and a sheltered portion which is covered by said solder mask.
- the method comprises the steps of: disposing a layer of semi-solid solder mask resin material having an expansion coefficient substantially the same as that of the substrate on the surface of said substrate to cover said copper conductor pattern, and a metal foil for covering the resin material layer; applying predetermined pressure to the metal foil and baking at a predetermined temperature for a predetermined time to cure the semi-solid solder mask resin material; utilizing chemical solution etching to remove the metal foil above the unsheltered portion of said copper conductor pattern, and using plasma etching to remove the solid solder mask material above said unsheltered portion of said conductor pattern such that the unsheltered portion of the said conductor pattern can be exposed; and lastly, using chemical solution to remove the residual metal foil.
- FIG. 1 is a flow chart of a preferred embodiment of the present invention.
- FIG. 2 is a schematic view of the preferred embodiment of the present invention.
- the solder mask manufacturing method for a printed circuit board of the present invention adapted to apply a solder mask on a surface of a substrate of the printed circuit board, said surface of the substrate is provided with a cooper conductor pattern having an unsheltered portion and a sheltered portion which is covered by said solder mask.
- the method includes the following steps:
- solder mask resin material disposing a layer of semi-solid solder mask resin material of a predetermined thickness and expansion coefficient identical or similar to that of the circuit board substrate on the surface of the substrate such that the cooper conductor pattern is covered by said resin material, and then a metal foil of a predetermined thickness is disposed to cover the solder mask resin material.
- solder mask resin material applying predetermined pressure to the metal foil such that solder mask resin material between the metal foil and the substrate of the printed circuit board tightly covers the surface of the substrate, and then baking treatment is applied at a predetermined temperature for a predetermined time to cure the semi-solid solder mask resin material.
- a printed circuit board 1 which has undergone the steps of hole drilling and plating, and outer layer cooper conductor pattern circuit layout is subjected to solder mask treatment of the outer layer conductor pattern of the circuit board 1 .
- the material of the substrate 11 of the printed circuit board 1 is multi-function epoxy resin. Therefore, in this embodiment, the printed circuit board 1 has a plurality of through holes 12 and predetermined outer layer copper conductor pattern 13 (see FIG. 2A).
- the cooper conductor pattern 13 can be defined into two portions, namely, the unsheltered portion 13 a and the sheltered portion.
- the solder mask manufacturing process for the printed circuit board 1 is as follows:
- solder mask resin material 3 of a thickness between 30 ⁇ m ⁇ 100 ⁇ m to one side of the aluminum foil 2 .
- the solder mask material is made of multifunction epoxy resin paint identical to that of the substrate 11 of the printed circuit board 1 with organic solution added, and is pre-baked to form a semi-solid state (i.e. thick and sticky). Cover the side of the circuit board 1 that is to be solder mask treated with the solder mask resin material on the aluminum foil 2 so that the solder mask material 3 is sandwiched between the substrate 11 of the circuit board 1 and the aluminum foil 2 (see FIG. 2B).
- solder mask material 3 fills through holes 12 and micro-pores such as blind holes in the substrate 11 of the circuit board 1 due to pressure applied and tightly covers the substrate 11 to form a cover layer.
- plasma etching is used to remove the exposed epoxy resin solder mask layer so that the unsheltered portion 13 a of the cooper conductor pattern is exposed on the substrate 11 (as shown in FIG. 2E).
- the thickness of the solder mask 3 can be set at one time to reduce process step so as to reduce process costs.
- solder mask 3 and substrate 11 of the circuit board 1 are of the same multifunction epoxy resin, the expansion coefficient thereof is the same as that of substrate 11 of the circuit board 1 . Therefore, during the process of baking in step 2 , internal stress will not be present between the solder mask 3 and the substrate 11 so as not to cause bend of the circuit board 1 . Particularly, application of uniform force to the substrate 11 during the process of baking in step 2 will prevent deformation of the circuit board 1 .
- solder mask material 3 As the solder mask material 3 is attached to the substrate 11 , it is subjected to an uniform force via the aluminum foil 2 for a period of time, the solder mask material 3 will cover the circuit board 1 with uniform thickness and forms a solder mask protective layer with uniform thickness after curing so that the circuit board 1 has stable electric characteristics.
- solder mask material 3 As the solder mask material 3 is attached to the substrate 11 , it is subjected to an uniform force via the aluminum foil 2 until cured, air bubbles will not get thereinto during that period of time and can therefore enhance quality of the solder mask protective layer and prolong the life thereof
- solder mask material 3 Due to the pressure applied, the solder mask material 3 can fill through holes and micro-pores such as blind holes in the substrate 11 simultaneously. Therefore, it is not necessary to fill the through holes with insulating filler material and grind the same even prior to solder mask of the circuit board 1 , thereby reducing manufacturing time and costs of the printed circuit board.
- solder mask material 3 As the solder mask material 3 is caused to cover the surface of the substrate 11 by applying pressure and heating, copper conductor pattern 13 on the substrate 11 can easily attach thereto and will not detach therefrom.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Plasma & Fusion (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
A solder mask manufacturing method adapted to apply a solder mask on a surface of a substrate of a circuit board, said surface is provided with a conductor pattern having an unsheltered portion and a sheltered portion which is covered by said solder mask. The method comprises the steps of: a) disposing a layer of semi-solid solder mask material having an expansion coefficient substantially the same as that of the substrate on the surface of said substrate to cover said copper conductor pattern, and a metal foil covering the material layer; b) applying pressure to the metal foil and applying baking treatment to cure the solder mask material in to solid; c) utilizing chemical solution and plasma etching to remove the metal foil and the solid solder mask material above the unsheltered portion of said copper conductor pattern respectively such that the unsheltered portion can be exposed; and d) using chemical solution to remove the residual metal foil.
Description
- The present invention relates generally to a method for manufacturing a printed circuit board (PCB), and more particularly to a method for manufacturing the solder mask of the printed circuit board.
- In the manufacture of a conventional printed circuit board, after forming the outer layer conductor pattern, a solder mask protective treatment has to be applied to the conductor pattern so as to prevent oxidation of the conductor pattern or solder connection short circuit.
- In a solder mask manufacturing process for the conventional printed circuit board, a solder mask paint is applied to the surface of the circuit board by halftone printing, roller type coating, screen coating or electrostatic spray coating, etc. After pre-baking, drying and cooling, exposure is employed to display images. The method of imaging removes unnecessary paint, and the resin in the remaining paint is completely cured by high-temperature baking in the final step to form a solder mask covered on the surface of the PCB to protect the conductor pattern.
- The conventional solder mask manufacturing process has the following disadvantages:
- 1. Using halftone printing or roller type coating to apply the solder mask paint to the printed circuit board requires multiple halftone printing or roller printing steps in order to accumulate the paint to the desired thickness, which is complicated.
- 2. During the process of baking the printing circuit board at high temperature, since the resin material in the solder mask paint has an expansion coefficient different from that of the circuit board substrate, internal stress will form between the resin material and the circuit board to cause the bend of the printed circuit board.
- 3. The thickness of the solder mask paint layer is not easy to control, resulting in electric instability of the circuit board.
- 4. Air bubbles can easily get in during the process of coating the solder mask paint to result in poor reliability quality of the solder mask and shortened life of the solder mask layer.
- 5. Coating the circuit board with solder mask paint cannot fill through holes in the circuit board with solder mask paint. Therefore, before coating, insulating fillers are disposed in the through holes respectively and are ground flat before coating the solder mask paint, thereby increasing manufacturing time and cost of the printing circuit board.
- 6. When coating the circuit board with solder mask paint, coating layer cannot be easily formed on the copper foil conductor pattern, and the bonding therebetween is relatively poor.
- The primary object of the present invention is to provide a solder mask manufacturing method for a printed circuit board that has good quality and that will not cause bend of the circuit board.
- In order to achieve the aforesaid object, the present invention is to provide a solder mask manufacturing method adapted to apply a solder mask on a surface of a substrate of a circuit board, said surface is provided with a conductor pattern having an unsheltered portion and a sheltered portion which is covered by said solder mask. The method comprises the steps of: disposing a layer of semi-solid solder mask resin material having an expansion coefficient substantially the same as that of the substrate on the surface of said substrate to cover said copper conductor pattern, and a metal foil for covering the resin material layer; applying predetermined pressure to the metal foil and baking at a predetermined temperature for a predetermined time to cure the semi-solid solder mask resin material; utilizing chemical solution etching to remove the metal foil above the unsheltered portion of said copper conductor pattern, and using plasma etching to remove the solid solder mask material above said unsheltered portion of said conductor pattern such that the unsheltered portion of the said conductor pattern can be exposed; and lastly, using chemical solution to remove the residual metal foil.
- FIG. 1 is a flow chart of a preferred embodiment of the present invention; and
- FIG. 2 is a schematic view of the preferred embodiment of the present invention.
- Referring to FIG. 1, the solder mask manufacturing method for a printed circuit board of the present invention adapted to apply a solder mask on a surface of a substrate of the printed circuit board, said surface of the substrate is provided with a cooper conductor pattern having an unsheltered portion and a sheltered portion which is covered by said solder mask. The method includes the following steps:
- 1. Coating of solder mask resin material: disposing a layer of semi-solid solder mask resin material of a predetermined thickness and expansion coefficient identical or similar to that of the circuit board substrate on the surface of the substrate such that the cooper conductor pattern is covered by said resin material, and then a metal foil of a predetermined thickness is disposed to cover the solder mask resin material.
- 2. Press bonding and curing of solder mask resin material: applying predetermined pressure to the metal foil such that solder mask resin material between the metal foil and the substrate of the printed circuit board tightly covers the surface of the substrate, and then baking treatment is applied at a predetermined temperature for a predetermined time to cure the semi-solid solder mask resin material.
- 3. Removing unnecessary solder mask material: utilizing chemical solution etching to remove the metal foil above the unsheltered portion of the cooper conductor pattern, and then using plasma etching to remove the solder mask resin material above the unsheltered portion of the cooper conductor pattern such that said unsheltered portion of the copper unsheltered portion can be exposed.
- 4. Removal of metal foil: using chemical solution to remove the residual metal foil covering the solder mask material, thereby completing the manufacturing of the solder mask.
- The aforesaid is the steps of the process of this invention. Hereinafter, the invention is described in detail using a preferred embodiment with reference to FIG. 2.
- Referring to FIG. 2, in the solder mask manufacturing process for a printed circuit board of this invention, a printed
circuit board 1 which has undergone the steps of hole drilling and plating, and outer layer cooper conductor pattern circuit layout is subjected to solder mask treatment of the outer layer conductor pattern of thecircuit board 1. The material of thesubstrate 11 of the printedcircuit board 1 is multi-function epoxy resin. Therefore, in this embodiment, theprinted circuit board 1 has a plurality of throughholes 12 and predetermined outer layer copper conductor pattern 13 (see FIG. 2A). Thecooper conductor pattern 13 can be defined into two portions, namely, theunsheltered portion 13 a and the sheltered portion. The solder mask manufacturing process for the printedcircuit board 1 is as follows: - 1. Coating of Solder Mask Material:
- Firstly, prepare a
aluminum foil 2 with a thickness between 20 μm˜40 μm. Apply soldermask resin material 3 of a thickness between 30 μm˜100 μm to one side of thealuminum foil 2. The solder mask material is made of multifunction epoxy resin paint identical to that of thesubstrate 11 of the printedcircuit board 1 with organic solution added, and is pre-baked to form a semi-solid state (i.e. thick and sticky). Cover the side of thecircuit board 1 that is to be solder mask treated with the solder mask resin material on thealuminum foil 2 so that thesolder mask material 3 is sandwiched between thesubstrate 11 of thecircuit board 1 and the aluminum foil 2 (see FIG. 2B). - 2. Press Bonding and Curing of Solder Mask Material:
- Apply uniform force of 10˜40 kgw/cm2 to the
aluminum foil 2, and bake thesolder mask material 3 at a temperature of 185° C. for 1.5 hours to 3 hours such that: - a) The
solder mask material 3 fills throughholes 12 and micro-pores such as blind holes in thesubstrate 11 of thecircuit board 1 due to pressure applied and tightly covers thesubstrate 11 to form a cover layer. - b) Organic solution in the
solder mask material 3 evaporates when heated, and epoxy resin in thesolder mask material 3 gradually cures to form a solder mask protective layer. - After curing of epoxy resin in the
solder mask material 3 to form a solder mask protective layer, release the pressure and temperature applied. - 3. Removal of Unnecessary Solder Mask Material:
- Press a dry film photo-
resist 4 on thealuminum foil 2 with suitable temperature and pressure (as shown in FIG. 2C), and subject the dry film photo-resist 4 to light exposure in conjunction with a negative film so that the dry film photo-resist 4 generates images relative to positions of the sheltered portion of thecooper conductor pattern 13. Etch the parts of the dry film 4 a without images and the aluminum foil 2 a using carbonic acid and ferric chloride (FeCi3) solution with specific gravity 1.3˜1.5 and temperature of 40° C.˜60° C. so that epoxy resin solder mask layer at where the aluminum foil was removed is exposed on the outside (as shown in FIG. 2D), and then remove the residualdry film 4 using sodium hydroxide of 1˜3 wt % and temperature of 45° C.˜65° C. - Subsequently, plasma etching is used to remove the exposed epoxy resin solder mask layer so that the
unsheltered portion 13 a of the cooper conductor pattern is exposed on the substrate 11 (as shown in FIG. 2E). - 4. Removal of Metal Foil:
- Lastly, use phosphoric acid (H3PO4) solution of 60%˜80% volume to volume and temperature of 50° C.˜80° C., or hydrochloric acid (HCl) with concentration of 10%˜40% and temperature of 20° C.˜40° C. to remove the residual aluminum foil 2 (as shown in FIG. 2F), completing the entire solder mask manufacturing process. The printed
circuit board 1 can subsequently undergo nickel-plating operation of theunsheltered portion 13 a of thecooper conductor pattern 13. Since phosphoric acid or hydrochloric acid can corrode aluminum and will not corrode copper severely, this is the reason why this embodiment selects aluminum foil as cover layer of the solder mask material. - As techniques relating to pressing the dry film, light exposure, imaging and plasma etching are known art, it is not necessary to further describe the same herein.
- Hereinafter, the advantages of the embodiment are set forth as follows:
- 1. The thickness of the
solder mask 3 can be set at one time to reduce process step so as to reduce process costs. - 2. Since the
solder mask 3 andsubstrate 11 of thecircuit board 1 are of the same multifunction epoxy resin, the expansion coefficient thereof is the same as that ofsubstrate 11 of thecircuit board 1. Therefore, during the process of baking instep 2, internal stress will not be present between thesolder mask 3 and thesubstrate 11 so as not to cause bend of thecircuit board 1. Particularly, application of uniform force to thesubstrate 11 during the process of baking instep 2 will prevent deformation of thecircuit board 1. - 3. As the
solder mask material 3 is attached to thesubstrate 11, it is subjected to an uniform force via thealuminum foil 2 for a period of time, thesolder mask material 3 will cover thecircuit board 1 with uniform thickness and forms a solder mask protective layer with uniform thickness after curing so that thecircuit board 1 has stable electric characteristics. - 4. As the
solder mask material 3 is attached to thesubstrate 11, it is subjected to an uniform force via thealuminum foil 2 until cured, air bubbles will not get thereinto during that period of time and can therefore enhance quality of the solder mask protective layer and prolong the life thereof - 5. Due to the pressure applied, the
solder mask material 3 can fill through holes and micro-pores such as blind holes in thesubstrate 11 simultaneously. Therefore, it is not necessary to fill the through holes with insulating filler material and grind the same even prior to solder mask of thecircuit board 1, thereby reducing manufacturing time and costs of the printed circuit board. - 6. As the
solder mask material 3 is caused to cover the surface of thesubstrate 11 by applying pressure and heating,copper conductor pattern 13 on thesubstrate 11 can easily attach thereto and will not detach therefrom. - Although the present invention has been illustrated and described with reference to the preferred embodiment thereof, it should be understood that it is in no way limited to the details of such embodiment but is capable of numerous modifications within the scope of the appended claims.
Claims (4)
1. A printed circuit board comprising:
a substrate having two opposite surfaces, two conductor patterns respectively disposed on the surfaces of said substrate, and at least one plated through hole electrically interconnected with said conductor patterns, each of said conductor patterns having an unsheltered portion and a sheltered portion;
two solder mask layers respectively coated on the surfaces of said substrate and covered over the sheltered portions of said conductor patterns and filling the at least one plated through hole such that the unsheltered portions of said conductor patterns are exposed outside;
wherein each of said solder mask layers has a thermal expansion coefficient substantially identical to that of said substrate;
2. The printed circuit board as defined in claim 1 , wherein said substrate is made of a material containing a resin, and each said solder mask layer is made of a material containing a resin which is substantially identical to the resin of said substrate.
3. The printed circuit board as defined in claim 2 , wherein the resin contained in the substrate is epoxy resin.
4. The printed circuit board as defined in claim 1 further comprising two metal foils respectively covered on said solder mask layers in the way that the unsheltered portions of said conductor patterns are exposed outside.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/155,026 US20030072927A1 (en) | 2001-10-12 | 2002-05-28 | Method for manufacturing solder mask of printed circuit board |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/974,908 US6395625B1 (en) | 2001-10-12 | 2001-10-12 | Method for manufacturing solder mask of printed circuit board |
US10/155,026 US20030072927A1 (en) | 2001-10-12 | 2002-05-28 | Method for manufacturing solder mask of printed circuit board |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US09/974,908 Division US6395625B1 (en) | 2001-10-12 | 2001-10-12 | Method for manufacturing solder mask of printed circuit board |
Publications (1)
Publication Number | Publication Date |
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US20030072927A1 true US20030072927A1 (en) | 2003-04-17 |
Family
ID=25522504
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
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US09/974,908 Expired - Fee Related US6395625B1 (en) | 2001-10-12 | 2001-10-12 | Method for manufacturing solder mask of printed circuit board |
US10/155,026 Abandoned US20030072927A1 (en) | 2001-10-12 | 2002-05-28 | Method for manufacturing solder mask of printed circuit board |
US10/155,027 Abandoned US20030071014A1 (en) | 2001-10-12 | 2002-05-28 | Method for manufacturing solder mask of printed circuit board |
US10/800,648 Expired - Fee Related US7080447B2 (en) | 2001-10-12 | 2004-03-16 | Method of manufacturing solder mask of printed circuit board |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
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US09/974,908 Expired - Fee Related US6395625B1 (en) | 2001-10-12 | 2001-10-12 | Method for manufacturing solder mask of printed circuit board |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
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US10/155,027 Abandoned US20030071014A1 (en) | 2001-10-12 | 2002-05-28 | Method for manufacturing solder mask of printed circuit board |
US10/800,648 Expired - Fee Related US7080447B2 (en) | 2001-10-12 | 2004-03-16 | Method of manufacturing solder mask of printed circuit board |
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US (4) | US6395625B1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN103025063A (en) * | 2012-12-05 | 2013-04-03 | 深圳市兴达线路板有限公司 | Circuit board machining process capable of preventing oil overflowing |
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EP1381260A1 (en) * | 2002-07-11 | 2004-01-14 | Ultratera Corporation | Method of plating connecting layers on a conductor pattern of a printed circuit board (PCB) |
US6835673B1 (en) * | 2004-04-28 | 2004-12-28 | Mei-Hui Tai | Semiconductor impedance thermal film processing process |
WO2006126621A1 (en) * | 2005-05-23 | 2006-11-30 | Ibiden Co., Ltd. | Printed wiring board |
US8853723B2 (en) | 2010-08-18 | 2014-10-07 | E. I. Du Pont De Nemours And Company | Light emitting diode assembly and thermal control blanket and methods relating thereto |
WO2012024009A1 (en) | 2010-08-18 | 2012-02-23 | E. I. Du Pont De Nemours And Company | Light emitting diode assembly and thermal control blanket and methods relating thereto |
CN102931096B (en) * | 2012-10-30 | 2015-11-18 | 无锡江南计算技术研究所 | Base plate for packaging solder-resisting manufacturing methods |
US10098236B2 (en) * | 2014-08-26 | 2018-10-09 | Hzo, Inc. | Use of combined masking techniques and/or combined material removal techniques to protectively coat electronic devices |
US9820386B2 (en) | 2016-03-18 | 2017-11-14 | Intel Corporation | Plasma etching of solder resist openings |
CN106028686B (en) * | 2016-06-21 | 2018-11-06 | 海弗斯(深圳)先进材料科技有限公司 | A kind of applying method of high-frequency antenna circuit plate weld-proof membrane |
JPWO2018088345A1 (en) * | 2016-11-11 | 2018-11-08 | 住友ベークライト株式会社 | Resin film with metal foil, structure, method for manufacturing wiring substrate, method for manufacturing semiconductor device |
CN114286532A (en) * | 2020-09-28 | 2022-04-05 | 深南电路股份有限公司 | Method for forming solder mask layer on circuit board, manufacturing method of circuit board and circuit board |
CN113438822A (en) * | 2021-07-02 | 2021-09-24 | 德中(天津)技术发展股份有限公司 | Circuit board manufacturing method for comprehensively optimizing bare board surface treatment and component mounting |
CN113710011A (en) * | 2021-08-30 | 2021-11-26 | 德中(天津)技术发展股份有限公司 | Method for manufacturing circuit board by laser etching pattern after electroplating thickening and weldability processing hole |
CN114216310B (en) * | 2022-02-22 | 2022-04-29 | 四川英创力电子科技股份有限公司 | Manufacturing device and manufacturing method of fine circuit PCB |
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US3620933A (en) * | 1969-12-31 | 1971-11-16 | Macdermid Inc | Forming plastic parts having surfaces receptive to adherent coatings |
FR2210467B1 (en) * | 1972-12-15 | 1975-03-28 | Voisin Ets A | |
US4657839A (en) * | 1981-10-21 | 1987-04-14 | Sullivan Donald F | Photoprinting process and apparatus for exposing paste-consistency photopolymers |
US5047114A (en) * | 1984-11-02 | 1991-09-10 | Amp-Akzo Corporation | Process for the production of metal clad thermoplastic base materials and printed circuits on thermoplastic base materials |
US4764452A (en) * | 1985-11-04 | 1988-08-16 | Tamura Kaken Co., Ltd. | Photosensitive resin compositions |
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JP2734839B2 (en) * | 1991-10-09 | 1998-04-02 | シャープ株式会社 | Etching solution for aluminum, etching method and aluminum etching product |
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DE59409539D1 (en) * | 1993-07-07 | 2000-11-02 | Heinze Dyconex Patente | STRUCTURED CIRCUIT BOARDS AND FILM CIRCUIT BOARDS AND METHOD FOR THE PRODUCTION THEREOF |
JPH07273428A (en) * | 1994-03-29 | 1995-10-20 | Olympus Optical Co Ltd | Working method based on resist pattern formation, and resist pattern-forming equipment |
US6119597A (en) * | 1994-06-14 | 2000-09-19 | Howard W. DeMoore | Method and apparatus for handling printed sheet material |
EP0744884A3 (en) * | 1995-05-23 | 1997-09-24 | Hitachi Chemical Co Ltd | Process for producing multilayer printed circuit board |
US5626774A (en) * | 1995-12-11 | 1997-05-06 | Alliedsignal Inc. | Solder mask for manufacture of printed circuit boards |
KR20070086862A (en) * | 1998-09-03 | 2007-08-27 | 이비덴 가부시키가이샤 | Multilayer printed wiring board and method for manufacturing the same |
-
2001
- 2001-10-12 US US09/974,908 patent/US6395625B1/en not_active Expired - Fee Related
-
2002
- 2002-05-28 US US10/155,026 patent/US20030072927A1/en not_active Abandoned
- 2002-05-28 US US10/155,027 patent/US20030071014A1/en not_active Abandoned
-
2004
- 2004-03-16 US US10/800,648 patent/US7080447B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN103025063A (en) * | 2012-12-05 | 2013-04-03 | 深圳市兴达线路板有限公司 | Circuit board machining process capable of preventing oil overflowing |
Also Published As
Publication number | Publication date |
---|---|
US6395625B1 (en) | 2002-05-28 |
US7080447B2 (en) | 2006-07-25 |
US20040172818A1 (en) | 2004-09-09 |
US20030071014A1 (en) | 2003-04-17 |
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AS | Assignment |
Owner name: ULTRATERA CORPORATION, TAIWAN Free format text: MERGER;ASSIGNOR:S & S TECHNOLOGY CORPORATION;REEL/FRAME:013663/0384 Effective date: 20021107 |
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STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |