US20020197826A1 - Singulation method used in leadless packaging process - Google Patents

Singulation method used in leadless packaging process Download PDF

Info

Publication number
US20020197826A1
US20020197826A1 US09/928,729 US92872901A US2002197826A1 US 20020197826 A1 US20020197826 A1 US 20020197826A1 US 92872901 A US92872901 A US 92872901A US 2002197826 A1 US2002197826 A1 US 2002197826A1
Authority
US
United States
Prior art keywords
lead frame
metal layer
cutting
molded product
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/928,729
Other versions
US6489218B1 (en
Inventor
Hyeongno Kim
Hyung Park
Sangbae Park
Junhong Lee
Kun-A Kang
Bae Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
Rutgers State University of New Jersey
Original Assignee
Advanced Semiconductor Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Assigned to RUTGERS, THE STATE UNIVERSITY OF NEW JERSEY reassignment RUTGERS, THE STATE UNIVERSITY OF NEW JERSEY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: UHRICH, KATHRYN
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Assigned to ADVANCED SEMICONDUCTOR ENGINEERING, INC. reassignment ADVANCED SEMICONDUCTOR ENGINEERING, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KANG, KUN-A, KIM, BAE DOO, KIM, HYEONGNO, LEE, JUNHONG, PARK, HYUNG JUN, PARK, SANGBAE
Application granted granted Critical
Publication of US6489218B1 publication Critical patent/US6489218B1/en
Publication of US20020197826A1 publication Critical patent/US20020197826A1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • This invention relates to a process for making leadless semiconductor packages and more specifically to a singulation method used in the leadless packaging process.
  • Lead frame packages have been used for a long period of time in the IC packaging history mainly because of their low manufacturing cost and high reliability.
  • the traditional lead frame packages have become gradually obsolete for some high performance-required packages.
  • BGA Bit Grid Array Packages
  • CSP Chip Scale Package
  • the former has been widely used in IC chips that have higher I/Os and need better electrical and thermal performance than the conventional packages such as CPU and graphic chips.
  • the latter has been widely used in mobile products of which the footprint, package profile and package weight are major concerns.
  • FIG. 1 shows a bottom view of a leadless package 10 wherein the leads 11 a are disposed at the bottom of the package as compared to the conventional gull-wing or J-leaded type package.
  • the die pad 11 b of the leadless package 10 is exposed from the bottom of the package thereby providing better heat dissipation.
  • leadless packages Due to the elimination of the outer leads, leadless packages are featured by lower profile and light weight. Furthermore, due to the lead length reduction, the corresponding reduction in the resistance, conductance and capacitance make the leadless package 10 very suitable for RF (radio-frequency) product packages operating in several GHz to tens of GHz frequency range. It's also a cost-effective package due to its use of existing BOM (bill of materials). All the above-mentioned properties make the current leadless packages very suitable for telecommunication products such as cellular phones, portable products such as PDA (personal digital assistant), digital cameras, and IA (Information Appliance).
  • PDA personal digital assistant
  • IA Information Appliance
  • the conventional leadless packaging process comprises the following steps.
  • a polyimide (PI) tape was attached to the bottom of a lead frame, and this is to prevent the mold flash problem in the molding process.
  • a lead frame (denoted as 15 in FIG. 2) for used in the MAP (mold array package) molding process comprises a plurality of units 11 each including a plurality of leads 11 a arranged at the periphery of a die pad 11 b .
  • Each die pad 11 b is connected to the lead frame 15 by four tie bars 11 c.
  • IC chips 12 are attached to the die pads 11 b by means of silver epoxy, and the epoxy is cured after die attach. After that, a regular wire-bonding process is performed to make interconnections between the silicon chips 12 and the leads 11 a of the lead frame 15 . After wire bonding, the lead frame 15 and the chips 12 attached thereon are encapsulated in a package body 13 . Typically, a MAP molding process was used to accomplish this encapsulation. The PI tape is then removed after the molding process. The molded product is then marked with either laser or traditional ink. Finally, post-mold curing and singulation steps were conducted to complete the packaging process.
  • a resin-bond saw blade is used to cut the molded product into separate units along predetermined dicing lines to obtain the finished leadless semiconductor packages.
  • the leadless semiconductor package 10 is mounted onto a substrate, such as a printed circuit board (PC board), by using conventional surface mount technology (SMT).
  • the present invention provides a singulation method comprising: (a) providing a molded product including a plurality of semiconductor chips attached and electrically coupled to an upper surface of a lead frame wherein a lower surface of the lead frame is exposed from the bottom of the molded product, the lead frame including a plurality of units in an array arrangement and a plurality of cutting streets between the units, each unit having a die pad and a plurality of leads arranged at the periphery of the die pad, a first metal layer formed on the entire lower surface of the lead frame except the cutting streets; (b) etching the lower surface of the lead frame with the first metal layer as mask such that the cutting streets are etched away to form a plurality of grooves; and (c) cutting the etched molded product along the grooves to obtain the leadless semiconductor packages.
  • step (b) Since the cutting streets of the lead frame are etched away during step (b), the lifetime of the blade is significantly increased by avoiding direct cutting of the cutting streets of the lead frame. Furthermore, since no metal burrs will be created when the blade cuts through the molded product, the finished leadless semiconductor packages will have a good coplanarity thereby enhancing the yield of the SMT mounting process.
  • the present invention further provides a process for making a plurality of leadless semiconductor packages.
  • the process comprises the steps of: (a) providing a lead frame having opposing upper and lower surfaces, the lead frame including a plurality of units in an array arrangement and a plurality of cutting streets between the units, each unit having a die pad and a plurality of leads arranged at the periphery of the die pad, a first metal layer formed on the entire lower surface of the lead frame except the cutting streets; (b) attaching a plurality of chips onto the die pad of the lead frame; (c) electrically coupling the chips to the leads of the lead frame; (d) attaching a tape onto the lower surface of the lead frame; (e) encapsulating the chips against the upper surface of the lead frame to form a molded product; (f) removing the tape from the bottom of the molded product; (g) etching the bottom of the molded product with the first metal layer as mask; and (h) cutting the etched molded product along the cutting streets to obtain the lead
  • each of the leads is half-etched at its lower surface to form an indentation at a location adjacent to the cutting street.
  • the molding compound will fill in the indentations thereby helping to reduce the “undercut” problem occurred in the isotropic etching process.
  • FIG. 1 is a bottom view of a conventional leadless package
  • FIG. 2 is a top plan view of a conventional lead frame for use in forming leadless semiconductor packages
  • FIG. 3 is a cross sectional view of the leadless package of FIG. 1;
  • FIG. 4 is a top plan view of a lead frame for use in forming leadless semiconductor package in accordance with the present invention.
  • FIG. 5 a to FIG. 5 h illustrate a process for making a plurality of leadless semiconductor packages according to a preferred embodiment of the present invention.
  • FIG. 5 a to FIG. 5 h illustrates a process for making a plurality of leadless semiconductor packages according to a preferred embodiment of the present invention.
  • FIG. 4 and 5 a shows a portion of a lead frame 100 for used in the MAP (mold array package) molding process in accordance with the present invention.
  • the lead frame 100 has an upper surface and a lower surface opposed to the upper surface.
  • the lead frame 100 comprises a plurality of units 110 each including a plurality of leads 111 a arranged at the periphery of a die pad 111 b.
  • the units 110 of the lead frame 100 are separated from each other by a plurality of cutting streets 111 c.
  • the cutting streets 111 c generally form an orthogonal grid on the lead frame 100 . Specifically, the cutting streets 111 c are defined between the leads 111 a at the periphery of the die pads 111 b.
  • the lead frame 100 is typically made of a copper-base alloy or made of copper or alloys containing copper, and shaped by pressing or etching. It is noted that the entire lower surface of lead frame 100 is plated with a first metal layer 120 a except areas on the cutting streets 111 c. The entire upper surface of lead frame 100 is plated with a second metal layer 120 b . Preferably, the first metal layer 120 a and the second metal layer 120 b are formed of nickel. Further, a third metal layer 120 c is formed over the second metal layer 120 b on the upper surface of lead frame 100 except areas corresponding to the cutting streets 111 c.
  • the third metal layer 120 c is formed of materials that allow a good bond to the conventional bonding wire material, e.g., silver.
  • each lead 110 a is half-etched at its lower surface to form an indentation 130 at a location adjacent to the cutting street 111 c.
  • a polyimide (PI) tape 200 is attached onto the lower surface of the lead frame 100 , and this is to prevent the mold flash problem in the molding process.
  • semiconductor chips 140 are respectively attached to the die pads 111 b by means of silver epoxy (not shown), and the epoxy is cured after die attach. After that, a regular wire-bonding process is performed to make interconnections between the semiconductor chips 140 and the leads 111 a of the lead frame 100 .
  • the chips 140 are encapsulating against the upper surface of the lead frame 100 to form a molded product.
  • the chips 140 and the upper surface of the lead frame 100 are encapsulated by a package body 150 .
  • a MAP (mold array package) molding process is used to accomplish this encapsulation.
  • molding compound will flow into the indentations 130 of the leads 110 a ; hence, after curing, the indentations 130 is embedded in the package body 150 formed from the molding compound.
  • the PI tape 200 is removed after the molding process.
  • the molded product is then marked with either laser or traditional ink.
  • the lower surface of the lead frame 100 is exposed from the bottom of the molded product.
  • the cutting streets 111 c are removed in an etching process.
  • the etching process is conducted by etching the lower surface of the lead frame 100 with the first metal layer 120 a as mask. Since the entire lower surface of lead frame 100 is plated with the first metal layer 120 a except the cutting streets 111 c, only the cutting streets 111 c without the protection of the first metal layer 120 a are etched away to form a plurality of grooves 160 . It is noted that, after the etching operation, the second metal layer 120 b exposed in the grooves 160 is remain intact. Furthermore, the molding compound filled in the indentations 130 can help to reduce the “undercut” problem occurred in the isotropic etching process.
  • a singulation step is conducted to complete the packaging process.
  • a resin-bond saw blade 300 is used to cut through the molded product into separate units along the grooves 160 . Since the cutting streets of the lead frame are etched away, only the package body 150 and the second metal layer 120 b exposed in the groove 160 is cut by the blade 300 . The lifetime of the blade 300 is significantly increased by avoiding direct cutting of the cutting streets 111 c of the lead frame. Furthermore, since no metal burrs will be created when the blade 300 cuts through the molded product, the finished leadless semiconductor packages have a better coplanarity (as shown in FIG. 5 h ) thereby enhancing the yield of the SMT mounting process.
  • the finished leadless semiconductor package can be mounted onto a substrate, such as a printed circuit board (PC board), like other leadless devices.
  • a PC board is screen printed with a solder paste in a pattern that corresponds to the pattern of the leads exposed from the bottom of the package.
  • the package is then appropriately positioned on the PC board and the solder is reflowed by using the conventional surface mount technology.
  • the leads exposed from the bottom of the package can be printed with solder paste and then mounted onto the PC board.
  • a tin/lead-plating step is performed before soldering the package to PCB thereby enhancing solderability.
  • a layer of tin/lead is plated on the leads exposed from the bottom of the package immediately after the etching process and before the singulation step. It is noted that the second metal layer 120 b exposed in the grooves 160 functions as electric path for plating.
  • the “half-etching” of the present invention is conventional technique, which comprises: (a) forming a photoresist layer on the lower surfaces of the lead frame by conventional techniques such as dry film lamination.
  • the photoresist layer is mainly composed of a resin mixture, and a photoactive material which makes the photoresist layer photodefinable; (b) photodefining the photoresist layer through a photomask and developing such that areas on the lower surfaces of the lead frame at which they are desired to form the indentations are not covered by the photoresist; (c) etching areas on the lower surfaces of the lead frame exposed from the remaining photoresist layer to form the indentations; (d) stripping the remaining photoresist by using conventional techniques.
  • the “half-etching” herein does not mean only exactly removing half of the thickness of the lead frame through etching but also includes a partial etching for removing merely a part of the thickness of the lead frame.

Abstract

A singulation method comprising: (a) providing a molded product including semiconductor chips attached and electrically coupled to an upper surface of a lead frame wherein a lower surface of the lead frame is exposed from the bottom of the molded product, the lead frame including a plurality of units in an array arrangement and cutting streets between the units, each unit having a die pad and leads arranged at the periphery of the die pad, a first metal layer formed on the entire lower surface of the lead frame except the cutting streets; (b) etching the lower surface of the lead frame with the first metal layer as mask such that the cutting streets are etched away to form a plurality of grooves; and (c) cutting the etched molded product along the grooves to obtain the leadless semiconductor packages.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • This invention relates to a process for making leadless semiconductor packages and more specifically to a singulation method used in the leadless packaging process. [0002]
  • 2. Description of the Related Art [0003]
  • Lead frame packages have been used for a long period of time in the IC packaging history mainly because of their low manufacturing cost and high reliability. However, as integrated circuits products move its endless pace toward both a faster speed and a smaller size, the traditional lead frame packages have become gradually obsolete for some high performance-required packages. Thus BGA (Ball Grid Array Packages) and CSP (Chip Scale Package) have emerged and become increasingly popular as a new packaging choice. The former has been widely used in IC chips that have higher I/Os and need better electrical and thermal performance than the conventional packages such as CPU and graphic chips. The latter has been widely used in mobile products of which the footprint, package profile and package weight are major concerns. [0004]
  • However, the lead frame package still remains its market share as a cost-effective solution for low I/O ICs. Traditional lead frame package has its limit of providing a solution for chip scale and low profile package due to the long inner leads and outer leads. Therefore, the semiconductor packaging industry develops a leadless package without outer leads such that both the foot print and the package profile can be greatly reduced. FIG. 1 shows a bottom view of a [0005] leadless package 10 wherein the leads 11 a are disposed at the bottom of the package as compared to the conventional gull-wing or J-leaded type package. The die pad 11 b of the leadless package 10 is exposed from the bottom of the package thereby providing better heat dissipation. Typically, there are four tie bars 11 c being connected to the die pad 11 b.
  • Due to the elimination of the outer leads, leadless packages are featured by lower profile and light weight. Furthermore, due to the lead length reduction, the corresponding reduction in the resistance, conductance and capacitance make the [0006] leadless package 10 very suitable for RF (radio-frequency) product packages operating in several GHz to tens of GHz frequency range. It's also a cost-effective package due to its use of existing BOM (bill of materials). All the above-mentioned properties make the current leadless packages very suitable for telecommunication products such as cellular phones, portable products such as PDA (personal digital assistant), digital cameras, and IA (Information Appliance).
  • The conventional leadless packaging process comprises the following steps. [0007]
  • Firstly, a polyimide (PI) tape was attached to the bottom of a lead frame, and this is to prevent the mold flash problem in the molding process. Typically, a lead frame (denoted as [0008] 15 in FIG. 2) for used in the MAP (mold array package) molding process comprises a plurality of units 11 each including a plurality of leads 11 a arranged at the periphery of a die pad 11 b. Each die pad 11 b is connected to the lead frame 15 by four tie bars 11 c.
  • Then, referring to FIG. 3, [0009] IC chips 12 are attached to the die pads 11 b by means of silver epoxy, and the epoxy is cured after die attach. After that, a regular wire-bonding process is performed to make interconnections between the silicon chips 12 and the leads 11 a of the lead frame 15. After wire bonding, the lead frame 15 and the chips 12 attached thereon are encapsulated in a package body 13. Typically, a MAP molding process was used to accomplish this encapsulation. The PI tape is then removed after the molding process. The molded product is then marked with either laser or traditional ink. Finally, post-mold curing and singulation steps were conducted to complete the packaging process. In the singulation process, a resin-bond saw blade is used to cut the molded product into separate units along predetermined dicing lines to obtain the finished leadless semiconductor packages. Typically, the leadless semiconductor package 10 is mounted onto a substrate, such as a printed circuit board (PC board), by using conventional surface mount technology (SMT).
  • One major problem during the manufacturing of the package occurred in the singulation process. Since the saw blade has to cut through two different materials, i.e., the metal leadframe as well as the molding compound. Cutting through two different materials not only results in shorter blade life, but also creates lead quality problems such as metal burrs created at the lead cutting ends [0010] 14 of the leads 11 a, which will introduce unsatisfactory coplanarity of the finished packages, thereby complicating and reducing the yield of the later SMT mounting process.
    • SUMMARY OF THE INVENTION
  • It is therefore an object of the present invention to provide a singulation method used in a leadless packaging process wherein the lifetime of the blade used in the singulation operation is significantly increased by avoiding direct cutting of the lead frame. [0011]
  • It is another object of the present invention to provide a singulation method used in a leadless packaging process wherein no metal burrs will be created during singulation such that the finished leadless semiconductor packages will have a better coplanarity. [0012]
  • In order to achieve the object mentioned above, the present invention provides a singulation method comprising: (a) providing a molded product including a plurality of semiconductor chips attached and electrically coupled to an upper surface of a lead frame wherein a lower surface of the lead frame is exposed from the bottom of the molded product, the lead frame including a plurality of units in an array arrangement and a plurality of cutting streets between the units, each unit having a die pad and a plurality of leads arranged at the periphery of the die pad, a first metal layer formed on the entire lower surface of the lead frame except the cutting streets; (b) etching the lower surface of the lead frame with the first metal layer as mask such that the cutting streets are etched away to form a plurality of grooves; and (c) cutting the etched molded product along the grooves to obtain the leadless semiconductor packages. [0013]
  • Since the cutting streets of the lead frame are etched away during step (b), the lifetime of the blade is significantly increased by avoiding direct cutting of the cutting streets of the lead frame. Furthermore, since no metal burrs will be created when the blade cuts through the molded product, the finished leadless semiconductor packages will have a good coplanarity thereby enhancing the yield of the SMT mounting process. [0014]
  • The present invention further provides a process for making a plurality of leadless semiconductor packages. The process comprises the steps of: (a) providing a lead frame having opposing upper and lower surfaces, the lead frame including a plurality of units in an array arrangement and a plurality of cutting streets between the units, each unit having a die pad and a plurality of leads arranged at the periphery of the die pad, a first metal layer formed on the entire lower surface of the lead frame except the cutting streets; (b) attaching a plurality of chips onto the die pad of the lead frame; (c) electrically coupling the chips to the leads of the lead frame; (d) attaching a tape onto the lower surface of the lead frame; (e) encapsulating the chips against the upper surface of the lead frame to form a molded product; (f) removing the tape from the bottom of the molded product; (g) etching the bottom of the molded product with the first metal layer as mask; and (h) cutting the etched molded product along the cutting streets to obtain the leadless semiconductor packages. Preferably, each of the leads is half-etched at its lower surface to form an indentation at a location adjacent to the cutting street. During the step (e), the molding compound will fill in the indentations thereby helping to reduce the “undercut” problem occurred in the isotropic etching process.[0015]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. [0016]
  • FIG. 1 is a bottom view of a conventional leadless package; [0017]
  • FIG. 2 is a top plan view of a conventional lead frame for use in forming leadless semiconductor packages; [0018]
  • FIG. 3 is a cross sectional view of the leadless package of FIG. 1; [0019]
  • FIG. 4 is a top plan view of a lead frame for use in forming leadless semiconductor package in accordance with the present invention; and [0020]
  • FIG. 5[0021] a to FIG. 5h illustrate a process for making a plurality of leadless semiconductor packages according to a preferred embodiment of the present invention.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
  • FIG. 5[0022] a to FIG. 5h illustrates a process for making a plurality of leadless semiconductor packages according to a preferred embodiment of the present invention.
  • FIG. 4 and [0023] 5 a shows a portion of a lead frame 100 for used in the MAP (mold array package) molding process in accordance with the present invention. The lead frame 100 has an upper surface and a lower surface opposed to the upper surface. The lead frame 100 comprises a plurality of units 110 each including a plurality of leads 111 a arranged at the periphery of a die pad 111 b. The units 110 of the lead frame 100 are separated from each other by a plurality of cutting streets 111 c. The cutting streets 111 c generally form an orthogonal grid on the lead frame 100. Specifically, the cutting streets 111 c are defined between the leads 111 a at the periphery of the die pads 111 b. The lead frame 100 is typically made of a copper-base alloy or made of copper or alloys containing copper, and shaped by pressing or etching. It is noted that the entire lower surface of lead frame 100 is plated with a first metal layer 120 a except areas on the cutting streets 111 c. The entire upper surface of lead frame 100 is plated with a second metal layer 120 b. Preferably, the first metal layer 120 a and the second metal layer 120 b are formed of nickel. Further, a third metal layer 120 c is formed over the second metal layer 120 b on the upper surface of lead frame 100 except areas corresponding to the cutting streets 111 c. Preferably, the third metal layer 120 c is formed of materials that allow a good bond to the conventional bonding wire material, e.g., silver. Preferably, each lead 110 a is half-etched at its lower surface to form an indentation 130 at a location adjacent to the cutting street 111 c.
  • Referring to FIG. 5[0024] b, a polyimide (PI) tape 200 is attached onto the lower surface of the lead frame 100, and this is to prevent the mold flash problem in the molding process.
  • Referring to FIG. 5[0025] c, semiconductor chips 140 are respectively attached to the die pads 111 b by means of silver epoxy (not shown), and the epoxy is cured after die attach. After that, a regular wire-bonding process is performed to make interconnections between the semiconductor chips 140 and the leads 111 a of the lead frame 100.
  • Referring to FIG. 5[0026] d, after wire bonding, the chips 140 are encapsulating against the upper surface of the lead frame 100 to form a molded product. After encapsulating, the chips 140 and the upper surface of the lead frame 100 are encapsulated by a package body 150. Usually, a MAP (mold array package) molding process is used to accomplish this encapsulation. During the encapsulating process, molding compound will flow into the indentations 130 of the leads 110 a; hence, after curing, the indentations 130 is embedded in the package body 150 formed from the molding compound.
  • Referring to FIG. 5[0027] e, the PI tape 200 is removed after the molding process. The molded product is then marked with either laser or traditional ink.
  • Referring to FIG. 5[0028] f, after removing the tape 200, the lower surface of the lead frame 100 is exposed from the bottom of the molded product. As shown, the cutting streets 111 c are removed in an etching process. Specifically, the etching process is conducted by etching the lower surface of the lead frame 100 with the first metal layer 120 a as mask. Since the entire lower surface of lead frame 100 is plated with the first metal layer 120 a except the cutting streets 111 c, only the cutting streets 111 c without the protection of the first metal layer 120 a are etched away to form a plurality of grooves 160. It is noted that, after the etching operation, the second metal layer 120 b exposed in the grooves 160 is remain intact. Furthermore, the molding compound filled in the indentations 130 can help to reduce the “undercut” problem occurred in the isotropic etching process.
  • Referring to FIG. 5[0029] g and FIG. 5h, a singulation step is conducted to complete the packaging process. As shown in FIG. 5g, a resin-bond saw blade 300 is used to cut through the molded product into separate units along the grooves 160. Since the cutting streets of the lead frame are etched away, only the package body 150 and the second metal layer 120 b exposed in the groove 160 is cut by the blade 300. The lifetime of the blade 300 is significantly increased by avoiding direct cutting of the cutting streets 111 c of the lead frame. Furthermore, since no metal burrs will be created when the blade 300 cuts through the molded product, the finished leadless semiconductor packages have a better coplanarity (as shown in FIG. 5h) thereby enhancing the yield of the SMT mounting process.
  • The finished leadless semiconductor package can be mounted onto a substrate, such as a printed circuit board (PC board), like other leadless devices. For example, a PC board is screen printed with a solder paste in a pattern that corresponds to the pattern of the leads exposed from the bottom of the package. The package is then appropriately positioned on the PC board and the solder is reflowed by using the conventional surface mount technology. Alternatively, the leads exposed from the bottom of the package can be printed with solder paste and then mounted onto the PC board. Preferably, a tin/lead-plating step is performed before soldering the package to PCB thereby enhancing solderability. Specifically, a layer of tin/lead is plated on the leads exposed from the bottom of the package immediately after the etching process and before the singulation step. It is noted that the [0030] second metal layer 120 b exposed in the grooves 160 functions as electric path for plating.
  • It could be understood that the “half-etching” of the present invention is conventional technique, which comprises: (a) forming a photoresist layer on the lower surfaces of the lead frame by conventional techniques such as dry film lamination. Typically, the photoresist layer is mainly composed of a resin mixture, and a photoactive material which makes the photoresist layer photodefinable; (b) photodefining the photoresist layer through a photomask and developing such that areas on the lower surfaces of the lead frame at which they are desired to form the indentations are not covered by the photoresist; (c) etching areas on the lower surfaces of the lead frame exposed from the remaining photoresist layer to form the indentations; (d) stripping the remaining photoresist by using conventional techniques. It is noted that the “half-etching” herein does not mean only exactly removing half of the thickness of the lead frame through etching but also includes a partial etching for removing merely a part of the thickness of the lead frame. [0031]
  • Although the invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed. [0032]

Claims (14)

What is claimed is:
1. A singulation method used in a process for making a plurality of leadless semiconductor packages, the singulation method comprising the following steps:
providing a molded product including a plurality of semiconductor chips attach ed and electrically coupled to an upper surface of a lead frame wherein a lower surface of the lead frame is exposed from the bottom of the molded product, the lead frame including a plurality of units in an array arrangement and a plurality of cutting streets between the units, each unit having a die pad and a plurality of leads arranged at the periphery of the die pad, a first metal layer formed on the entire lower surface of the lead frame except the cutting streets;
etching the lower surface of the lead frame with the first metal layer as mask such that the cutting streets are etched away to form a plurality of grooves; and
cutting the etched molded product along the grooves to obtain the leadless semiconductor packages.
2. The method as claimed in claim 1, further comprising the step of half-etching each of the leads at its lower surface to form an indentation at a location adjacent to the cutting street.
3. The method as claimed in claim 1, wherein the first metal layer is made of nickel.
4. The method as claimed in claim 1, wherein the first metal layer is formed by plating.
5. The method as claimed in claim 1, wherein the lead frame is made of copper.
6. A process for making a plurality of leadless semiconductor packages, comprising the following steps:
providing a lead frame having opposing upper and lower surfaces, the lead frame including a plurality of units in an array arrangement and a plurality of cutting streets between the units, each unit having a die pad and a plurality of leads arranged at the periphery of the die pad, a first metal layer formed on the entire lower surface of the lead frame except the cutting streets;
attaching a plurality of chips onto the die pads of the lead frame;
electrically coupling the chips to the leads of the lead frame;
attaching a tape onto the lower surface of the lead frame;
encapsulating the chips against the upper surface of the lead frame to form a molded product;
removing the tape from the bottom of the molded product to expose the lower surface of the lead frame;
etching the lower surface of the lead frame with the first metal layer as mask such that the cutting streets are etched away to form a plurality of grooves; and
cutting the etched molded product along the grooves to obtain the leadless semiconductor packages.
7. The process as claimed in claim 6, further comprising the step of half-etching each of the leads at its lower surface to form an indentation at a location adjacent to the cutting street.
8. The process as claimed in claim 6, wherein the first metal layer is made of nickel.
9. The process as claimed in claim 6, wherein the first metal layer is formed on the lower surface of the lead frame by plating.
10. The process as claimed in claim 6, wherein the lead frame is made of copper.
11. The process as claimed in claim 6, wherein the entire upper surface of lead frame is plated with a second metal layer.
12. The process as claimed in claim 11, after the etching step and before the cutting step, further comprising the step of plating a layer of tin/lead on the leads exposed from the bottom of the molded product with the second metal layer exposed in the grooves functioning as electric path for plating.
13. The process as claimed in claim 12, wherein the second metal layer is made of nickel.
14. The process as claimed in claim 12, wherein a third metal layer is formed over the second metal layer on the upper surface of lead frame except areas corresponding to the cutting streets
US09/928,729 2001-06-21 2001-08-14 Singulation method used in leadless packaging process Expired - Lifetime US6489218B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
TW90115514A 2001-06-21
TW90115514 2001-06-21
TW090115514A TW498443B (en) 2001-06-21 2001-06-21 Singulation method for manufacturing multiple lead-free semiconductor packages

Publications (2)

Publication Number Publication Date
US6489218B1 US6489218B1 (en) 2002-12-03
US20020197826A1 true US20020197826A1 (en) 2002-12-26

Family

ID=21678636

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/928,729 Expired - Lifetime US6489218B1 (en) 2001-06-21 2001-08-14 Singulation method used in leadless packaging process

Country Status (2)

Country Link
US (1) US6489218B1 (en)
TW (1) TW498443B (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030054591A1 (en) * 2001-09-20 2003-03-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device, and method of manufacturing the semiconductor device
US20030124762A1 (en) * 2001-12-27 2003-07-03 Nobuaki Hashimoto Optical device and method of manufacturing the same, optical module, circuit board, and electronic instrument
US20030127711A1 (en) * 2002-01-09 2003-07-10 Matsushita Electric Industrial Co., Ltd. Lead frame, method for manufacturing the same, resin-encapsulated semiconductor device and method for manufacturing the same
US20040107570A1 (en) * 1997-08-20 2004-06-10 Micron Technology, Inc. Singulation methods and substrates for use with same
US20040232524A1 (en) * 2003-05-23 2004-11-25 Howard Gregory E. Scribe street width reduction by deep trench and shallow saw cut
US6841414B1 (en) * 2002-06-19 2005-01-11 Amkor Technology, Inc. Saw and etch singulation method for a chip package
US7008825B1 (en) * 2003-05-27 2006-03-07 Amkor Technology, Inc. Leadframe strip having enhanced testability
US7049177B1 (en) * 2004-01-28 2006-05-23 Asat Ltd. Leadless plastic chip carrier with standoff contacts and die attach pad
US20070096271A1 (en) * 2003-09-01 2007-05-03 Norio Takahashi Substrate frame
CN100411125C (en) * 2005-05-30 2008-08-13 矽品精密工业股份有限公司 Method for preparing packages of semiconductor, and cutting unit
US20080206913A1 (en) * 2007-02-23 2008-08-28 Finisar Corporation Cleaving edge-emitting lasers from a wafer cell
US20110159643A1 (en) * 2009-12-31 2011-06-30 Siliconware Precision Industries Co., Ltd. Fabrication method of semiconductor package structure
CN102148168A (en) * 2010-02-04 2011-08-10 飞思卡尔半导体公司 Method for manufacturing semiconductor package with improved standoff
KR200480459Y1 (en) 2014-07-07 2016-05-26 창 와 테크놀러지 컴퍼니 리미티드 dual layered lead frame structure

Families Citing this family (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4349541B2 (en) * 2000-05-09 2009-10-21 大日本印刷株式会社 Resin-encapsulated semiconductor device frame
US6543510B1 (en) * 2000-06-07 2003-04-08 Micron Technology, Inc. Apparatus and methods for coverlay removal and adhesive application
US6548764B1 (en) * 2000-06-07 2003-04-15 Micron Technology, Inc. Semiconductor packages and methods for making the same
US6836166B2 (en) 2003-01-08 2004-12-28 Micron Technology, Inc. Method and system for delay control in synchronization circuits
WO2004100255A1 (en) * 2003-04-29 2004-11-18 Semiconductor Components Industries L.L.C. Method of making a low profile packaged semiconductor device
US7094633B2 (en) * 2003-06-23 2006-08-22 Sandisk Corporation Method for efficiently producing removable peripheral cards
US7153724B1 (en) * 2003-08-08 2006-12-26 Ns Electronics Bangkok (1993) Ltd. Method of fabricating no-lead package for semiconductor die with half-etched leadframe
TWI231578B (en) * 2003-12-01 2005-04-21 Advanced Semiconductor Eng Anti-warpage package and method for making the same
MY136216A (en) * 2004-02-13 2008-08-29 Semiconductor Components Ind Method of forming a leadframe for a semiconductor package
US7281535B2 (en) * 2004-02-23 2007-10-16 Towa Intercon Technology, Inc. Saw singulation
KR101070890B1 (en) * 2004-04-16 2011-10-06 삼성테크윈 주식회사 Method for manufacturing the semiconductor package of multi-row lead type
US7125747B2 (en) * 2004-06-23 2006-10-24 Advanced Semiconductor Engineering, Inc. Process for manufacturing leadless semiconductor packages including an electrical test in a matrix of a leadless leadframe
US7087461B2 (en) * 2004-08-11 2006-08-08 Advanced Semiconductor Engineering, Inc. Process and lead frame for making leadless semiconductor packages
US7169651B2 (en) * 2004-08-11 2007-01-30 Advanced Semiconductor Engineering, Inc. Process and lead frame for making leadless semiconductor packages
US20060069291A1 (en) * 2004-09-24 2006-03-30 General Electric Company Phosphazenium salt phase transfer catalysts
US20060125062A1 (en) * 2004-12-15 2006-06-15 Zuniga-Ortiz Edgar R Semiconductor package having improved adhesion and solderability
US20060199308A1 (en) * 2005-03-02 2006-09-07 Advanced Semiconductor Engineering, Inc. Process for manufacturing sawing type leadless semiconductor packages
JP4544143B2 (en) * 2005-06-17 2010-09-15 セイコーエプソン株式会社 Semiconductor device manufacturing method, semiconductor device, circuit board, and electronic apparatus
US20070072338A1 (en) * 2005-09-26 2007-03-29 Advanced Chip Engineering Technology Inc. Method for separating package of WLP
US7943431B2 (en) * 2005-12-02 2011-05-17 Unisem (Mauritius) Holdings Limited Leadless semiconductor package and method of manufacture
JP4851214B2 (en) * 2006-03-24 2012-01-11 株式会社ディスコ Package substrate division method
US8461694B1 (en) 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8492906B2 (en) 2006-04-28 2013-07-23 Utac Thai Limited Lead frame ball grid array with traces under die
US8460970B1 (en) 2006-04-28 2013-06-11 Utac Thai Limited Lead frame ball grid array with traces under die having interlocking features
US8487451B2 (en) 2006-04-28 2013-07-16 Utac Thai Limited Lead frame land grid array with routing connector trace under unit
US8310060B1 (en) 2006-04-28 2012-11-13 Utac Thai Limited Lead frame land grid array
US8013437B1 (en) 2006-09-26 2011-09-06 Utac Thai Limited Package with heat transfer
US8125077B2 (en) 2006-09-26 2012-02-28 Utac Thai Limited Package with heat transfer
US20080085572A1 (en) * 2006-10-05 2008-04-10 Advanced Chip Engineering Technology Inc. Semiconductor packaging method by using large panel size
US8013332B2 (en) * 2006-10-20 2011-09-06 Sandisk Technologies Inc. Portable memory devices
US7928010B2 (en) * 2006-10-20 2011-04-19 Sandisk Corporation Method for producing portable memory devices
US9082607B1 (en) 2006-12-14 2015-07-14 Utac Thai Limited Molded leadframe substrate semiconductor package
US9761435B1 (en) 2006-12-14 2017-09-12 Utac Thai Limited Flip chip cavity package
US20080174981A1 (en) * 2007-01-24 2008-07-24 Chan Say Teow Pre-molded lead frame and process for manufacturing the same
US7790512B1 (en) 2007-11-06 2010-09-07 Utac Thai Limited Molded leadframe substrate semiconductor package
TWI378518B (en) * 2007-11-21 2012-12-01 Chipmos Technologies Inc Leadframe for leadless package and package structure thereof
US8063470B1 (en) 2008-05-22 2011-11-22 Utac Thai Limited Method and apparatus for no lead semiconductor package
JP5203045B2 (en) * 2008-05-28 2013-06-05 日本特殊陶業株式会社 Intermediate product of multilayer wiring board, manufacturing method of multilayer wiring board
US9947605B2 (en) 2008-09-04 2018-04-17 UTAC Headquarters Pte. Ltd. Flip chip cavity package
TWI378515B (en) * 2008-11-07 2012-12-01 Chipmos Technoligies Inc Method of fabricating quad flat non-leaded package
CN102341899B (en) * 2009-03-06 2013-05-29 优特香港有限公司 Leadless array plastic package with various IC packaging configurations
US8367476B2 (en) * 2009-03-12 2013-02-05 Utac Thai Limited Metallic solderability preservation coating on metal part of semiconductor package to prevent oxide
US9449900B2 (en) * 2009-07-23 2016-09-20 UTAC Headquarters Pte. Ltd. Leadframe feature to minimize flip-chip semiconductor die collapse during flip-chip reflow
US9355940B1 (en) 2009-12-04 2016-05-31 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
US8368189B2 (en) 2009-12-04 2013-02-05 Utac Thai Limited Auxiliary leadframe member for stabilizing the bond wire process
CN102117753A (en) * 2010-01-05 2011-07-06 飞思卡尔半导体公司 Method for packaging semiconductor device
US8575732B2 (en) 2010-03-11 2013-11-05 Utac Thai Limited Leadframe based multi terminal IC package
US8871571B2 (en) 2010-04-02 2014-10-28 Utac Thai Limited Apparatus for and methods of attaching heat slugs to package tops
DE102011056700A1 (en) * 2011-12-20 2013-06-20 Osram Opto Semiconductors Gmbh Process for the production of optoelectronic semiconductor components, lead frame composite and optoelectronic semiconductor component
US9029198B2 (en) 2012-05-10 2015-05-12 Utac Thai Limited Methods of manufacturing semiconductor devices including terminals with internal routing interconnections
US9449905B2 (en) 2012-05-10 2016-09-20 Utac Thai Limited Plated terminals with routing interconnections semiconductor device
US9006034B1 (en) 2012-06-11 2015-04-14 Utac Thai Limited Post-mold for semiconductor package having exposed traces
TWI456217B (en) * 2012-10-18 2014-10-11 Powertech Technology Inc Probing method of leadless semiconductor package
US9012268B2 (en) * 2013-06-28 2015-04-21 Stmicroelectronics, Inc. Leadless packages and method of manufacturing same
CN104681505B (en) * 2013-11-27 2021-05-28 意法半导体研发(深圳)有限公司 Leadless surface mount component package and method of manufacturing the same
US10242953B1 (en) 2015-05-27 2019-03-26 Utac Headquarters PTE. Ltd Semiconductor package with plated metal shielding and a method thereof
WO2015145651A1 (en) * 2014-03-27 2015-10-01 ルネサスエレクトロニクス株式会社 Semiconductor device manufacturing method and semiconductor device
US10242934B1 (en) 2014-05-07 2019-03-26 Utac Headquarters Pte Ltd. Semiconductor package with full plating on contact side surfaces and methods thereof
US9082760B2 (en) * 2014-06-16 2015-07-14 Chang Wah Technology Co., Ltd. Dual layered lead frame
US9373569B1 (en) * 2015-09-01 2016-06-21 Texas Instruments Incorporation Flat no-lead packages with electroplated edges
US9917038B1 (en) 2015-11-10 2018-03-13 Utac Headquarters Pte Ltd Semiconductor package with multiple molding routing layers and a method of manufacturing the same
JP2017162876A (en) * 2016-03-07 2017-09-14 株式会社ジェイデバイス Method for manufacturing semiconductor package
JP6752639B2 (en) 2016-05-02 2020-09-09 ローム株式会社 Manufacturing method of semiconductor devices
US10388616B2 (en) 2016-05-02 2019-08-20 Rohm Co., Ltd. Semiconductor device and method for manufacturing the same
US10276477B1 (en) 2016-05-20 2019-04-30 UTAC Headquarters Pte. Ltd. Semiconductor package with multiple stacked leadframes and a method of manufacturing the same
US10892211B2 (en) * 2017-08-09 2021-01-12 Semtech Corporation Side-solderable leadless package
US10249556B1 (en) 2018-03-06 2019-04-02 Nxp B.V. Lead frame with partially-etched connecting bar
EP3736857A1 (en) * 2019-05-07 2020-11-11 Nexperia B.V. Through hole side wettable flank
CN113035722A (en) 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 Packaging process for plating with selective molding
CN113035721A (en) * 2019-12-24 2021-06-25 维谢综合半导体有限责任公司 Packaging process for plating conductive film on side wall
CN113628977A (en) * 2021-06-21 2021-11-09 江西万年芯微电子有限公司 Frame and copper sheet device packaging design method

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3018542B2 (en) * 1991-04-03 2000-03-13 セイコーエプソン株式会社 Lead frame and manufacturing method thereof
JPH09139362A (en) * 1995-11-10 1997-05-27 Disco Abrasive Syst Ltd Dicing method
JP3012816B2 (en) 1996-10-22 2000-02-28 松下電子工業株式会社 Resin-sealed semiconductor device and method of manufacturing the same
JP3562311B2 (en) * 1998-05-27 2004-09-08 松下電器産業株式会社 Method for manufacturing lead frame and resin-encapsulated semiconductor device

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040107570A1 (en) * 1997-08-20 2004-06-10 Micron Technology, Inc. Singulation methods and substrates for use with same
US6886247B2 (en) * 1997-08-20 2005-05-03 Micron Technology, Inc. Circuit board singulation methods
US20030054591A1 (en) * 2001-09-20 2003-03-20 Mitsubishi Denki Kabushiki Kaisha Semiconductor device, and method of manufacturing the semiconductor device
US20030124762A1 (en) * 2001-12-27 2003-07-03 Nobuaki Hashimoto Optical device and method of manufacturing the same, optical module, circuit board, and electronic instrument
US8193091B2 (en) * 2002-01-09 2012-06-05 Panasonic Corporation Resin encapsulated semiconductor device and method for manufacturing the same
US20030127711A1 (en) * 2002-01-09 2003-07-10 Matsushita Electric Industrial Co., Ltd. Lead frame, method for manufacturing the same, resin-encapsulated semiconductor device and method for manufacturing the same
US6841414B1 (en) * 2002-06-19 2005-01-11 Amkor Technology, Inc. Saw and etch singulation method for a chip package
US20040232524A1 (en) * 2003-05-23 2004-11-25 Howard Gregory E. Scribe street width reduction by deep trench and shallow saw cut
US6890836B2 (en) * 2003-05-23 2005-05-10 Texas Instruments Incorporated Scribe street width reduction by deep trench and shallow saw cut
US7008825B1 (en) * 2003-05-27 2006-03-07 Amkor Technology, Inc. Leadframe strip having enhanced testability
US20070096271A1 (en) * 2003-09-01 2007-05-03 Norio Takahashi Substrate frame
US7049177B1 (en) * 2004-01-28 2006-05-23 Asat Ltd. Leadless plastic chip carrier with standoff contacts and die attach pad
CN100411125C (en) * 2005-05-30 2008-08-13 矽品精密工业股份有限公司 Method for preparing packages of semiconductor, and cutting unit
US20080206913A1 (en) * 2007-02-23 2008-08-28 Finisar Corporation Cleaving edge-emitting lasers from a wafer cell
US7858493B2 (en) * 2007-02-23 2010-12-28 Finisar Corporation Cleaving edge-emitting lasers from a wafer cell
US20110159643A1 (en) * 2009-12-31 2011-06-30 Siliconware Precision Industries Co., Ltd. Fabrication method of semiconductor package structure
US8304268B2 (en) * 2009-12-31 2012-11-06 Siliconware Precision Industries Co., Ltd. Fabrication method of semiconductor package structure
CN102148168A (en) * 2010-02-04 2011-08-10 飞思卡尔半导体公司 Method for manufacturing semiconductor package with improved standoff
KR200480459Y1 (en) 2014-07-07 2016-05-26 창 와 테크놀러지 컴퍼니 리미티드 dual layered lead frame structure

Also Published As

Publication number Publication date
TW498443B (en) 2002-08-11
US6489218B1 (en) 2002-12-03

Similar Documents

Publication Publication Date Title
US6489218B1 (en) Singulation method used in leadless packaging process
US6400004B1 (en) Leadless semiconductor package
US6773961B1 (en) Singulation method used in leadless packaging process
US7169651B2 (en) Process and lead frame for making leadless semiconductor packages
US7087461B2 (en) Process and lead frame for making leadless semiconductor packages
US7439097B2 (en) Taped lead frames and methods of making and using the same in semiconductor packaging
KR100347706B1 (en) New molded package having a implantable circuits and manufacturing method thereof
US6420779B1 (en) Leadframe based chip scale package and method of producing the same
US7378299B2 (en) Leadless semiconductor package and manufacturing method thereof
US6979594B1 (en) Process for manufacturing ball grid array package
US8084299B2 (en) Semiconductor device package and method of making a semiconductor device package
US6762118B2 (en) Package having array of metal pegs linked by printed circuit lines
US7129116B2 (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US8241967B2 (en) Semiconductor package with a support structure and fabrication method thereof
CN209785926U (en) semiconductor device with a plurality of transistors
US6524886B2 (en) Method of making leadless semiconductor package
US6610924B1 (en) Semiconductor package
JPH11297917A (en) Semiconductor device and its manufacture
JP2006049694A (en) Dual gauge lead frame
KR101120718B1 (en) Dual gauge leadframe
TWI237357B (en) Singulation method used in leadless packaging process
JP2003273283A (en) Semiconductor device and its manufacturing method
JPH08162558A (en) Semiconductor device
KR20110125001A (en) Semiconductor package capable of cost reduction and manufacturing method thereof

Legal Events

Date Code Title Description
AS Assignment

Owner name: RUTGERS, THE STATE UNIVERSITY OF NEW JERSEY, NEW J

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:UHRICH, KATHRYN;REEL/FRAME:010068/0017

Effective date: 19990611

AS Assignment

Owner name: ADVANCED SEMICONDUCTOR ENGINEERING, INC., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, HYEONGNO;PARK, HYUNG JUN;PARK, SANGBAE;AND OTHERS;REEL/FRAME:012079/0895

Effective date: 20010621

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12