US20020102797A1 - Composite gate dielectric layer - Google Patents

Composite gate dielectric layer Download PDF

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Publication number
US20020102797A1
US20020102797A1 US09/773,442 US77344201A US2002102797A1 US 20020102797 A1 US20020102797 A1 US 20020102797A1 US 77344201 A US77344201 A US 77344201A US 2002102797 A1 US2002102797 A1 US 2002102797A1
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Prior art keywords
layer
silicon oxide
dielectric layer
silicon
chemical vapor
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Abandoned
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US09/773,442
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English (en)
Inventor
David Muller
Gregory Timp
Glen Wilk
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Nokia of America Corp
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Individual
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Priority to US09/773,442 priority Critical patent/US20020102797A1/en
Assigned to LUCENT TECHNOLOGIES INC. reassignment LUCENT TECHNOLOGIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TIMP, GREGORY L., MULLER, DAVID A., WILK, GLEN DAVID
Priority to JP2002025036A priority patent/JP2002305303A/ja
Publication of US20020102797A1 publication Critical patent/US20020102797A1/en
Priority to US10/227,091 priority patent/US7253063B2/en
Priority to JP2009063925A priority patent/JP2009177192A/ja
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer

Definitions

  • the present invention relates to semiconductor devices.
  • a capacitance is associated with a gate dielectric layer, which insulates a gate electrode from a channel disposed within a semiconductor substrate.
  • the input capacitance of a FET may be increased by either reducing the thickness of the gate dielectric layer or increasing its dielectric constant.
  • Gate dielectric layers have historically been realized by bulk silicon dioxide, SiO 2 .
  • industry has been reducing the thickness of bulk silicon dioxide-based gate dielectric layers to increase input FET capacitances.
  • bulk silicon dioxide becomes exceedingly susceptible to leakage currents tunneling through the gate dielectric layer.
  • the leakage current problem is now becoming a practical concern.
  • a gate dielectric layer may be advantageously formed from at least one layer of the silicon oxide (SiO X ⁇ 2 ) to increase the input FET capacitance, while also providing a desirable interface with a silicon substrate.
  • a gate dielectric layer formed of at least one layer of silicon oxide (SiO X ⁇ 2 ) having a thickness of about 5 ⁇ or less may be insufficient to withstand leakage current problems. Consequently, we have invented a composite gate dielectric layer having a complementary dielectric layer formed upon a layer of silicon oxide (SiO X ⁇ 2 ). The complementary dielectric layer is of sufficient thickness to substantially inhibit the flow of leakage current.
  • the complementary dielectric layer has a dielectric constant greater than that of the layer of silicon oxide.
  • the complementary dielectric layer may be formed from at least one of aluminate, silicate, ZrO 2 , HfO 2 , TiO 2 , Gd 2 O 3 , Y 2 O 3 , Si 3 N 4 , Ta 2 O 5 and Al 2 O 3 .
  • FIG. 2 is a cross-sectional view of an embodiment of the present invention
  • FIG. 3 is a cross-sectional view of another embodiment of the present invention.
  • FIG. 4 is a flow chart of another embodiment of the present invention.
  • the input capacitance of a field effect transistor is associated with a gate dielectric layer positioned between a gate electrode and a channel disposed within a silicon semiconductor.
  • FET field effect transistor
  • C is the capacitance
  • A is the area (length by width) of the dielectric layer
  • C/A is the capacitance per unit area
  • ⁇ 0 is a constant (i.e., 8.854 ⁇ 10 ⁇ 12 Farads/meter) referred to as the permittivity in free space
  • k is the dielectric constant of the dielectric layer
  • t is the thickness of the dielectric layer.
  • silicon oxide, SiO X ⁇ 2 is an oxide-based compound having a stoichiometry in which each silicon atom is bonded with four or less oxygen atoms.
  • silicon oxide, SiO X ⁇ 2 exhibits a dielectric constant greater than that of bulk silicon dioxide. This general observation was initially theorized in the aforementioned study reported by two of us in “The Electronic Structure at the Atomic Scale Of Ultrathin Gate Oxides,” Nature, Vol. 399, June 1999.
  • the layer of silicon oxide, SiO X ⁇ 2 creates a high quality interface with silicon. Consequently, we have recognized that a layer of silicon oxide, SiO X ⁇ 2 , may be advantageously employed as a gate dielectric layer to increase the input capacitance per unit area of a semiconductor device, such as a field effect transistor (“FET”).
  • FET field effect transistor
  • FIG. 1 graphically depicts the dielectric constant of a layer of silicon oxide, SiO X ⁇ 2 , as a function of the layer's thickness.
  • the dielectric constant of the layer of silicon oxide, SiO X ⁇ 2 begins to increase beyond that of bulk silicon dioxide (i.e., about 3.9).
  • Our inventive efforts have uncovered that the dielectric constant of the layer of silicon oxide, SiO X ⁇ 2 , peaks below 3 ⁇ .
  • the layer of silicon oxide reaches a dielectric constant in the range of about 8 to 12, at a thickness of about 3 ⁇ or less.
  • FIG. 2 a first embodiment of the present invention is illustrated.
  • a cross-sectional view of a semiconductor device 10 such as a metal oxide semiconductor FET (“MOSFET”), for example, is shown.
  • MOSFET metal oxide semiconductor FET
  • gate dielectric layer 60 may be formed from a layer of silicon oxide, SiO X ⁇ 2 .
  • the layer of silicon oxide, SiO X ⁇ 2 exhibits a dielectric constant, k, greater than that of bulk silicon dioxide (i.e., about 3.9).
  • this layer of silicon oxide, SiO X ⁇ 2 has a thickness of about 5 ⁇ or less to realize this increased dielectric constant.
  • the dielectric constant of this layer of silicon oxide, SiO X ⁇ 2 may be optimized in view of the potential flow of leakage current through gate dielectric layer 60 .
  • Gate dielectric layer 65 comprises a first layer 60 of silicon oxide, SiO X ⁇ 2 .
  • First layer 60 has a dielectric constant, k, greater than that of bulk silicon dioxide. As shown in FIG. 1, first layer 60 has a thickness of about 5 ⁇ or less to realize this increased dielectric constant.
  • second layer 80 reduces the input capacitance per unit area of device 100 because the positioning of second layer 80 upon first layer 60 of silicon oxide, SiO X ⁇ 2 , creates a series capacitance.
  • the input capacitance, C IN of device 100 may be expressed using the following mathematical equations:
  • C 1 is the capacitance created by first layer 60
  • C 2 is the capacitance created by the second layer 80 .
  • C IN /A is input capacitance per unit area. From the hereinabove mathematical equations, input capacitance per unit area will decrease with the addition of second layer 80 . As such, the thickness of second layer 80 may be optimized to further minimize the potential flow of leakage current through gate dielectric layer 65 , while providing the maximum possible capacitance per unit area for device 100 .
  • Second layer 80 advantageously may have a thickness of about 3.5 ⁇ , a dielectric constant of in the range of about 9-10.
  • the inclusion of second layer 80 also enables the thickness of first layer 60 to be potentially reduced to about 3.5 ⁇ such that its dielectric constant is also in the range of about 9-10.
  • FIG. 4 a third embodiment of the present invention is illustrated.
  • a cross-sectional view is shown of a semiconductor device 110 .
  • device 110 comprises a conductive channel 30 electrically connected to a source 40 and a drain 50 , each of which are formed within a silicon substrate 20 .
  • Composite dielectric layer 75 comprises at least two dielectric layers, one of which being a layer 60 of silicon oxide, SiO X ⁇ 2 .
  • First layer 60 has a dielectric constant, k, greater than about 3.9, and as such, a thickness of about 5 ⁇ or less.
  • First layer 60 is formed upon channel 30 to provide an interface with silicon substrate 20 which is less rough in comparison with the alternative materials presently being explored for use as gate dielectric layers.
  • composite dielectric layer 75 of device 110 comprises a complementary dielectric layer 90 formed from alternative materials.
  • Complementary dielectric layer 90 has a higher dielectric constant than that of layer 60 of silicon oxide, SiO X ⁇ 2 .
  • complementary dielectric layer 90 may be sufficiently thicker than second layer 80 of FIG. 3 to further inhibit the flow of leakage current, all while maintaining the capacitance per unit area of device 110 . Consequently, complementary dielectric layer 90 may have a thickness as high as about 60 ⁇ , for example.
  • complementary dielectric layer 90 advantageously may have a dielectric constant of greater than about 7 and as high as about 30—though higher dielectric constants may be derived by skilled artisans upon reviewing the instant disclosure—a thickness range of about 5 ⁇ and 60 ⁇ . We believe that the inclusion of complementary dielectric layer 90 within composite gate dielectric layer 75 will further reduce the leakage current.
  • a dielectric layer is formed upon a clean silicon substrate.
  • a thermal layer of silicon dioxide is grown upon a clean silicon (Si) substrate.
  • This growth step may be realized by rapid thermal oxidation at a temperature of about 1000° C., for about 5 seconds or less, at a pressure of 0.5 mTorr or less. Similar results have been obtained using a furnace at a temperature of about 800° C. or more, for about 10 seconds or more, at a pressure of about one (1) mTorr or less.
  • a transition metal, such as Zr, Hf or Ti, for example, is subsequently implanted into the thermally grown layer of silicon dioxide.
  • the implanted thermally grown layer of silicon dioxide is annealed in an O 2 atmosphere at a temperature of about 800° C. or more, for about 5 seconds or less, at a pressure of about one (1) mTorr or less.
  • the anneal step forms a layer of silicon oxide, SiO X ⁇ 2 , upon the silicon substrate, and the aforementioned complementary dielectric layer upon the silicon oxide layer.
  • an etch back step may also be performed after the growth step, as well as after the implant step to insure that the resultant thickness of the silicon oxide is about 5 ⁇ or less.
  • This etch back step may be performed using an HF chemistry, as well as atomic scale electron-energy-loss spectroscopy (“EELS”) to ascertain the appropriate thickness.
  • EELS atomic scale electron-energy-loss spectroscopy
  • a layer of silicon oxide, SiO X ⁇ 2 is formed upon a clean silicon substrate using atomic layer chemical vapor deposition (“ALCVD”) techniques.
  • ACVD atomic layer chemical vapor deposition
  • a monolayer of oxygen is first formed upon the substrate by ALCVD.
  • a monolayer of a hydroxyl group is first formed upon the substrate by ALCVD.
  • a monolayer of silicon (with a ligand) is thereafter formed upon the monolayer of oxygen (or hydroxyl group), and a second monolayer of oxygen (again in practice a hydroxyl group) is formed upon the monolayer of silicon (with a ligand).
  • Each ALCVD step may be advantageously performed at a temperature of about 1000° C.
  • each ALCVD step includes the step of introducing an oxygen or silicon precursor dose of about 10 15 atoms/cm 2 .
  • the complementary dielectric layer may be formed upon the layer of silicon oxide.
  • a second layer(s) of silicon oxide may be formed upon the layer of silicon oxide.
  • a composite dielectric layer is formed upon a clean silicon substrate by either a metal organic chemical vapor deposition (“MOCVD”) or a low pressure chemical vapor deposition (“LPCVD”) technique.
  • MOCVD metal organic chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • gaseous ZrO and SiO are introduced in the presence of the substrate.
  • a layer of silicon oxide, SiO X ⁇ 2 is formed upon the substrate, and a metal-silicate is formed upon the layer of silicon oxide.
  • a composite dielectric layer is formed by initially evaporating a metal in an O 2 atmosphere.
  • These metal atoms deposited by any means, such as CVD or PVD, for example, form a layer of metal-oxide or metal-silicide upon the cleaned silicon substrate.
  • an anneal step is performed in an O 2 atmosphere at a temperature range of about 800° C. and 1100° C., for about 5 seconds or less, at a pressure of about one (1) mTorr or less. Consequently, a layer of silicon oxide, SiO X ⁇ 2 , is formed upon the substrate, and a layer of metal-silicate is formed upon the layer of silicon oxide.
  • a composite dielectric layer is formed by initially sputtering transition metal atoms into an O 2 atmosphere having a temperature or about 800° C. or more.
  • a chemical vapor deposition or an evaporation step may be performed. These metal atoms form a layer of metal or metal-silicide upon the cleaned silicon substrate.
  • an anneal step is performed in an O 2 atmosphere at a temperature of about 800° C. ore more, for about 5 seconds or less, at a pressure of about one (1) mTorr or less. Consequently, a layer of silicon oxide, SiO X ⁇ 2 , is formed upon the substrate, and a layer of metal-silicate is formed upon the layer of silicon oxide.

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  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
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  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
US09/773,442 2001-02-01 2001-02-01 Composite gate dielectric layer Abandoned US20020102797A1 (en)

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Application Number Priority Date Filing Date Title
US09/773,442 US20020102797A1 (en) 2001-02-01 2001-02-01 Composite gate dielectric layer
JP2002025036A JP2002305303A (ja) 2001-02-01 2002-02-01 半導体デバイスとゲート誘電体組み合わせ層の形成方法。
US10/227,091 US7253063B2 (en) 2001-02-01 2002-08-23 Method of fabricating a composite gate dielectric layer
JP2009063925A JP2009177192A (ja) 2001-02-01 2009-03-17 半導体デバイスとゲート誘電体組み合わせ層の形成方法

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