US20020050403A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
US20020050403A1
US20020050403A1 US09/370,990 US37099099A US2002050403A1 US 20020050403 A1 US20020050403 A1 US 20020050403A1 US 37099099 A US37099099 A US 37099099A US 2002050403 A1 US2002050403 A1 US 2002050403A1
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US
United States
Prior art keywords
base
semiconductor chip
chips
semiconductor device
underneath
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/370,990
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US6410978B1 (en
Inventor
Akio Yasukawa
Hirohisa Yamamura
Tatsuya Shigemura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP10146906A priority Critical patent/JPH11340394A/en
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to US09/370,990 priority patent/US6410978B1/en
Assigned to HITACHI, LTD. reassignment HITACHI, LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SHIGEMURA, TATSUYA, YAMAMURA, HIROSHISA, YASUKAWA, AKIO
Publication of US20020050403A1 publication Critical patent/US20020050403A1/en
Application granted granted Critical
Publication of US6410978B1 publication Critical patent/US6410978B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components

Definitions

  • the present invention relates to a semiconductor device having a base on which a semiconductor chip is mounted.
  • the present invention is devised in order to solve the above-mentioned problem inherent to the above-mentioned prior art device, and accordingly, one object of the present invention is to provide a semiconductor device which can reduce strain caused in a solder layer joined to a semiconductor chip so as to be prevented from incurring a fatigue failure.
  • a semiconductor device comprising a base, and a semiconductor chip mounted on the base, wherein a recess is formed in the base in a part underneath the semiconductor chip.
  • FIG. 1 is a cross-sectional view illustrating a semiconductor device in an embodiment of the present invention
  • FIG. 2 is a sectional view along line A-A′ show in FIG. 1;
  • FIG. 3 is sectional view for explaining the operation of the semiconductor device shown in FIG. 1;
  • FIG. 4 is a characteristic view showing a temperature distribution in the base shown in FIG. 3.
  • a plurality of semiconductor chips 1 are joined onto an insulating substrate 2 through the intermediary of a solder layer 3 , and the insulating substrate 2 is in turn joined onto a base 4 through the intermediary of a solder layer 5 .
  • the base 4 is formed therein with recesses 4 a in a surface thereof on the side remote from the semiconductor chips in parts corresponding respectively to the chips 1 mounted thereon.
  • the base 4 is joined thereto with an intermediate board 7 for covering the recesses 4 a, by means of a blazing filler material.
  • the thickness of the brazing filler material is very thin, and accordingly, the brazing filled material is not shown in the accompanying drawings.
  • a plurality of nozzles 6 are joined to the intermediate board 7 by a brazing filler material.
  • the nozzles 6 are located respectively at positions corresponding to the recesses 4 a, respectively.
  • a outflow pipe 8 is brazed to the intermediate board 7
  • a lower board 10 to which an inflow pipe 9 is brazed is brazed to the intermediate board 7 so as to cover inflow holes in the nozzles 6 .
  • cooling liquid 11 is led into the device from the inflow pipe 9 , and then, the cooling liquid 11 flows through the nozzles 6 and impinges upon the bottoms of the recesses 4 a. Thereafter, the cooling liquid 11 flows around the nozzles 6 and is discharged from the device after flowing through the outflow pipe 8 .
  • the insulating substrate 2 is made of AlN
  • the base 4 is made of Cu or Al. With the combination of the materials having high heat-conductivity, the heat generated from the chips 1 can be effectively transmitted to the cooling liquid 11 .
  • the parts 4 b of the base underneath the chips 1 are thin, and are surrounded therearound by parts 4 c having a thickness larger than that of the parts 4 b.
  • the temperature is distributed so that it is high in the thin parts 4 b underneath the chips, but is low in the thick parts 4 c, as shown in FIG. 4 which shows a temperature distribution on a straight line passing through the center line of the chip as viewed at a plan B-B′ in FIG. 3 and from the above. Accordingly, with reference to FIG.
  • the strain can be decreased though a similar mechanism, thereby it is possible to exhibit such a technical effect and advantage that fatigue failure can be prevented.
  • the shape of the recesses 4 a are circular in a plan view as shown in FIG. 2.
  • a plurality of recesses 4 a can be formed simultaneously by drilling. Accordingly, it is possible to manufacture the device in a short time in comparison with other shapes.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)

Abstract

A semiconductor device in which fatigue failure of a solder layer underneath a semiconductor chip mounted on a base can be prevented from occurring due to repetitions of turn-on and -off of power during operation thereof, is provided, that is, a recess is formed in the base in a part underneath the semiconductor chip so as to prevent occurrence of thermal expansion in the base.

Description

    BACKGROUND OF THE INVENTION
  • 1. Filed of the Invention [0001]
  • The present invention relates to a semiconductor device having a base on which a semiconductor chip is mounted. [0002]
  • 2. Related Art [0003]
  • In a conventional semiconductor device as disclosed in Japanese Laid-Open Patent No. H10-22428, a base to which a semiconductor chip is joined, is flat. With the repetitions of turn-on and -off of power in this device during use thereof, the temperature rise is repeated in a part of the base in which the semiconductor chip is joined, and accordingly, a solder layer underneath the semiconductor chip clacks by fatigue, resulting in a problem of damage thereof. Thus, there has been a premise of solving the above-mentioned problem. [0004]
    • SUMMARY OF THE INVENTION
  • The present invention is devised in order to solve the above-mentioned problem inherent to the above-mentioned prior art device, and accordingly, one object of the present invention is to provide a semiconductor device which can reduce strain caused in a solder layer joined to a semiconductor chip so as to be prevented from incurring a fatigue failure. [0005]
  • To the end according to the present invention, there is provided a semiconductor device comprising a base, and a semiconductor chip mounted on the base, wherein a recess is formed in the base in a part underneath the semiconductor chip.[0006]
  • The present invention will be detailed in the form of a preferred embodiment with reference to the accompanying drawings in which: [0007]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view illustrating a semiconductor device in an embodiment of the present invention; [0008]
  • FIG. 2 is a sectional view along line A-A′ show in FIG. 1; [0009]
  • FIG. 3 is sectional view for explaining the operation of the semiconductor device shown in FIG. 1; and [0010]
  • FIG. 4 is a characteristic view showing a temperature distribution in the base shown in FIG. 3.[0011]
    • DESCRIPTION OF THE PREFERRED EMBODIMENT
  • Referring to FIG. 1, a plurality of [0012] semiconductor chips 1 are joined onto an insulating substrate 2 through the intermediary of a solder layer 3, and the insulating substrate 2 is in turn joined onto a base 4 through the intermediary of a solder layer 5. The base 4 is formed therein with recesses 4 a in a surface thereof on the side remote from the semiconductor chips in parts corresponding respectively to the chips 1 mounted thereon. The base 4 is joined thereto with an intermediate board 7 for covering the recesses 4 a, by means of a blazing filler material. The thickness of the brazing filler material is very thin, and accordingly, the brazing filled material is not shown in the accompanying drawings. A plurality of nozzles 6 are joined to the intermediate board 7 by a brazing filler material. The nozzles 6 are located respectively at positions corresponding to the recesses 4 a, respectively. Further, a outflow pipe 8 is brazed to the intermediate board 7, and a lower board 10 to which an inflow pipe 9 is brazed, is brazed to the intermediate board 7 so as to cover inflow holes in the nozzles 6.
  • When the device is operated so as to generate a heat from the [0013] chips 1, cooling liquid 11 is led into the device from the inflow pipe 9, and then, the cooling liquid 11 flows through the nozzles 6 and impinges upon the bottoms of the recesses 4 a. Thereafter, the cooling liquid 11 flows around the nozzles 6 and is discharged from the device after flowing through the outflow pipe 8. In this embodiment, the insulating substrate 2 is made of AlN, and the base 4 is made of Cu or Al. With the combination of the materials having high heat-conductivity, the heat generated from the chips 1 can be effectively transmitted to the cooling liquid 11.
  • Since the heat generated from the [0014] chips 1 during the operation of the device, is transmitted to the cooling liquid 11 by way of the base underneath the chips 1, the temperature of the base 4 in parts underneath the chips 1 rises up. At this time, in the conventional device, great thermal expansion occurs in the base since no recesses are formed in these parts, and accordingly, the lower parts of the insulating substrate 2 underneath the chips 1 are expanded so as to produce large strain in the solder layer 3 between the insulating substrate 2 and the chips 1. With the repetitions of turn-on and -off of power, this strain is repeatedly effected. Thus, there has been presented a problem of occurrence of fatigue failure of the soldering layer.
  • On the contrary, in the instant embodiment, since the [0015] recesses 4 a are formed in the base 4, the parts 4 b of the base underneath the chips 1 are thin, and are surrounded therearound by parts 4 c having a thickness larger than that of the parts 4b. In this arrangement, the temperature is distributed so that it is high in the thin parts 4 b underneath the chips, but is low in the thick parts 4 c, as shown in FIG. 4 which shows a temperature distribution on a straight line passing through the center line of the chip as viewed at a plan B-B′ in FIG. 3 and from the above. Accordingly, with reference to FIG. 3, even though the thin parts 4 b tend to thermally expand, the thermal expansion of the thin part 4 b are restrained by the thick parts 4 c therearound, having a low temperature. That is, restraining force 12 is effected so as to restrain expansion. Thus, it is possible to prevent occurrence of fatigue failure of the solder layer.
  • With the provision of the [0016] recesses 4 a, as to the solder layer 5 for joining the insulating substrate, the strain can be decreased though a similar mechanism, thereby it is possible to exhibit such a technical effect and advantage that fatigue failure can be prevented.
  • In this embodiment, the shape of the [0017] recesses 4 a are circular in a plan view as shown in FIG. 2. With the circular shape, a plurality of recesses 4 a can be formed simultaneously by drilling. Accordingly, it is possible to manufacture the device in a short time in comparison with other shapes.
  • With the device according to the present invention, it is possible to prevent occurrence of large strain in the solder layers, thereby it is possible to prevent occurrence of fatigue failure in the solder layers. [0018]

Claims (1)

What is claimed is:
1. A semiconductor device having a base on which a semiconductor chip is mounted, and a recess formed in said base in a part underneath said semiconductor chip.
US09/370,990 1998-05-28 1999-08-10 Semiconductor device Expired - Fee Related US6410978B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP10146906A JPH11340394A (en) 1998-05-28 1998-05-28 Semiconductor device
US09/370,990 US6410978B1 (en) 1998-05-28 1999-08-10 Semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10146906A JPH11340394A (en) 1998-05-28 1998-05-28 Semiconductor device
US09/370,990 US6410978B1 (en) 1998-05-28 1999-08-10 Semiconductor device

Publications (2)

Publication Number Publication Date
US20020050403A1 true US20020050403A1 (en) 2002-05-02
US6410978B1 US6410978B1 (en) 2002-06-25

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JP (1) JPH11340394A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070152346A1 (en) * 2005-12-30 2007-07-05 Ibm Corporation Silicon carrier having increased flexibility
US20120258573A1 (en) * 2008-12-15 2012-10-11 Industrial Technology Research Institute Fabrication method of substrate

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003051689A (en) * 2001-08-06 2003-02-21 Toshiba Corp Heating element cooling unit
DE102004026061B4 (en) * 2004-05-25 2009-09-10 Danfoss Silicon Power Gmbh Power semiconductor module and method for cooling a power semiconductor module
US7536870B2 (en) * 2006-03-30 2009-05-26 International Business Machines Corporation High power microjet cooler
US8427832B2 (en) * 2011-01-05 2013-04-23 Toyota Motor Engineering & Manufacturing North America, Inc. Cold plate assemblies and power electronics modules
DE102018211520A1 (en) * 2018-07-11 2020-01-16 Mahle International Gmbh Power electronics unit

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4920574A (en) * 1985-10-04 1990-04-24 Fujitsu Limited Cooling system for an electronic circuit device
JP3525498B2 (en) * 1994-07-13 2004-05-10 株式会社デンソー Boiling cooling device
JP3203475B2 (en) 1996-06-28 2001-08-27 株式会社日立製作所 Semiconductor device
US6140144A (en) * 1996-08-08 2000-10-31 Integrated Sensing Systems, Inc. Method for packaging microsensors

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070152346A1 (en) * 2005-12-30 2007-07-05 Ibm Corporation Silicon carrier having increased flexibility
WO2007077109A2 (en) * 2005-12-30 2007-07-12 International Business Machines Corporation Silicon carrier having increased flexibility
WO2007077109A3 (en) * 2005-12-30 2007-08-30 Ibm Silicon carrier having increased flexibility
US7345353B2 (en) 2005-12-30 2008-03-18 International Business Machines Corporation Silicon carrier having increased flexibility
US20120258573A1 (en) * 2008-12-15 2012-10-11 Industrial Technology Research Institute Fabrication method of substrate
US8763243B2 (en) * 2008-12-15 2014-07-01 Industrial Technology Research Institute Fabrication method of substrate

Also Published As

Publication number Publication date
US6410978B1 (en) 2002-06-25
JPH11340394A (en) 1999-12-10

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