US20020047950A1 - Thin film transistor for a liquid crystal display device and a fabrication process thereof - Google Patents
Thin film transistor for a liquid crystal display device and a fabrication process thereof Download PDFInfo
- Publication number
- US20020047950A1 US20020047950A1 US09/942,194 US94219401A US2002047950A1 US 20020047950 A1 US20020047950 A1 US 20020047950A1 US 94219401 A US94219401 A US 94219401A US 2002047950 A1 US2002047950 A1 US 2002047950A1
- Authority
- US
- United States
- Prior art keywords
- film
- substrate
- electrode
- gate
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 59
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims description 76
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000010408 film Substances 0.000 claims abstract description 232
- 239000000758 substrate Substances 0.000 claims abstract description 122
- 239000004020 conductor Substances 0.000 claims abstract description 113
- 239000003870 refractory metal Substances 0.000 claims abstract description 18
- 238000009413 insulation Methods 0.000 claims description 164
- 230000001681 protective effect Effects 0.000 claims description 69
- 239000004065 semiconductor Substances 0.000 claims description 44
- 238000005530 etching Methods 0.000 claims description 24
- 238000001312 dry etching Methods 0.000 claims description 21
- 239000011521 glass Substances 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 230000003287 optical effect Effects 0.000 claims description 6
- 238000004528 spin coating Methods 0.000 claims description 6
- 229910052681 coesite Inorganic materials 0.000 claims description 4
- 229910052906 cristobalite Inorganic materials 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 229910052682 stishovite Inorganic materials 0.000 claims description 4
- 229910052905 tridymite Inorganic materials 0.000 claims description 4
- 229910015844 BCl3 Inorganic materials 0.000 claims description 3
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 claims description 3
- 229910004541 SiN Inorganic materials 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims 1
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 29
- 238000010276 construction Methods 0.000 description 17
- 238000010586 diagram Methods 0.000 description 10
- 229910000838 Al alloy Inorganic materials 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 6
- 229910000542 Sc alloy Inorganic materials 0.000 description 5
- 229910000583 Nd alloy Inorganic materials 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 238000004299 exfoliation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
Definitions
- the present invention generally relates to liquid crystal display devices and more particularly to a liquid crystal display device having a thin-film transistor (TFT).
- TFT thin-film transistor
- Liquid crystal display devices are used extensively in information processing apparatuses such as a computer as a compact display device consuming little electric power.
- FIG. 1 shows the construction of a conventional active-matrix type liquid crystal display device 10 .
- the liquid crystal display device 10 includes a TFT glass substrate 11 carrying thereon a number of TFTs and corresponding transparent pixel electrodes, and a glass substrate 12 is provided on the TFT substrate 11 so as to face the TFT substrate 11 with a gap formed therebetween.
- the gap thus formed is filled by a liquid crystal layer 1 in the state that the liquid crystal layer 1 is confined between the TFT substrate 11 and the opposing substrate 12 by a seal member not illustrated.
- the direction of the liquid crystal molecules in the liquid crystal layer 1 is selectively modified by applying a drive voltage to a selected pixel electrode via a corresponding TFT.
- the liquid crystal display device 10 includes a pair of polarizers at respective outer sides of the glass substrates 11 and 12 in the crossed Nicol state, and the glass substrates 11 and 12 further carry molecular alignment films on the respective interior sides thereof in contact with the liquid crystal layer 1 .
- FIG. 2 shows a part of the TFT substrate 11 in an enlarged scale.
- the TFT substrate 11 carries thereon a number of pad electrodes 11 A for receiving a scanning signal and a number of scanning electrodes 11 a each extending from a corresponding pad electrode 11 A in a first direction. Further, the TFT substrate 11 carries thereon a number of pad electrodes 11 B for receiving an image signal and a number of signal electrodes 11 b each extending from a corresponding pad electrode 11 B in a second direction generally perpendicular to the first direction. Further, in correspondence to each intersection of a scanning electrode 11 a and a signal electrode 11 b , there is provided a TFT 11 C and a corresponding transparent pixel electrode 11 D.
- one of the scanning electrodes 11 a is selected by selectively supplying a scanning signal to the corresponding electrode pad 11 A. Further, a signal electrode 11 b is selected by supplying an image signal to the corresponding electrode pad 11 B. Thereby, the image signal is forwarded to the corresponding transparent pixel electrode 11 D via the TFT 11 C.
- FIG. 3 shows the construction of a conventional TFT 11 C.
- the TFT 11 C is constructed on a glass substrate 21 corresponding to the TFT substrate 11 of FIG. 1 and includes a gate electrode 22 formed on the glass substrate 21 in electrical connection to the scanning electrode 11 a , wherein a gate insulation film 23 provided on the glass substrate 21 covers the gate electrode 22 . Further, an amorphous silicon pattern 24 is provided on the gate insulation film 23 so as to cover the gate electrode 22 .
- the gate electrode 22 is formed of an Al—Nd alloy or an Al—Sc alloy.
- amorphous silicon pattern 24 constitutes the active region of the TFT 11 C and is covered by a channel protection pattern 25 of SiN in the part corresponding to the channel region of the TFT 11 C located immediately above the gate electrode 22 .
- the amorphous silicon pattern 24 there are provided a pair of amorphous silicon patterns 26 A and 26 B of the n + -type at both lateral sides of the channel protection pattern 25 , and the amorphous silicon pattern 26 A carries thereon a Ti layer 27 a , an Al layer 27 b and a Ti layer 27 c consecutively, wherein the layers 27 a - 27 c constitute an ohmic electrode 27 A connected to the signal electrode 11 b .
- the amorphous silicon pattern 26 B carries thereon a Ti layer 27 d , an Al layer 27 e and a Ti layer 27 f consecutively, wherein the layers 27 d - 27 f constitute an ohmic electrode 27 B.
- the ohmic electrodes 27 A and 27 B are covered by a protective film 28 of SiN, and a transparent pixel electrode 29 of In 2 SnO 5 (ITO) is provided on the protective film 28 , wherein the pixel electrode 29 makes a contact with the uppermost Ti layer 27 f of the ohmic electrode 27 B via a contact hole formed in the protective film 28 .
- ITO In 2 SnO 5
- the conduction between the ohmic electrode 27 A and the ohmic electrode 27 B via the channel region formed in the amorphous silicon pattern 24 is controlled in response to the scanning signal supplied to the gate electrode, and the pixel electrode 29 corresponding to the TFT 11 C thus turned on is selectively activated by the image signal supplied to the ohmic electrode 27 A.
- the fabrication process of the TFT 11 C of FIG. 3 includes the steps of consecutively depositing, on an amorphous silicon layer constituting the amorphous silicon patterns 26 A and 26 B, a Ti layer corresponding to the Ti layers 27 a and 27 b , an Al layer corresponding to the Al layers 27 b and 27 e , and a Ti layer corresponding to the Ti layers 27 c and 27 f , followed by a patterning process conducted on the layered structure thus obtained by a dry etching process while using an etching mask.
- the dry etching process may be conducted typically by an RIE (reactive ion etching) process that uses a mixture of Cl 2 and BCl 3 as an etching gas.
- RIE reactive ion etching
- the Al pattern 27 b or 27 e may experience a selective lateral etching at the exposed edge part of the electrode patterns 27 A and 27 B as indicated in FIG. 3.
- a selective lateral etching occurs in the Al patterns 27 b and 27 e , there inevitably occurs a problem of overhang formation at the edge part of the ohmic electrode 27 A or 27 B, wherein the existence of such an overhang structure may induce the problem of failure of electrical connection in the patterns connected to the ohmic electrode 27 A or 27 B.
- the electrical connection of the pixel electrode 29 to the ohmic electrode 27 B may suffer from such a failure at the receded side edge of the Al pattern 27 e.
- Another and more specific object of the present invention is to provide a reliable thin-film transistor for use in a liquid crystal display device of the active-matrix type.
- Another object of the present invention is to provide a fabrication process of a thin-film transistor for use in a liquid crystal display device of the active-matrix type wherein the yield of production is improved.
- Another object of the present invention is to provide a thin-film transistor having a protective insulation film covering said thin-film transistor and a pixel electrode provided on said protective insulation film in electrical connection with said thin-film transistor, comprising:
- a gate electrode provided on a substrate
- a gate insulation film provided on said substrate so as to cover said gate electrode
- a semiconductor layer provided on said gate insulation film so as to cover said gate electrode when viewed in a direction perpendicular to a principal surface of said substrate;
- a first ohmic electrode provided on said semiconductor layer so as to be located at a first side of said gate electrode when viewed in a direction perpendicular to said principal surface;
- a second ohmic electrode provided on said semiconductor layer so as to be located at a second, opposite side of said gate electrode when viewed in a direction perpendicular to said principal surface;
- said second ohmic electrode comprising:
- said second conductor film has a lateral edge corresponding to said lateral edge of said first conductor film such that said lateral edge of said second conductor film is located flush to or inside said lateral edge of said first conductor film when viewed in a direction perpendicular to said substrate.
- Another object of the present invention is to provide a thin-film transistor having a protective insulation film covering said thin-film transistor and a pixel electrode provided on said protective insulation film in electrical connection with said thin-film transistor, comprising:
- a gate electrode provided on a substrate
- a gate insulation film provided on said substrate so as to cover said gate electrode
- a semiconductor layer provided on said gate insulation film so as to cover said gate electrode when viewed in a direction perpendicular to a principal surface of said substrate;
- a first ohmic electrode provided on said semiconductor layer so as to be located at a first side of said gate electrode when viewed in a direction perpendicular to said principal surface;
- a second ohmic electrode provided on said semiconductor layer so as to be located at a second, opposite side of said gate electrode when viewed in a direction perpendicular to said principal surface;
- said gate insulation film comprising:
- a pair of insulation films disposed on said substrate at both sides of a gate structure including said gate electrode and said insulation pattern, such that said pair of insulation films have respective surfaces continuing to a surface of said insulation pattern.
- Another object of the present invention is to provide a method of fabricating a thin-film transistor, comprising the steps of:
- Another object of the present invention is to provide a method of fabricating a thin-film transistor, comprising the steps of:
- said step of forming said gate insulation film includes the steps of:
- Another object of the present invention is to provide a liquid crystal display device, comprising:
- a pixel electrode provided on said protective insulation film in electrical connection with said thin-film transistor, said thin-film transistor comprising:
- a gate electrode provided on said first substrate
- a gate insulation film provided on said first substrate so as to cover said gate electrode
- a semiconductor layer provided on said gate insulation film so as to cover said gate electrode when viewed in a direction perpendicular to a principal surface of said first substrate;
- a first ohmic electrode provided on said semiconductor layer so as to be located at a first side of said gate electrode when viewed in a direction perpendicular to said principal surface;
- a second ohmic electrode provided on said semiconductor layer so as to be located at a second, opposite side of said gate electrode when viewed in a direction perpendicular to said principal surface;
- said second ohmic electrode comprising:
- a second conductor film provided on said first conductor film, said second conductor film being covered intimately by said protective insulation film and containing Al therein, wherein said second conductor film has a lateral edge corresponding to said lateral edge of said first conductor film such that said lateral edge of said second conductor film is located flush to or inside said lateral edge of said first conductor film when viewed in a direction perpendicular to said first substrate.
- Another object of the present invention is to provide a method of fabricating a liquid crystal display device comprising: a first substrate; a second substrate facing said first substrate; a liquid crystal layer confined between said first substrate and said second substrate; a thin-film transistor provided on said first substrate; a protective insulation film covering said thin-film transistor; and a pixel electrode provided on said protective insulation film in electrical connection with said thin-film transistor, said method comprising the steps of:
- the second conductor pattern being located inside the first conductor pattern, never forms an overhang structure with respect to the adjacent first conductor pattern, and the step coverage of the protective film over the thin-film transistor is improved substantially. Associated therewith, the risk of the pixel electrode containing defect as a result of the poor step coverage of the protective insulation film is reduced substantially.
- Another object of the present invention is to provide a liquid crystal display device, comprising:
- a pixel electrode provided on said protective insulation film in electrical connection with said thin-film transistor
- said thin-film transistor comprising:
- a gate electrode provided on said first substrate
- a gate insulation film provided on said first substrate so as to cover said gate electrode
- a semiconductor layer provided on said gate insulation film so as to cover said gate electrode when viewed in a direction perpendicular to a principal surface of said first substrate;
- a first ohmic electrode provided on said semiconductor layer so as to be located at a first side of said gate electrode when viewed in a direction perpendicular to said principal surface;
- a second ohmic electrode provided on said semiconductor layer so as to be located at a second, opposite side of said gate electrode when viewed in a direction perpendicular to said principal surface;
- said gate insulation film comprising:
- a pair of insulation films disposed on said first substrate at both sides of a gate structure including said gate electrode and said insulation pattern, such that said pair of insulation films have respective surfaces continuing to a surface of said insulation pattern.
- Another object of the present invention is to provide a method of fabricating a liquid crystal display device comprising: a first substrate; a second substrate facing said first substrate; a liquid crystal layer confined between said first substrate and said second substrate; a thin-film transistor provided on said first substrate; a protective insulation film covering said thin-film transistor; and a pixel electrode provided on said protective insulation film in electrical connection with said thin-film transistor, said method comprising the steps of:
- step of forming said gate insulation film includes the steps of:
- the gate electrode being covered by the insulation pattern at a top part thereof, is effectively protected from contamination even in such a case in which the foregoing pair of insulation films are formed at both sides of the gate structure by a spin coating process of an organic insulation film.
- an effective planarization is achieved for the gate structure.
- FIG. 1 is a diagram showing the general construction of a conventional liquid crystal display device
- FIG. 2 is a diagram showing a TFT array formed on a glass substrate in the liquid crystal display device of FIG. 1;
- FIG. 3 is a diagram showing the construction of a conventional TFT
- FIG. 4 is a diagram showing the construction of a TFT according to a first embodiment of the present invention.
- FIGS. 5 A- 5 E are diagrams showing the fabrication process of the TFT of FIG. 4;
- FIG. 6 is a diagram showing the construction of a TFT according to a second embodiment of the present invention.
- FIGS. 7 A- 7 E are diagrams showing the fabrication process of a TFT according to a third embodiment of the present invention.
- FIGS. 8 A- 8 E are diagrams showing the fabrication process of a TFT according to a fourth embodiment of the present invention.
- FIG. 4 shows the construction of a TFT 30 according to a first embodiment of the present invention, wherein the TFT 30 may be used in the liquid crystal display device 11 of FIGS. 1 and 2 in place of the TFT 11 C.
- the TFT 30 may be used in the liquid crystal display device 11 of FIGS. 1 and 2 in place of the TFT 11 C.
- those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
- the TFT 30 has a construction similar to that of the TFT 11 C except that the ohmic electrode 27 A or ohmic electrode 27 B, in which the conductor layers 27 a - 27 c or 27 d - 27 f are stacked consecutively, is replaced with an ohmic electrode 37 A or ohmic electrode 37 B, wherein the ohmic electrode 37 A includes a stacking of only the conductor layer 27 a of Ti and the conductor layer 27 b of Al or an Al alloy. Similarly, the ohmic electrode 37 B includes a stacking of only the conductor layer 27 d of Ti and the conductor layer 27 e of Al or an Al alloy.
- the conductor layer 27 a or 27 d of Ti acts as a barrier metal layer prohibiting the reaction between the conductor layer 27 b or 27 e containing Al therein and the amorphous silicon pattern 26 A or 26 B underneath the barrier metal layer.
- the conductor layer 27 a has a lateral edge at a position flush to or receded from a corresponding lateral edge of the n + type amorphous silicon pattern 26 A underneath the conductor layer 27 a . Further, the conductor layer 27 b on the conductor layer 27 a has a lateral edge further receded from the lateral edge of the conductor layer 27 a .
- the conductor layer 27 d has a lateral edge flush to or receded from a corresponding lateral edge of the n + -type amorphous silicon pattern 26 B underneath the conductor layer 27 d
- the conductor layer 27 e on the conductor layer 27 d has a lateral edge further receded from the lateral edge of the conductor layer 27 d
- the protective insulation film 28 is provided on the structure of FIG. 4 so as to cover the ohmic electrodes 37 A and 37 B so as to make a direct contact with the conductor layer 27 b or 27 e.
- the step coverage of the protective insulation film 28 over the ohmic electrode 37 A or 37 B is improved substantially, even when the protective insulation film 28 is formed by a sputtering process of SiN.
- the protective insulation film 28 has a gently inclined surface, and thus, the transparent pixel electrode 29 of ITO covers the protective insulation film 28 with a generally uniform thickness.
- the problem of disconnection of the transparent pixel electrode 29 which tends to occur when the protective insulation film 28 has a steeply inclined surface, is effectively eliminated.
- the protective insulation film 28 is formed with a contact hole exposing the conductor layer 27 e of the ohmic electrode 37 B and a Ti barrier pattern 29 A is provided on the protective insulation film 28 in contact with the exposed conductor layer 27 e at the foregoing contact hole.
- the transparent pixel electrode 29 is connected to the ohmic electrode 37 B at the foregoing contact hole via the Ti barrier pattern 29 A.
- the Ti barrier pattern 29 A may be formed with a thickness of about 30 nm or less, for allowing a passage of optical beam.
- FIGS. 5 A- 5 E show a fabrication process of the TFT 30 .
- the gate electrode 22 typically of Al or an Al alloy is formed on the glass substrate 21 by a PVD process such as a sputtering process, and the gate insulation film 23 is provided in the step of FIG. 5B such that the gate insulation film 23 covers the gate electrode 22 .
- a PVD process such as a sputtering process
- a layer 24 M of amorphous silicon of either the p-type, undoped or n-type is formed further on the gate insulation film 23 by a CVD process with a thickness of about 30 nm, as the active layer of the TFT 30 .
- the protective pattern 25 of SiO 2 , SiN or SiON is formed on the amorphous silicon layer 24 M by a plasma CVD process with a thickness of about 120 nm, wherein the protective pattern 25 is provided in correspondence to the gate electrode 22 and acts as a protective pattern protecting the channel region of the TFT 30 formed in the amorphous silicon layer 24 M.
- an amorphous silicon layer 26 M of the n + -type is formed on the amorphous silicon layer 24 M so as to cover the channel protective pattern 25 with a generally uniform thickness, and a Ti layer 27 M and a conductor layer 28 M of Al or an Al alloy are deposited consecutively on the amorphous silicon layer 26 M by a PVD process.
- a dry etching process is applied to the structure of FIG. 5B by using a mixture of Cl 2 and BCl 3 as an etching gas, to conduct a patterning of the layers 24 M- 28 M simultaneously, wherein the foregoing amorphous silicon pattern 24 , the doped amorphous silicon patterns 26 A and 26 B, and the ohmic electrodes 37 A and 37 B further thereon are formed substantially simultaneously.
- the concentration of Cl 2 in the etching gas is preferably set to be 40% or more, for setting the lateral etching rate of the Ti layer 27 M, and hence the lateral etching rate of the Ti patterns 27 a and 27 d , to be equal to or larger than lateral etching rate of the amorphous silicon layers 24 M or 26 M, and hence the lateral etching rate of the amorphous silicon pattern 24 or the amorphous silicon patterns 26 A and 26 B.
- a protective insulation film 28 of SiN is provided on the structure of FIG. 5C by a plasma CVD process and a contact hole 28 A is formed in the protective insulation film 28 thus formed such that the contact hole 28 A exposes the conductor pattern 27 e of the ohmic electrode 37 B.
- the Ti pattern 29 A is provided in the step of FIG. 5E with a thickness of less than about 30 nm, preferably about 20 nm, such that the Ti pattern 29 A makes a contact with the exposed conductor pattern 27 e at the contact hole 28 A.
- the lateral etching rate is controlled in the dry etching step of FIG. 5C such that the lateral etching rate increases consecutively from the lowermost level patterns 26 A and 26 B to the uppermost level patterns 27 b and 27 e .
- the lateral etching rate increases consecutively from the lowermost level patterns 26 A and 26 B to the uppermost level patterns 27 b and 27 e .
- the present embodiment provides an advantageous feature of suppressing the increase of resistance of the pixel electrode 29 , by interposing the Ti pattern 29 A between the pixel electrode 29 and the conductor pattern 27 e.
- FIG. 6 shows the construction of a TFT 40 according to a second embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
- the TFT 40 has a construction similar to that of the TFT 30 except that the Ti pattern 29 A is now omitted and a pixel electrode 39 of Ti is provided in direct contact with the conductor layer 27 e of the ohmic electrode 27 B, in place of the ITO pixel electrode 29 .
- the thickness of the Ti pixel electrode 39 is about 30 nm or less, it is possible to secure a sufficient optical transparency for the pixel electrode 39 .
- the step of formation of the Ti pattern 29 A is omitted and the fabrication process of the liquid crystal display device including the TFT 40 is substantially facilitated.
- TFT 40 As other features of the TFT 40 are identical with those of the TFT 30 , further description of the TFT 40 will be omitted.
- the gate insulation film 23 is generally formed of SiN, wherein the tendency of an SiN film to accumulate stress therein is well known in the art.
- the SiN film constituting the gate insulation film 23 may cause an exfoliation.
- the gate insulation film 23 thus formed of SiN tends to form a projection on the surface thereof in conformity with the shape of the gate electrode 22 . In such a case, it becomes difficult to form the TFT on the gate insulation film 23 because of the existence of the projection.
- FIGS. 7 A- 7 E are diagrams showing the fabrication process of TFT 30 or 40 conducted such that the gate insulation film 23 has a planarized surface.
- a conductor layer 22 M of an Al—Nd alloy or an Al—Sc alloy is deposited on the glass substrate 21 by a PVD process, followed by a formation of a resist pattern in conformity with the shape of the gate electrode 22 to be formed.
- the conductor layer 22 M is patterned while using the resist pattern as a mask, to form the gate electrode 22 .
- an SOG (spin-on-glass) layer 23 1 is deposited on the glass substrate 21 in the step of FIG. 7C such that the SOG layer 23 1 covers the gate electrode 22 .
- the SOG layer 23 1 is subjected to a sintering to form a solidified layer, followed by an etch back process conducted by using a buffered HF solution as an etchant, until the gate electrode 22 is exposed.
- a buffered HF solution as an etchant
- an SiN film 23 2 is deposited on the structure of FIG. 7D by a plasma CVD process, and the amorphous silicon layer 24 and the channel protective pattern 25 are formed on the SiN film 23 2 by a plasma CVD process.
- the TFT 30 or 40 is formed.
- the foregoing SOG regions ( 23 1 )A and ( 23 1 )B constitute the gate insulation film 23 together with the SiN film 232 .
- the gate insulation film 23 is formed with a planarized top surface.
- the structure of FIG. 7E using SiN for the upper layer 23 2 of the gate insulation film 23 , cannot avoid the problem of accumulation of stress in the gate insulation film 23 .
- the structure of FIG. 7E tends to cause the problem of warp in the TFT substrate 11 on which the TFTs of FIG. 7E are formed.
- there is a substantial risk because of the stress in the gate insulation film 23 , in that a part of the upper layer 23 2 may cause exfoliation and produce a dust. When such dust is formed, there is a substantial risk that the endurance voltage of the TFT may be degraded.
- the surface of the gate electrode 22 is covered by the SOG film 23 1 , while such a process tends to induce an oxidation at the surface of the gate electrode 22 .
- the threshold voltage of the TFT is inevitably changed.
- FIGS. 8 A- 8 E are diagrams showing the fabrication process of the TFT according to a fourth embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
- the glass substrate 21 is covered consecutively by a conductor layer 22 M of an Al—Nd ally or an Al—Sc alloy and an SiN layer 23 M, respectively with a thickness of about 500 nm and about 300 nm, wherein the conductor layer 22 M may be deposited by a PVD process while the SiN layer 23 M may be deposited by a plasma CVD process. Further, a resist pattern is formed on the SiN film 23 M in correspondence to the gate electrode 22 to be formed.
- the SiN layer 23 M and the conductor layer 22 are subjected to a patterning process while using the resist pattern as a mask, to form the gate electrode 22 such that the gate electrode 22 is covered by an SiN pattern 23 A.
- an SOG layer 23 1 is formed on the structure of FIG. 8B with a thickness of about 800 nm by a spin-coating process, such that the SOG layer 23 1 covers the SiN pattern 23 A. After the formation, the SOG layer 23 1 is subjected to a sintering process.
- the SOG layer 23 1 thus sintered is subjected to an etch back process conducted by a wet etching process while using a buffered HF solution for the etchant, until the SiN pattern 23 A is exposed.
- SOG regions ( 23 1 )A and ( 23 1 )B are formed on the substrate 21 at both lateral sides of the gate structure, which is formed by the gate electrode 22 and the SiN pattern 23 thereon, with a thickness of about 800 nm.
- a thin SiN film 23 2 is deposited on the structure of FIG. 8D by a plasma CVD process with a thickness of about 100 nm, followed by a deposition of an amorphous silicon layer 24 M further on the SiN film 23 2 with a thickness of about 30 nm.
- a channel protective film 25 is formed on the amorphous silicon layer 24 M with a thickness of about 120 nm. Furthermore, the steps of FIGS. 5 B- 5 E are conducted on the structure of FIG. 8E, and the TFT 30 or 40 having the construction described previously are obtained. It should be noted that the TFT 30 or 40 fabricated according to such a process includes the SOG regions ( 23 1 )A and ( 23 1 )B as a part of the gate insulation film 23 together with the SiN film 23 2 .
- the problem of stress accumulation in the TFT substrate 11 caused by the gate insulation film 23 is successfully avoided by reducing the thickness of the SiN film 23 2 .
- the conductor layer 22 M, used for the gate electrode 22 is covered immediately by the SiN layer 23 after the formation thereof in the present embodiment, the problem of the top surface of the gate electrode 22 being contaminated by the organic material from the SOG film is effectively eliminated. Thereby, the problem of increase of the gate resistance as a result of use of SOG is eliminated.
- the gate insulation film 23 is primarily formed by the SOG, the gate insulation film 23 has a highly planarized surface and the construction of a TFT on such a planarized gate insulation film is substantially facilitated.
- the conductor patterns 27 a , 27 d or 29 A are by no means limited to a Ti pattern but a pattern of other refractory metals such as Ta, Mo, W, and the like, may also be used.
- the gate electrode 22 is by no means limited to an Al—Nd alloy or Al—Sc alloy but a refractory metal element such as W, Ta, Cr or Ti may also be used.
- a refractory metal element such as W, Ta, Cr or Ti may also be used.
- the use of Al—Nd alloy or Al—Sc alloy is preferable, though, because of the low electrical resistance and resistance against hillock.
- the channel protection film 25 may be formed by SiO 2 or SiON.
Landscapes
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Ceramic Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Optics & Photonics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
- The present invention generally relates to liquid crystal display devices and more particularly to a liquid crystal display device having a thin-film transistor (TFT).
- Liquid crystal display devices are used extensively in information processing apparatuses such as a computer as a compact display device consuming little electric power.
- In order to realize a high-quality color representation, recent liquid crystal display devices tend to use a so-called active-matrix driving method, in which each of the pixel electrodes in the liquid crystal display device is turned on and off by a corresponding TFT that is provided on a glass substrate constituting the liquid crystal display device in correspondence to the pixel electrode.
- FIG. 1 shows the construction of a conventional active-matrix type liquid
crystal display device 10. - Referring to FIG. 1, the liquid
crystal display device 10 includes a TFT glass substrate 11 carrying thereon a number of TFTs and corresponding transparent pixel electrodes, and aglass substrate 12 is provided on the TFT substrate 11 so as to face the TFT substrate 11 with a gap formed therebetween. The gap thus formed is filled by a liquid crystal layer 1 in the state that the liquid crystal layer 1 is confined between the TFT substrate 11 and theopposing substrate 12 by a seal member not illustrated. - In the conventional liquid
crystal display device 10 of the foregoing construction, the direction of the liquid crystal molecules in the liquid crystal layer 1 is selectively modified by applying a drive voltage to a selected pixel electrode via a corresponding TFT. - Further, it should be noted that the liquid
crystal display device 10 includes a pair of polarizers at respective outer sides of theglass substrates 11 and 12 in the crossed Nicol state, and theglass substrates 11 and 12 further carry molecular alignment films on the respective interior sides thereof in contact with the liquid crystal layer 1. - FIG. 2 shows a part of the TFT substrate11 in an enlarged scale.
- Referring to FIG. 2, the TFT substrate11 carries thereon a number of pad electrodes 11A for receiving a scanning signal and a number of scanning electrodes 11 a each extending from a corresponding pad electrode 11A in a first direction. Further, the TFT substrate 11 carries thereon a number of
pad electrodes 11B for receiving an image signal and a number of signal electrodes 11 b each extending from acorresponding pad electrode 11B in a second direction generally perpendicular to the first direction. Further, in correspondence to each intersection of a scanning electrode 11 a and a signal electrode 11 b, there is provided a TFT 11C and a corresponding transparent pixel electrode 11D. - In the liquid
crystal display device 10 of the foregoing construction, one of the scanning electrodes 11 a is selected by selectively supplying a scanning signal to the corresponding electrode pad 11A. Further, a signal electrode 11 b is selected by supplying an image signal to thecorresponding electrode pad 11B. Thereby, the image signal is forwarded to the corresponding transparent pixel electrode 11D via the TFT 11C. - FIG. 3 shows the construction of a conventional TFT11C.
- Referring to FIG. 3, the TFT11C is constructed on a
glass substrate 21 corresponding to the TFT substrate 11 of FIG. 1 and includes agate electrode 22 formed on theglass substrate 21 in electrical connection to the scanning electrode 11 a, wherein agate insulation film 23 provided on theglass substrate 21 covers thegate electrode 22. Further, anamorphous silicon pattern 24 is provided on thegate insulation film 23 so as to cover thegate electrode 22. Typically, thegate electrode 22 is formed of an Al—Nd alloy or an Al—Sc alloy. - It should be noted that the foregoing
amorphous silicon pattern 24 constitutes the active region of the TFT 11C and is covered by achannel protection pattern 25 of SiN in the part corresponding to the channel region of the TFT 11C located immediately above thegate electrode 22. - On the
amorphous silicon pattern 24, there are provided a pair ofamorphous silicon patterns channel protection pattern 25, and theamorphous silicon pattern 26A carries thereon aTi layer 27 a, anAl layer 27 b and aTi layer 27 c consecutively, wherein the layers 27 a-27 c constitute anohmic electrode 27A connected to the signal electrode 11 b. Similarly, theamorphous silicon pattern 26B carries thereon aTi layer 27 d, anAl layer 27 e and aTi layer 27 f consecutively, wherein thelayers 27 d-27 f constitute anohmic electrode 27B. - It should be noted that the
ohmic electrodes protective film 28 of SiN, and atransparent pixel electrode 29 of In2SnO5 (ITO) is provided on theprotective film 28, wherein thepixel electrode 29 makes a contact with theuppermost Ti layer 27 f of theohmic electrode 27B via a contact hole formed in theprotective film 28. - In the TFT11C having such a construction, it should be noted that the conduction between the
ohmic electrode 27A and theohmic electrode 27B via the channel region formed in theamorphous silicon pattern 24 is controlled in response to the scanning signal supplied to the gate electrode, and thepixel electrode 29 corresponding to the TFT 11C thus turned on is selectively activated by the image signal supplied to theohmic electrode 27A. - It should be noted that the fabrication process of the TFT11C of FIG. 3 includes the steps of consecutively depositing, on an amorphous silicon layer constituting the
amorphous silicon patterns Ti layers Al layers Ti layers amorphous silicon patterns electrode patterns amorphous silicon pattern 24 substantially simultaneously. - In such a fabrication process of the TFT11C, it should be noted that the
Al pattern electrode patterns Al patterns ohmic electrode ohmic electrode pixel electrode 29 to theohmic electrode 27B may suffer from such a failure at the receded side edge of theAl pattern 27 e. - While it is possible to suppress the overhang formation in the foregoing dry etching process by enhancing the anisotropy of the etching process, such a highly anisotropic dry etching process is also disadvantageous in eliminating the electrical connection failure, as a vertical side edge of the
ohmic electrodes pixel electrode 29 extending across the vertical side edge. - Accordingly, it is a general object of the present invention to provide a novel and useful thin-film transistor, liquid crystal display device using such a thin-film transistor and a fabrication process thereof wherein the foregoing problems are eliminated.
- Another and more specific object of the present invention is to provide a reliable thin-film transistor for use in a liquid crystal display device of the active-matrix type.
- Another object of the present invention is to provide a fabrication process of a thin-film transistor for use in a liquid crystal display device of the active-matrix type wherein the yield of production is improved.
- Another object of the present invention is to provide a thin-film transistor having a protective insulation film covering said thin-film transistor and a pixel electrode provided on said protective insulation film in electrical connection with said thin-film transistor, comprising:
- a gate electrode provided on a substrate;
- a gate insulation film provided on said substrate so as to cover said gate electrode;
- a semiconductor layer provided on said gate insulation film so as to cover said gate electrode when viewed in a direction perpendicular to a principal surface of said substrate;
- a first ohmic electrode provided on said semiconductor layer so as to be located at a first side of said gate electrode when viewed in a direction perpendicular to said principal surface;
- a second ohmic electrode provided on said semiconductor layer so as to be located at a second, opposite side of said gate electrode when viewed in a direction perpendicular to said principal surface;
- said second ohmic electrode comprising:
- a first conductor film containing a refractory metal element, said first conductor film having a lateral edge; and
- a second conductor film provided on said first conductor film, said second conductor film being covered intimately by said protective insulation film and containing Al therein,
- wherein said second conductor film has a lateral edge corresponding to said lateral edge of said first conductor film such that said lateral edge of said second conductor film is located flush to or inside said lateral edge of said first conductor film when viewed in a direction perpendicular to said substrate.
- Another object of the present invention is to provide a thin-film transistor having a protective insulation film covering said thin-film transistor and a pixel electrode provided on said protective insulation film in electrical connection with said thin-film transistor, comprising:
- a gate electrode provided on a substrate;
- a gate insulation film provided on said substrate so as to cover said gate electrode;
- a semiconductor layer provided on said gate insulation film so as to cover said gate electrode when viewed in a direction perpendicular to a principal surface of said substrate;
- a first ohmic electrode provided on said semiconductor layer so as to be located at a first side of said gate electrode when viewed in a direction perpendicular to said principal surface;
- a second ohmic electrode provided on said semiconductor layer so as to be located at a second, opposite side of said gate electrode when viewed in a direction perpendicular to said principal surface;
- said gate insulation film comprising:
- an insulation pattern formed on said gate electrode; and
- a pair of insulation films disposed on said substrate at both sides of a gate structure including said gate electrode and said insulation pattern, such that said pair of insulation films have respective surfaces continuing to a surface of said insulation pattern.
- Another object of the present invention is to provide a method of fabricating a thin-film transistor, comprising the steps of:
- forming a gate electrode on a substrate;
- forming a gate insulation film on said substrate so as to cover said gate electrode;
- forming a semiconductor film on said gate insulation film;
- forming an electrode layer on said semiconductor film by depositing a first conductor layer containing a refractory metal element and a second conductor layer containing Al consecutively;
- applying a dry etching process to said electrode layer to form a first ohmic electrode pattern located at a first side of said gate electrode and a second ohmic electrode pattern located at a second, opposite side of said gate electrode;
- covering said first and second ohmic electrode patterns by a protective insulation film such that said protective insulation film contacts each of said first and second ohmic electrode patterns intimately;
- forming a contact hole in said protective insulation film so as to expose said second conductor layer at said contact hole; and
- forming a pixel electrode on said protective insulation film to as to achieve an electrical contact with said second ohmic electrode pattern at said contact hole.
- Another object of the present invention is to provide a method of fabricating a thin-film transistor, comprising the steps of:
- forming said gate electrode on a substrate;
- forming a gate insulation film on said substrate so as to cover said gate electrode;
- forming a semiconductor film on said gate insulation film;
- forming an electrode layer on said semiconductor film by depositing a first conductor layer containing a refractory metal element and a second conductor layer containing Al consecutively;
- applying a dry etching process to said electrode layer to form a first ohmic electrode pattern located at a first side of said gate electrode and a second ohmic electrode pattern located at a second, opposite side of said gate electrode;
- wherein said step of forming said gate insulation film includes the steps of:
- forming an insulation pattern on said gate electrode with a shape in conformity with a shape of said gate electrode to form a gate structure;
- forming a planarizing insulation film on said first substrate by a spin-coating process, such that said planarizing insulation film covers said gate structure; and
- etching back said planarizing insulation film.
- Another object of the present invention is to provide a liquid crystal display device, comprising:
- a first substrate;
- a second substrate facing said first substrate;
- a liquid crystal layer confined between said first substrate and said second substrate;
- a thin-film transistor provided on said first substrate;
- a protective insulation film covering said thin-film transistor; and
- a pixel electrode provided on said protective insulation film in electrical connection with said thin-film transistor, said thin-film transistor comprising:
- a gate electrode provided on said first substrate;
- a gate insulation film provided on said first substrate so as to cover said gate electrode;
- a semiconductor layer provided on said gate insulation film so as to cover said gate electrode when viewed in a direction perpendicular to a principal surface of said first substrate;
- a first ohmic electrode provided on said semiconductor layer so as to be located at a first side of said gate electrode when viewed in a direction perpendicular to said principal surface;
- a second ohmic electrode provided on said semiconductor layer so as to be located at a second, opposite side of said gate electrode when viewed in a direction perpendicular to said principal surface;
- said second ohmic electrode comprising:
- a first conductor film containing a refractory metal element, said first conductor film having-a lateral edge; and
- a second conductor film provided on said first conductor film, said second conductor film being covered intimately by said protective insulation film and containing Al therein, wherein said second conductor film has a lateral edge corresponding to said lateral edge of said first conductor film such that said lateral edge of said second conductor film is located flush to or inside said lateral edge of said first conductor film when viewed in a direction perpendicular to said first substrate.
- Another object of the present invention is to provide a method of fabricating a liquid crystal display device comprising: a first substrate; a second substrate facing said first substrate; a liquid crystal layer confined between said first substrate and said second substrate; a thin-film transistor provided on said first substrate; a protective insulation film covering said thin-film transistor; and a pixel electrode provided on said protective insulation film in electrical connection with said thin-film transistor, said method comprising the steps of:
- forming said gate electrode on said first substrate;
- forming a gate insulation film on said first substrate so as to cover said gate electrode;
- forming said semiconductor film on said gate insulation film;
- forming an electrode layer on said semiconductor film by depositing a first conductor layer containing a refractory metal element and a second conductor layer containing Al consecutively;
- applying a dry etching process to said electrode layer to form a first ohmic electrode pattern located at a first side of said gate electrode and a second ohmic electrode pattern located at a second, opposite side of said gate electrode;
- covering said first and second ohmic electrode patterns by said protective insulation film such that said protective insulation film contacts each of said first and second ohmic electrode patterns intimately;
- forming a contact hole in said protective insulation film so as to expose said second conductor layer at said contact hole; and
- forming said pixel electrode on said protective insulation film to as to achieve an electrical contact with said second ohmic electrode pattern at said contact hole.
- According to the present invention, the second conductor pattern, being located inside the first conductor pattern, never forms an overhang structure with respect to the adjacent first conductor pattern, and the step coverage of the protective film over the thin-film transistor is improved substantially. Associated therewith, the risk of the pixel electrode containing defect as a result of the poor step coverage of the protective insulation film is reduced substantially.
- Another object of the present invention is to provide a liquid crystal display device, comprising:
- a first substrate;
- a second substrate facing said first substrate;
- a liquid crystal layer confined between said first substrate and said second substrate;
- a thin-film transistor provided on said first substrate;
- a protective insulation film covering said thin-film transistor; and
- a pixel electrode provided on said protective insulation film in electrical connection with said thin-film transistor,
- said thin-film transistor comprising:
- a gate electrode provided on said first substrate;
- a gate insulation film provided on said first substrate so as to cover said gate electrode;
- a semiconductor layer provided on said gate insulation film so as to cover said gate electrode when viewed in a direction perpendicular to a principal surface of said first substrate;
- a first ohmic electrode provided on said semiconductor layer so as to be located at a first side of said gate electrode when viewed in a direction perpendicular to said principal surface;
- a second ohmic electrode provided on said semiconductor layer so as to be located at a second, opposite side of said gate electrode when viewed in a direction perpendicular to said principal surface;
- said gate insulation film comprising:
- an insulation pattern formed on said gate electrode; and
- a pair of insulation films disposed on said first substrate at both sides of a gate structure including said gate electrode and said insulation pattern, such that said pair of insulation films have respective surfaces continuing to a surface of said insulation pattern.
- Another object of the present invention is to provide a method of fabricating a liquid crystal display device comprising: a first substrate; a second substrate facing said first substrate; a liquid crystal layer confined between said first substrate and said second substrate; a thin-film transistor provided on said first substrate; a protective insulation film covering said thin-film transistor; and a pixel electrode provided on said protective insulation film in electrical connection with said thin-film transistor, said method comprising the steps of:
- forming said gate electrode on said first substrate;
- forming a gate insulation film on said first substrate so as to cover said gate electrode;
- forming said semiconductor film on said gate insulation film;
- forming an electrode layer on said semiconductor film by depositing a first conductor layer containing a refractory metal element and a second conductor layer containing Al consecutively;
- applying a dry etching process to said electrode layer to form a first ohmic electrode pattern located at a first side of said gate electrode and a second ohmic electrode pattern located at a second, opposite side of said gate electrode;
- wherein said step of forming said gate insulation film includes the steps of:
- forming an insulation pattern on said gate electrode with a shape in conformity with a shape of said gate electrode to form a gate structure;
- forming a planarizing insulation film on said first substrate by a spin-coating process, such that said planarizing insulation film covers said gate structure; and
- etching back said planarizing insulation film.
- According to the present invention, the gate electrode, being covered by the insulation pattern at a top part thereof, is effectively protected from contamination even in such a case in which the foregoing pair of insulation films are formed at both sides of the gate structure by a spin coating process of an organic insulation film. By providing the organic insulation film as noted above at both sides of the gate electrode, an effective planarization is achieved for the gate structure.
- Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.
- FIG. 1 is a diagram showing the general construction of a conventional liquid crystal display device;
- FIG. 2 is a diagram showing a TFT array formed on a glass substrate in the liquid crystal display device of FIG. 1;
- FIG. 3 is a diagram showing the construction of a conventional TFT;
- FIG. 4 is a diagram showing the construction of a TFT according to a first embodiment of the present invention;
- FIGS.5A-5E are diagrams showing the fabrication process of the TFT of FIG. 4;
- FIG. 6 is a diagram showing the construction of a TFT according to a second embodiment of the present invention;
- FIGS.7A-7E are diagrams showing the fabrication process of a TFT according to a third embodiment of the present invention; and
- FIGS.8A-8E are diagrams showing the fabrication process of a TFT according to a fourth embodiment of the present invention.
- [FIRST EMBODIMENT]
- FIG. 4 shows the construction of a
TFT 30 according to a first embodiment of the present invention, wherein theTFT 30 may be used in the liquid crystal display device 11 of FIGS. 1 and 2 in place of the TFT 11C. In FIG. 4, those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted. - Referring to FIG. 4, the
TFT 30 has a construction similar to that of the TFT 11C except that theohmic electrode 27A orohmic electrode 27B, in which the conductor layers 27 a-27 c or 27 d-27 f are stacked consecutively, is replaced with anohmic electrode 37A orohmic electrode 37B, wherein theohmic electrode 37A includes a stacking of only theconductor layer 27 a of Ti and theconductor layer 27 b of Al or an Al alloy. Similarly, theohmic electrode 37B includes a stacking of only theconductor layer 27 d of Ti and theconductor layer 27 e of Al or an Al alloy. Here, it should be noted that theconductor layer conductor layer amorphous silicon pattern - As can be seen in FIG. 4, the
conductor layer 27 a has a lateral edge at a position flush to or receded from a corresponding lateral edge of the n+ typeamorphous silicon pattern 26A underneath theconductor layer 27 a. Further, theconductor layer 27 b on theconductor layer 27 a has a lateral edge further receded from the lateral edge of theconductor layer 27 a. Similarly, theconductor layer 27 d has a lateral edge flush to or receded from a corresponding lateral edge of the n+-typeamorphous silicon pattern 26B underneath theconductor layer 27 d, and theconductor layer 27 e on theconductor layer 27 d has a lateral edge further receded from the lateral edge of theconductor layer 27 d. Further, theprotective insulation film 28 is provided on the structure of FIG. 4 so as to cover theohmic electrodes conductor layer - According to the construction as noted above, it should be noted that the step coverage of the
protective insulation film 28 over theohmic electrode protective insulation film 28 is formed by a sputtering process of SiN. As a result of the improved step coverage, theprotective insulation film 28 has a gently inclined surface, and thus, thetransparent pixel electrode 29 of ITO covers theprotective insulation film 28 with a generally uniform thickness. Thereby, the problem of disconnection of thetransparent pixel electrode 29, which tends to occur when theprotective insulation film 28 has a steeply inclined surface, is effectively eliminated. - It should be noted that the
protective insulation film 28 is formed with a contact hole exposing theconductor layer 27 e of theohmic electrode 37B and aTi barrier pattern 29A is provided on theprotective insulation film 28 in contact with the exposedconductor layer 27 e at the foregoing contact hole. Thereby, thetransparent pixel electrode 29 is connected to theohmic electrode 37B at the foregoing contact hole via theTi barrier pattern 29A. By interposing theTi pattern 29A between theITO pixel electrode 29 and theconductor layer 27 e of Al or an Al alloy, the problem of increase of the resistance, which tends to occur when theITO pixel electrode 29 contacts directly with theconductor layer 27 e, is effectively avoided. - In order to minimize the optical loss of the liquid crystal display device11, it is preferable to form the foregoing
Ti barrier pattern 29A within the active region of the TFT formed by theamorphous silicon pattern 24. Alternatively, theTi barrier pattern 29A may be formed with a thickness of about 30 nm or less, for allowing a passage of optical beam. - FIGS.5A-5E show a fabrication process of the TFT30.
- Referring to FIG. 5A, the
gate electrode 22 typically of Al or an Al alloy is formed on theglass substrate 21 by a PVD process such as a sputtering process, and thegate insulation film 23 is provided in the step of FIG. 5B such that thegate insulation film 23 covers thegate electrode 22. The detailed process of forming thegate insulation film 23 will be described later with reference to another embodiment. - In the step of FIG. 5B, a
layer 24M of amorphous silicon of either the p-type, undoped or n-type, is formed further on thegate insulation film 23 by a CVD process with a thickness of about 30 nm, as the active layer of theTFT 30. In addition, theprotective pattern 25 of SiO2, SiN or SiON is formed on theamorphous silicon layer 24M by a plasma CVD process with a thickness of about 120 nm, wherein theprotective pattern 25 is provided in correspondence to thegate electrode 22 and acts as a protective pattern protecting the channel region of theTFT 30 formed in theamorphous silicon layer 24M. - Next, in the step of FIG. 5B, an
amorphous silicon layer 26M of the n+-type is formed on theamorphous silicon layer 24M so as to cover the channelprotective pattern 25 with a generally uniform thickness, and aTi layer 27M and aconductor layer 28M of Al or an Al alloy are deposited consecutively on theamorphous silicon layer 26M by a PVD process. - Next, in the step of FIG. 5C, a dry etching process is applied to the structure of FIG. 5B by using a mixture of Cl2 and BCl3 as an etching gas, to conduct a patterning of the
layers 24M-28M simultaneously, wherein the foregoingamorphous silicon pattern 24, the dopedamorphous silicon patterns ohmic electrodes - During the dry etching process of FIG. 5C, the concentration of Cl2 in the etching gas is preferably set to be 40% or more, for setting the lateral etching rate of the
Ti layer 27M, and hence the lateral etching rate of theTi patterns amorphous silicon pattern 24 or theamorphous silicon patterns layer 28M of Al or an Al alloy, and hence the lateral etching rate of theconductor patterns Ti patterns - Next, in the step of FIG. 5D, a
protective insulation film 28 of SiN is provided on the structure of FIG. 5C by a plasma CVD process and acontact hole 28A is formed in theprotective insulation film 28 thus formed such that thecontact hole 28A exposes theconductor pattern 27 e of theohmic electrode 37B. - Further, the
Ti pattern 29A is provided in the step of FIG. 5E with a thickness of less than about 30 nm, preferably about 20 nm, such that theTi pattern 29A makes a contact with the exposedconductor pattern 27 e at thecontact hole 28A. - By providing the
transparent pixel electrode 29 on the structure of FIG. 5E thus obtained, the fabrication of theTFT 30 is completed. - As explained before, the lateral etching rate is controlled in the dry etching step of FIG. 5C such that the lateral etching rate increases consecutively from the
lowermost level patterns uppermost level patterns protective insulation film 28 in the step of FIG. 5D. - Further, the present embodiment provides an advantageous feature of suppressing the increase of resistance of the
pixel electrode 29, by interposing theTi pattern 29A between thepixel electrode 29 and theconductor pattern 27 e. - [SECOND EMBODIMENT]
- FIG. 6 shows the construction of a
TFT 40 according to a second embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted. - Referring to FIG. 6, the
TFT 40 has a construction similar to that of theTFT 30 except that theTi pattern 29A is now omitted and apixel electrode 39 of Ti is provided in direct contact with theconductor layer 27 e of theohmic electrode 27B, in place of theITO pixel electrode 29. By setting the thickness of theTi pixel electrode 39 to be about 30 nm or less, it is possible to secure a sufficient optical transparency for thepixel electrode 39. - According to the construction of the
TFT 40 of FIG. 6, the step of formation of theTi pattern 29A is omitted and the fabrication process of the liquid crystal display device including theTFT 40 is substantially facilitated. - As other features of the
TFT 40 are identical with those of theTFT 30, further description of theTFT 40 will be omitted. - [THIRD EMBODIMENT]
- In the foregoing
TFT gate insulation film 23 is generally formed of SiN, wherein the tendency of an SiN film to accumulate stress therein is well known in the art. Thus, in the liquid crystal display devices that use theTFTs glass substrate 21, which corresponds to the TFT substrate 1 of FIG. 1. In the worst case, the SiN film constituting thegate insulation film 23 may cause an exfoliation. Further, thegate insulation film 23 thus formed of SiN tends to form a projection on the surface thereof in conformity with the shape of thegate electrode 22. In such a case, it becomes difficult to form the TFT on thegate insulation film 23 because of the existence of the projection. - FIGS.7A-7E are diagrams showing the fabrication process of
TFT gate insulation film 23 has a planarized surface. - Referring to FIG. 7A, a
conductor layer 22M of an Al—Nd alloy or an Al—Sc alloy is deposited on theglass substrate 21 by a PVD process, followed by a formation of a resist pattern in conformity with the shape of thegate electrode 22 to be formed. - Next, in the step of FIG. 7B, the
conductor layer 22M is patterned while using the resist pattern as a mask, to form thegate electrode 22. Further, an SOG (spin-on-glass)layer 23 1 is deposited on theglass substrate 21 in the step of FIG. 7C such that theSOG layer 23 1 covers thegate electrode 22. - Next, in the step of FIG. 7D, the
SOG layer 23 1 is subjected to a sintering to form a solidified layer, followed by an etch back process conducted by using a buffered HF solution as an etchant, until thegate electrode 22 is exposed. As a result of the etch back process, there are formed SOG regions (23 1)A and (23 1)B on thesubstrate 21 at both lateral sides of thegate electrode 22. - Next, in the step of FIG. 7E, an
SiN film 23 2 is deposited on the structure of FIG. 7D by a plasma CVD process, and theamorphous silicon layer 24 and the channelprotective pattern 25 are formed on theSiN film 23 2 by a plasma CVD process. - Further, by conducting the process steps described with reference to FIGS.5B-5E on the structure of FIG. 7E thus formed, the
TFT TFT gate insulation film 23 together with theSiN film 232. - In the present embodiment, it becomes possible to planarized the surface of the
gate insulation film 23 by forming the SOG regions (23 1)A and (23 1)B at both sides of thegate electrode 22. Thereby the fabrication process of theTFT gate insulation film 23 is substantially facilitated. - [FOURTH EMBODIMENT]
- In the process of FIGS.7A-7E described above, the
gate insulation film 23 is formed with a planarized top surface. On the other hand, the structure of FIG. 7E, using SiN for theupper layer 23 2 of thegate insulation film 23, cannot avoid the problem of accumulation of stress in thegate insulation film 23. Thus, the structure of FIG. 7E tends to cause the problem of warp in the TFT substrate 11 on which the TFTs of FIG. 7E are formed. Further, there is a substantial risk, because of the stress in thegate insulation film 23, in that a part of theupper layer 23 2 may cause exfoliation and produce a dust. When such dust is formed, there is a substantial risk that the endurance voltage of the TFT may be degraded. Further, in the step of FIG. 7C, it should be noted that the surface of thegate electrode 22 is covered by theSOG film 23 1, while such a process tends to induce an oxidation at the surface of thegate electrode 22. When such oxidation is caused, the threshold voltage of the TFT is inevitably changed. - FIGS.8A-8E are diagrams showing the fabrication process of the TFT according to a fourth embodiment of the present invention, wherein those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
- Referring to FIG. 8A, the
glass substrate 21 is covered consecutively by aconductor layer 22M of an Al—Nd ally or an Al—Sc alloy and an SiN layer 23M, respectively with a thickness of about 500 nm and about 300 nm, wherein theconductor layer 22M may be deposited by a PVD process while the SiN layer 23M may be deposited by a plasma CVD process. Further, a resist pattern is formed on the SiN film 23M in correspondence to thegate electrode 22 to be formed. - Next, in the step of FIG. 8B, the SiN layer23M and the
conductor layer 22 are subjected to a patterning process while using the resist pattern as a mask, to form thegate electrode 22 such that thegate electrode 22 is covered by anSiN pattern 23A. - Next, in the step of FIG. 8C, an
SOG layer 23 1 is formed on the structure of FIG. 8B with a thickness of about 800 nm by a spin-coating process, such that theSOG layer 23 1 covers theSiN pattern 23A. After the formation, theSOG layer 23 1 is subjected to a sintering process. - Next, in the step of FIG. 8D, the
SOG layer 23 1 thus sintered is subjected to an etch back process conducted by a wet etching process while using a buffered HF solution for the etchant, until theSiN pattern 23A is exposed. As a result, SOG regions (23 1)A and (23 1)B are formed on thesubstrate 21 at both lateral sides of the gate structure, which is formed by thegate electrode 22 and theSiN pattern 23 thereon, with a thickness of about 800 nm. - Next, in the step of FIG. 8E, a
thin SiN film 23 2 is deposited on the structure of FIG. 8D by a plasma CVD process with a thickness of about 100 nm, followed by a deposition of anamorphous silicon layer 24M further on theSiN film 23 2 with a thickness of about 30 nm. - Further, a channel
protective film 25 is formed on theamorphous silicon layer 24M with a thickness of about 120 nm. Furthermore, the steps of FIGS. 5B-5E are conducted on the structure of FIG. 8E, and theTFT TFT gate insulation film 23 together with theSiN film 23 2. - According to the present embodiment, the problem of stress accumulation in the TFT substrate11 caused by the
gate insulation film 23, is successfully avoided by reducing the thickness of theSiN film 23 2. As theconductor layer 22M, used for thegate electrode 22, is covered immediately by theSiN layer 23 after the formation thereof in the present embodiment, the problem of the top surface of thegate electrode 22 being contaminated by the organic material from the SOG film is effectively eliminated. Thereby, the problem of increase of the gate resistance as a result of use of SOG is eliminated. As thegate insulation film 23 is primarily formed by the SOG, thegate insulation film 23 has a highly planarized surface and the construction of a TFT on such a planarized gate insulation film is substantially facilitated. - In the embodiments described heretofore, it should be noted that the
conductor patterns - Similarly, the
gate electrode 22 is by no means limited to an Al—Nd alloy or Al—Sc alloy but a refractory metal element such as W, Ta, Cr or Ti may also be used. The use of Al—Nd alloy or Al—Sc alloy is preferable, though, because of the low electrical resistance and resistance against hillock. - In the fourth embodiment, it is also possible to use an SiO2 pattern or an SiON pattern for the SiN insulating pattern on the
gate electrode 22. Further, thechannel protection film 25 may be formed by SiO2 or SiON. - Further, the present invention is by no means limited to the embodiments described heretofore, but various variations and modifications may be made without departing from the scope of the invention.
- The present application is based on Japanese priority application No.10-147761 filed on May 29, 1998, the entire contents of which are hereby incorporated by reference.
Claims (22)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/942,194 US6445428B1 (en) | 1998-05-28 | 2001-08-29 | Thin film transistor for a liquid crystal display device and a fabrication process thereof |
US10/186,825 US6704069B2 (en) | 1998-05-28 | 2002-07-01 | TFT-LCD having particular gate insulator structure |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10147761A JPH11340462A (en) | 1998-05-28 | 1998-05-28 | Liquid crystal display and fabrication thereof |
JP10-147761 | 1998-05-28 | ||
US09/251,044 US6323917B1 (en) | 1998-05-28 | 1999-02-18 | Thin film transistor for a liquid crystal display device and a fabrication process thereof |
US09/942,194 US6445428B1 (en) | 1998-05-28 | 2001-08-29 | Thin film transistor for a liquid crystal display device and a fabrication process thereof |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/251,044 Division US6323917B1 (en) | 1998-05-28 | 1999-02-18 | Thin film transistor for a liquid crystal display device and a fabrication process thereof |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/186,825 Division US6704069B2 (en) | 1998-05-28 | 2002-07-01 | TFT-LCD having particular gate insulator structure |
Publications (2)
Publication Number | Publication Date |
---|---|
US20020047950A1 true US20020047950A1 (en) | 2002-04-25 |
US6445428B1 US6445428B1 (en) | 2002-09-03 |
Family
ID=15437578
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/251,044 Expired - Lifetime US6323917B1 (en) | 1998-05-28 | 1999-02-18 | Thin film transistor for a liquid crystal display device and a fabrication process thereof |
US09/942,194 Expired - Fee Related US6445428B1 (en) | 1998-05-28 | 2001-08-29 | Thin film transistor for a liquid crystal display device and a fabrication process thereof |
US10/186,825 Expired - Fee Related US6704069B2 (en) | 1998-05-28 | 2002-07-01 | TFT-LCD having particular gate insulator structure |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/251,044 Expired - Lifetime US6323917B1 (en) | 1998-05-28 | 1999-02-18 | Thin film transistor for a liquid crystal display device and a fabrication process thereof |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/186,825 Expired - Fee Related US6704069B2 (en) | 1998-05-28 | 2002-07-01 | TFT-LCD having particular gate insulator structure |
Country Status (4)
Country | Link |
---|---|
US (3) | US6323917B1 (en) |
JP (1) | JPH11340462A (en) |
KR (1) | KR100334046B1 (en) |
TW (1) | TW409426B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090056990A1 (en) * | 2007-08-31 | 2009-03-05 | Seiko Epson Corporation | Electro-optic device and electronic apparatus |
US20090065778A1 (en) * | 2006-03-15 | 2009-03-12 | Sharp Kabushiki Kaisha | Active Matrix Substrate, Display Apparatus, and Television Receiver |
Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3362008B2 (en) * | 1999-02-23 | 2003-01-07 | シャープ株式会社 | Liquid crystal display device and manufacturing method thereof |
KR20020052562A (en) * | 2000-12-26 | 2002-07-04 | 구본준, 론 위라하디락사 | In-plane switching mode liquid crystal device and method for manufacturing the same |
KR100491144B1 (en) * | 2001-12-26 | 2005-05-24 | 삼성에스디아이 주식회사 | Flat Panel Display Device and Fabrication Method thereof |
KR100491143B1 (en) * | 2001-12-26 | 2005-05-24 | 삼성에스디아이 주식회사 | Flat Panel Display with Black Matrix and Method for fabricating the Same |
KR100869736B1 (en) * | 2001-12-29 | 2008-11-21 | 엘지디스플레이 주식회사 | Liquid Crystal Display Device And Method For Manufacturing The Same |
TW589663B (en) * | 2003-05-12 | 2004-06-01 | Au Optronics Corp | Flat panel display and manufacturing method thereof |
CN1324359C (en) * | 2003-05-28 | 2007-07-04 | 友达光电股份有限公司 | Planar displaying device and producing method thereof |
TWI336921B (en) * | 2003-07-18 | 2011-02-01 | Semiconductor Energy Lab | Method for manufacturing semiconductor device |
KR100623247B1 (en) * | 2003-12-22 | 2006-09-18 | 삼성에스디아이 주식회사 | flat panel display device and fabrication method of the same |
JP2005203579A (en) * | 2004-01-16 | 2005-07-28 | Chi Mei Electronics Corp | Array substrate with reduced wiring resistance and its manufacturing method |
US7223641B2 (en) * | 2004-03-26 | 2007-05-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, method for manufacturing the same, liquid crystal television and EL television |
WO2006019157A1 (en) | 2004-08-20 | 2006-02-23 | National Institute Of Advanced Industrial Science And Technology | Semiconductor element and process for producing the same |
US7668209B2 (en) * | 2005-10-05 | 2010-02-23 | Lg Electronics Inc. | Method of processing traffic information and digital broadcast system |
TWI273712B (en) * | 2005-12-30 | 2007-02-11 | Au Optronics Corp | A method for manufacturing a bottom substrate of a liquid crystal display device with three mask processes |
JP2008191415A (en) * | 2007-02-05 | 2008-08-21 | Toshiba Matsushita Display Technology Co Ltd | Liquid crystal display device and manufacturing method thereof |
KR100986024B1 (en) * | 2007-12-31 | 2010-10-07 | (주)에이디에스 | Method for manufacturing transparent electrode pattern and method for manufacturing optical device |
US9666719B2 (en) * | 2008-07-31 | 2017-05-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9991311B2 (en) | 2008-12-02 | 2018-06-05 | Arizona Board Of Regents On Behalf Of Arizona State University | Dual active layer semiconductor device and method of manufacturing the same |
WO2010138811A2 (en) * | 2009-05-29 | 2010-12-02 | Arizona Board Of Regents, For And On Behalf Of Arizona State University | Method of providing a flexible semiconductor device at high temperatures and flexible semiconductor device thereof |
US9721825B2 (en) | 2008-12-02 | 2017-08-01 | Arizona Board Of Regents, A Body Corporate Of The State Of Arizona, Acting For And On Behalf Of Arizona State University | Method of providing a flexible semiconductor device and flexible semiconductor device thereof |
US9601530B2 (en) | 2008-12-02 | 2017-03-21 | Arizona Board Of Regents, A Body Corporated Of The State Of Arizona, Acting For And On Behalf Of Arizona State University | Dual active layer semiconductor device and method of manufacturing the same |
CN103596370A (en) | 2008-12-02 | 2014-02-19 | 代表亚利桑那大学的亚利桑那校董会 | Method of preparing a flexible substrate assembly and flexible substrate assembly therefrom |
KR101476817B1 (en) | 2009-07-03 | 2014-12-26 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Display device including transistor and manufacturing method thereof |
KR101623961B1 (en) | 2009-12-02 | 2016-05-26 | 삼성전자주식회사 | Transistor, method of manufacturing the same and electronic device comprising transistor |
WO2012021197A2 (en) | 2010-05-21 | 2012-02-16 | Arizona Board Of Regents, For And On Behalf Of Arizona State University | Method of manufacturing electronic devices on both sides of a carrier substrate and electronic devices thereof |
WO2012021196A2 (en) | 2010-05-21 | 2012-02-16 | Arizona Board Of Regents, For And On Behalf Of Arizona State University | Method for manufacturing electronic devices and electronic devices thereof |
WO2015156891A2 (en) | 2014-01-23 | 2015-10-15 | Arizona Board Of Regents, Acting For And On Behalf Of Arizona State University | Method of providing a flexible semiconductor device and flexible semiconductor device thereof |
WO2017034644A2 (en) | 2015-06-09 | 2017-03-02 | ARIZONA BOARD OF REGENTS a body corporate for THE STATE OF ARIZONA for and on behalf of ARIZONA STATE UNIVERSITY | Method of providing an electronic device and electronic device thereof |
US10381224B2 (en) | 2014-01-23 | 2019-08-13 | Arizona Board Of Regents On Behalf Of Arizona State University | Method of providing an electronic device and electronic device thereof |
KR102221842B1 (en) * | 2014-04-08 | 2021-03-03 | 삼성디스플레이 주식회사 | Sensor substrate, method of manufacturing the same and display apparatus having the same |
EP3143641A4 (en) | 2014-05-13 | 2018-01-17 | Arizona Board of Regents, a Body Corporate of the State of Arizona acting for and on behalf of Arizona State University | Method of providing an electronic device and electronic device thereof |
US10446582B2 (en) | 2014-12-22 | 2019-10-15 | Arizona Board Of Regents On Behalf Of Arizona State University | Method of providing an imaging system and imaging system thereof |
US9741742B2 (en) | 2014-12-22 | 2017-08-22 | Arizona Board Of Regents, A Body Corporate Of The State Of Arizona, Acting For And On Behalf Of Arizona State University | Deformable electronic device and methods of providing and using deformable electronic device |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03220529A (en) | 1990-01-25 | 1991-09-27 | Nec Corp | Manufacture of active matrix liquid crystal display |
US5621556A (en) * | 1994-04-28 | 1997-04-15 | Xerox Corporation | Method of manufacturing active matrix LCD using five masks |
JPH0843860A (en) * | 1994-04-28 | 1996-02-16 | Xerox Corp | Electrically separated pixel element in low-voltage driven active matrix liquid crystal display |
KR0175030B1 (en) | 1995-12-07 | 1999-04-01 | 김광호 | High heat-resistant metal wiring structure of semiconductor device and method of forming the same |
JP3625598B2 (en) * | 1995-12-30 | 2005-03-02 | 三星電子株式会社 | Manufacturing method of liquid crystal display device |
KR100255592B1 (en) * | 1997-03-19 | 2000-05-01 | 구본준 | The structure and manufacturing method of lcd |
-
1998
- 1998-05-28 JP JP10147761A patent/JPH11340462A/en active Pending
-
1999
- 1999-02-18 US US09/251,044 patent/US6323917B1/en not_active Expired - Lifetime
- 1999-02-25 TW TW088102873A patent/TW409426B/en not_active IP Right Cessation
- 1999-04-27 KR KR1019990015042A patent/KR100334046B1/en not_active IP Right Cessation
-
2001
- 2001-08-29 US US09/942,194 patent/US6445428B1/en not_active Expired - Fee Related
-
2002
- 2002-07-01 US US10/186,825 patent/US6704069B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090065778A1 (en) * | 2006-03-15 | 2009-03-12 | Sharp Kabushiki Kaisha | Active Matrix Substrate, Display Apparatus, and Television Receiver |
US8304769B2 (en) | 2006-03-15 | 2012-11-06 | Sharp Kabushiki Kaisha | Active matrix substrate having channel protection film covering transistor channel, and display apparatus and/or, television receiver including same |
US20090056990A1 (en) * | 2007-08-31 | 2009-03-05 | Seiko Epson Corporation | Electro-optic device and electronic apparatus |
US8208108B2 (en) * | 2007-08-31 | 2012-06-26 | Seiko Epson Corporation | Electro-optic device and electronic apparatus |
Also Published As
Publication number | Publication date |
---|---|
US6704069B2 (en) | 2004-03-09 |
US6323917B1 (en) | 2001-11-27 |
KR100334046B1 (en) | 2002-04-26 |
US6445428B1 (en) | 2002-09-03 |
TW409426B (en) | 2000-10-21 |
US20020180903A1 (en) | 2002-12-05 |
JPH11340462A (en) | 1999-12-10 |
KR19990087971A (en) | 1999-12-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6323917B1 (en) | Thin film transistor for a liquid crystal display device and a fabrication process thereof | |
US6897479B2 (en) | ITO film contact structure, TFT substrate and manufacture thereof | |
US6878966B2 (en) | Thin-film transistor display devices | |
US6184966B1 (en) | Semiconductor device and method for producing the same | |
US7319239B2 (en) | Substrate for display device having a protective layer provided between the pixel electrodes and wirings of the active matrix substrate, manufacturing method for same, and display device | |
US6480255B2 (en) | Substrate of LCD device having external terminals covered with protective film and manufacturing method thereof | |
US6730970B1 (en) | Thin film transistor and fabrication method of the same | |
JP2003107523A (en) | Liquid crystal display device | |
KR100673331B1 (en) | Liquid crystal display and method for fabricating the same | |
KR100582599B1 (en) | Liquid crystal display and method for fabricating the same | |
JPH06208137A (en) | Manufacture of thin film transistor matrix | |
KR100654158B1 (en) | Liquid crystal display and method for fabricating the same | |
KR100632216B1 (en) | Array substrate for liquid crystal display device and manufacturing method thereof | |
US6317174B1 (en) | TFT array substrate, liquid crystal display using TFT array substrate, and manufacturing method thereof | |
KR20010066244A (en) | Liquid crystal display device and method for fabricating the same | |
KR100309210B1 (en) | Liquid crystal display and method for fabricating the same | |
KR100897487B1 (en) | Array Substrate of Liquid Crystal Display Device and Fabricating Method Thereof | |
JP3989662B2 (en) | Liquid crystal device and manufacturing method thereof | |
JP2001223366A (en) | Active matrix substrate and its manufacturing method, and electrooptic device | |
KR101097675B1 (en) | Thin film transistor and fabricating method thereof | |
KR100642721B1 (en) | Method for fabricating a liquid crystal display device | |
JP3941246B2 (en) | Manufacturing method of semiconductor device | |
KR100654777B1 (en) | liquid crystal display device and fabrication method thereof | |
JPH09258200A (en) | Liquid crystal display device and its production | |
JPH09185083A (en) | Liquid crystal display device and its production |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
AS | Assignment |
Owner name: FUJITSU DISPLAY TECHNOLOGIES CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:013552/0107 Effective date: 20021024 Owner name: FUJITSU DISPLAY TECHNOLOGIES CORPORATION,JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:013552/0107 Effective date: 20021024 |
|
CC | Certificate of correction | ||
AS | Assignment |
Owner name: FUJITSU LIMITED,JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU DISPLAY TECHNOLOGIES CORPORATION;REEL/FRAME:016345/0310 Effective date: 20050630 Owner name: FUJITSU LIMITED, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU DISPLAY TECHNOLOGIES CORPORATION;REEL/FRAME:016345/0310 Effective date: 20050630 |
|
AS | Assignment |
Owner name: SHARP KABUSHIKI KAISHA,JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:016345/0210 Effective date: 20050701 Owner name: SHARP KABUSHIKI KAISHA, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:016345/0210 Effective date: 20050701 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
REMI | Maintenance fee reminder mailed | ||
LAPS | Lapse for failure to pay maintenance fees | ||
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20140903 |