US20020042155A1

US20020042155A1 - Optical semiconductor device having active layer and carrier recombination layer different from each other

Info

Publication number: US20020042155A1
Application number: US10/002,083
Authority: US
Inventors: Yasutaka Sakata
Original assignee: Individual
Current assignee: Individual
Priority date: 1998-09-02
Filing date: 2001-11-01
Publication date: 2002-04-11
Also published as: JP2000077780A; JP3241002B2; US6350629B1

Abstract

In an optical semiconductor device including a semiconductor substrate, an active layer formed on the semiconductor substrate, a pnpn-type current blocking layer formed on a side of the active layer, and a carrier recombination layer on the semiconductor substrate on the side of the active layer, a structure of the active layer is different from a structure of the carrier recomibination layer.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an optical semiconductor device such as a double-channel planer buried heterostructured (DC-PBH) semiconductor laser device.

2. Description of the Related Art

Generally, in a DC-PBH semiconductor laser device, in order to reduce a leakage current (invalid current) at a high temperature or in a high bias condition, a current blocking structure using a pnpn-type thyristor-structure has been adopted. However, in such a pnpn-type thyristor-structure, carrier recombination at a high bias condition charges up the thyristor to turn it ON (see JP-A-102583; I. Mito et al., “Double-channel Planar Buried-Heterostructure Laser Diode With Effective Current Confinement”, Electronics Lett., Vol. 18, No. 22, pp. 953-954, October 1982; and Y. Sakata et al., “Low Threshold and High Uniformity for Novel 1.3 μm-strained InGaAsP MQW DC-PBH LD's Fabricated by the All-Selected MOVPE Technique”, IEEE photonics Tech. Lett, Vol. 9, No. 3, pp. 291-293, March 1997).

In order to avoid the above-mentioned latch-up phenomenon in the pnpn-type thyristor-structure, a carrier recombination layer has been provided in the DC-PBH semiconductor laser device.

For example, in a first prior art semiconductor laser device (see JP-A-8-213691) including an InGaAsP active layer, a p-type InP buried layer, an n-type InP current blocking layer, a semi-insulating InP current blocking layer and an n-type InP buried layer, an InGaAsP carrier recombination is provided between the semi-insulating InP layer and the n-type InP buried layer.

In a second prior art semiconductor laser device (see JP-A-8-236858) including an InGaAsP active layer, an n-type InP current blocking layer and a p-type InP current blocking layer, an i-type InGaAsP carrier recombination layer is provided on the p-type InP current blocking layer.

In a third prior art semiconductor laser device (see JP-A-9-167874) including an InGaAsP bulk or quantum well structured active layer, a p-type InP buried layer, an n-type current blocking layer and a p-type current blocking layer, an In GaAsP carrier recombination layer is provided on the p-type InP current blocking layer.

In a fourth prior art semiconductor laser device (see JP-A-9-266349) including a multiple quantum well (MQW) active layer, a p-type InP buried layer, an n-type current blocking layer, a p-type current blocking layer and an n-type InP buried layer, an MQW carrier recombination layer is provided between the p-type InP current blocking layer and the n-type InP buried layer.

In a fifth prior art semiconductor laser device (see JP-A-10-93190) including an MQW active layer, a p-type InP current blocking layer and an n-type InP current blocking layer, an MQW carrier recombination layer is provided beneath the n-type InP current blocking layer.

In the above-described prior art semiconductor laser devices, however, since the structure of the carrier recombination layer is the same as that of the active layer, the invalid current consumed in the carrier recombination layer is increased as compensation to suppress the turning ON operation of the thyristor structure, thus increasing the consumption power at a high temperature and at a high bias condition.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an optical semiconductor device such as a semiconductor laser device capable of reducing the invalid current.

According to the present invention, in an optical semiconductor device including a semiconductor substrate, an active layer formed on the semiconductor-substrate, a pnpn-type current blocking layer formed on a side of the active layer, and a carrier recombination layer on the semiconductor substrate on the side of the active layer, a structure of the active layer is different from a structure of the carrier recombination layer. For example, the active layer is constructed by an MQW structure, and the carrier recombination layer is constructed by an i-type InGaAsP layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be more clearly understood from the description set forth below, with reference to the accompanying drawings, wherein: [0014]
FIGS. 1A through 1G are cross-sectional views for explaining a first embodiment of the method for manufacturing a semiconductor laser device according to the present invention; [0015]
FIG. 2 is perspective view illustrating the semiconductor laser device obtained by the method as illustrated in FIG. 1A through 1G; [0016]
FIGS. 3A through 3H are cross-sectional views for explaining a second embodiment of the method for manufacturing a semiconductor laser device according to the present invention; [0017]
FIG. 4 is a perspective view illustrating the semiconductor laser device obtained by the method as illustrated in FIG. 3A through 3H; [0018]
FIGS. 5A through 5F are cross-sectional views for explaining a third embodiment of the method for manufacturing a semiconductor laser device according to the present invention; [0019]
FIG. 6 is a perspective view illustrating the semiconductor laser device obtained by the method as illustrated in FIG. 5A through 5F; [0020]
FIGS. 7A through 7H are cross-sectional views for explaining a fourth embodiment of the method for manufacturing a semiconductor laser device according to the present invention; [0021]
FIG. 8 is a perspective view illustrating the semiconductor laser device obtained by the method as illustrated in FIG. 7A through 7H; [0022]
FIGS. 9A through 9H are cross-sectional views for explaining a fifth embodiment of the method for manufacturing a semiconductor laser device according to the present invention; [0023]
FIG. 10 is a perspective view illustrating the semiconductor laser device obtained by the method as illustrated in FIG. 9A through 9H; [0024]
FIGS. 11A through 11G are cross-sectional views for explaining a sixth embodiment of the method for manufacturing a semiconductor laser device according to the present invention; and [0025]
FIG. 12 is a perspective view illustrating the semiconductor laser device obtained by the method as illustrated in FIG. 11A through 11G.[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1A through 1G are cross-sectional views for explaining a first embodiment of the method for manufacturing a semiconductor laser device according to the present invention. [0027]
First, referring to FIG. 1A, an about 0.10 μm thick i-type InGaAsP [0028] carrier recombination layer 102 having a bandgap wavelength of about 1.20 μm and a p-type InP layer 103 are sequentially grown by a metal-organic vapor phase epitaxy (MOVPE) process on a (100) n-type InP substrate 101. Then, a silicon dioxide layer is deposited by a chemical vapor deposition (CVD) process on the entire surface, and the silicon dioxide layer is patterned by a photolithography and etching process. As a result, a silicon dioxide pattern 104 having an about 1.5 μm wide-striped space is formed along the direction [011] of the n-type InP substrate 101.
Next, referring to FIG. 1B, the P-[0029] type InP layer 103 and the i-type InGaAsP carrier recombination layer 102 are etched by a wet etching process using the silicon dioxide pattern 104 as a mask.
Next, referring to FIG. 1C, an n-[0030] type InP layer 1051, an MQW active layer 1502 consisting of six periods of one about 5 nm thick 1.0% compression-strained In_0.881Ga_0.119As_0.567P_0.433well layer and one about 10 nm thick In_0.810Ga_0.190As_0.405P_0.595barrier layer and a p-type InP layer 1053 are selectively and sequentially grown by an MOVPE process using the silicon dioxide pattern 104 as a mask. In this case, the MQW active layer 1052 has a photoluminescence wavelength of 1.29 μm. Then, the silicon dioxide pattern 104 is removed.
Next, referring to FIG. 1D, a silicon dioxide layer is deposited by a CVD process on the entire surface, and the silicon dioxide layer is patterned by a self-alignment process (see Y. Sakata et al., “All-Selective MOVPE-Grown 1.3 μm strained Multi-Quantum-Well Buried-Heterostructure Laser Diodes”, IEEE Journal of Quantum Electronis, Vol. 35, No. 3, FIG. 3, p. 370, March 1999). As a result, a [0031] silicon dioxide pattern 107 is formed only on the p-type InP layer 1052, i.e., only on a mesa structure.
Next, referring to FIG. 1E, a p-[0032] type InP layer 108, an n-type InP layer 109 and a p-type InP layer 110 are sequentially grown by an MOVPE process using the silicon dioxide pattern 107 as a mask. Note that the p-type InP layer 108, the n-type InP layer 109 and the p-type InP layer 110 form a current blocking layer. Then, the silicon dioxide pattern 107 is removed.
Next, referring to FIG. 1F, a p-type InP clad [0033] layer 111 and a p-type InGaAs cap layer 112 are sequentially grown by an MOVPE process.
Finally, referring to FIG. 1G, a p-[0034] side electrode 113 and an n-side electrode 114 are formed on the front and back surfaces, respectively, thus completing a semiconductor laser device as illustrated in FIG. 2.
The semiconductor laser device of FIG. 2 is cut so that its length is 300 μm. Also, a 90 percent high reflection layer (not shown) is coated on a rear end facet, and an AlN heat sink (not shown) is adhered to the semiconductor laser devico of FIG. 2. In this case, the following laser characteristics were obtained: [0035]
1) The threshold currents at 25° C. and 85° C. were 4 mA and 10 mA, respectively. The slope efficiencies at 25° C. and 85° C. were 0.60 W/A and 0.50 W/A, respectively. [0036]
Thus, at a high temperature such as 85° C., a low threshold current and a high slope efficiency were obtained. [0037]
2) A drive current in a 15 mW light output operation mode at 85° C. was 41 mA, which exhibited an excellent output characteristic. [0038]
FIG. 3A through 3H are cross-sectional views for explaining a second embodiment of the method for manufacturing a semiconductor laser device according to the present invention. [0039]
First, referring to FIG. 3A, a silicon dioxide layer is deposited by a CVD process on a (100) n-[0040] type InP substrate 201, and the silicon dioxide layer is patterned by a photolithography and etching process. As a result, a silicon dioxide pattern 202 having an about 1.5 μm wide-striped space along the direction [011] of the n-type InP substrate 201.
Next, referring to FIG. 3B, an n-[0041] type InP layer 2031, an MQW active layer 2032 consisting of six periods of one about 5 nm thick 1.0% compression-strained In_0.881Ga_0.119As_0.567P_0.433well layer and one about 10 nm thick In_0.810Ga_0.190As_0.405P_0.595barrier layer and a p-type InP layer 2033 are selectively and sequentially is grown by an MOVPE process using the silicon dioxide pattern 202 as a mask. In this case, the MQW active layer 2032 has a photoluminescence wavelength of 1.29 μm. Then, the silicon dioxide pattern 202 is removed.
Next, referring to FIG. 3C, a silicon dioxide layer is deposited by a CVD process on the entire surface, and the silicon dioxide layer is patterned by a photolithography and etching process. As a result, a [0042] silicon dioxide pattern 204 is formed on the p-type InP layer 2033 and its periphery, i.e., on a mesa structure and its periphery.
Next, referring to FIG. 3D, an about 0.10 [0043] 82 m thick i-type InGaAsP carrier recombination layer 205 having a bandgap wavelength of about 1.20 μm is grown by an MOVPE process on the n-type InP substrate 101 using the silicon dioxide pattern 204 as a mask. Then, the silicon dioxide pattern 204 is removed.
Next, referring to FIG. 3E, a silicon dioxide layer is deposited by a CVD process on the entire surface, and the silicon dioxide layer is patterned by a self-alignment process. As a result, a [0044] silicon dioxide pattern 206 is formed only on the p-type InP layer 2033, i.e., only on a mesa structure.
Next, referring to FIG. 3F, a p-[0045] type InP layer 207, an n-type InP layer 208 and a p-type InP layer 209 are sequentially grown by an MOVPE process using the silicon dioxide pattern 206 as a mask. Note that the p-type InP layer 207, the n-type InP layer 208 and the p-type InP layer 209 form a current blocking layer. Then, the silicon dioxide pattern 206 is removed.
Next, referring to FIG. 3G, a p-type InP clad [0046] layer 210 and a p-type InGaAs cap layer 211 are sequentially grown by an MOVPE process.
Finally, referring to FIG. 3H, a p-[0047] side electrode 212 and an n-side electrode 213 are formed on the front and back surfaces, respectively, thus completing a semiconductor laser device as illustrated in FIG. 4.
The semiconductor laser device of FIG. 4 is cut so that its length is 300 μm. Also, a 90 percent high reflection layer (not shown) is coated on a rear end facet, and an AIN heat sink (not shown) is adhered to the semiconductor laser device of FIG. 4. In this case, the following laser characteristics were obtained: [0048]
1) The threshold currents at 25° C. and 85° C. were 3.9 mA and 9.8 mA, respectively. The slope efficiencies at 25° C. and 85° C. were 0.61 W/A and 0.51 W/A, respectively. [0049]
Thus, at a high temperature such as 85° C., a low threshold current and a high slope efficiency were obtained. [0050]
2) A drive current in a 15 mW light output operation mode at 85° C. was 40 mA, which exhibited an excellent output characteristic. [0051]
FIG. 5A through 5F are cross-sectional views for explaining a third embodiment of the method for manufacturing a semiconductor laser device according to the present invention. [0052]
First, referring to FIG. 5A, in the same way as in FIG. 3A, silicon dioxide layer is deposited by a CVD process on a (100) n-[0053] type InP substrate 301, and the silicon dioxide layer is patterned by a photolithography and etching process. As a result, a silicon dioxide pattern 302 having an about 1.5 μm wide-striped space is formed along the direction [011] of the n-type InP substrate 301.
Next, referring to FIG. 5B, in the same way as in FIG. 3B, an n-[0054] type InP layer 3031, an MQW active layer 3032 consisting of six periods of one about 5 nm thick 1.0% compression-strained In_0.881Ga_0.119As_0.567P_0.433well layer and one about 10 nm thick In_0.810Ga_0.119As_0.405P_0.595barrier layer and a p-type InP layer 3033 are selectively and sequentially grown by an MOVPE process using the silicon dioxide pattern 302 as a mask. In this case, the MQW active layer 303 has a photoluminescence wavelength of 1.29 μm. Then, the silicon dioxide pattern 302 is removed.
Next, referring to FIG. 5C, a silicon dioxide layer is deposited by a CVD process on the entire surface, and the silicon dioxide layer is patterned by a self-alignment process. As a result, a [0055] silicon dioxide pattern 304 is formed only on the p-type InP layer 3033, i.e., only on a mesa structure.
Next, referring to FIG. 5D, an about 0.10 μm thick i-type InGaAsP [0056] carrier recombination layer 305 having a bandgap wavelength of about 1.20 μm, a p-type InP layer 307, an n-type InP layer 308 and a p-type InP layer 309 are sequentially grown by an MOVPE process using the silicon dioxide pattern 304 as a mask. Note that p-type InP layer 307, the n-type InP layer 308 and the p-type InP layer 309 form a current blocking layer. Then, the silicon dioxide pattern 304 is removed.
Next, referring to FIG. 5E, in the same way as in FIG. 3G, a p-type InP clad [0057] layer 310 and a p-type InGaAs cap layer 311 are sequentially grown by an MOVPE process.
Finally, referring to FIG. 5F, in the same way as in FIG. 3H, a p-[0058] side electrode 312 and an n-side electrode 313 are formed on the front and back surfaces, respectively, thus completing a semiconductor laser device as illustrated in FIG. 6.
The semiconductor laser device of FIG. 6 is cut so that its length is 300 μm. Also, a 90 percent high reflection layer (not shown) is coated on a rear end facet, and an AIN heat sink (not shown) is adhered to the semiconductor laser device of FIG. 6. In this case, the following laser characteristics were obtained: [0059]
1) The threshold currents at 25° C. and 85° C. were 4 mA and 10 mA, respectively. The slope efficiencies at 25° C. and 85° C. were 0.58 W/A and 0.49 W/A, respectively. [0060]
Thus, at a high temperature such as 85° C., a low threshold current and a high slope efficiency were obtained. [0061]
2) A drive current in a 15 mW light output operation mode at 85° C. was 42 mA, which exhibited an excellent output characteristic. [0062]
FIG. 7A through 7H are cross-sectional views for explaining a fourth embodiment of the method for manufacturing a semiconductor laser device according to the present invention. [0063]
First, referring to FIG. 7A, a silicon dioxide layer is deposited by a CVD process on a (100) n-[0064] type InP substrate 401, and the silicon dioxide layer is patterned by a photolithography and etching process. As a result, an about 1 μm wide silicon dioxide pattern 402 is formed along the direction [011] of the n-type InP substrate 401.
Next, referring to FIG. 7B, an about 0.1 μm thick i-type InGaAsP [0065] carrier recombination layer 403 having a bandgap wavelength of about 1.20 μm and a p-type InP layer 404 are sequentially grown by an MOVPE process on the n-type InP substrate 101 using the silicon dioxide pattern 402 as a mask. Then, the silicon dioxide pattern 402 is removed.
Next, referring to FIG. 7C, a silicon dioxide layer is deposited by a CVD process on the entire surface, and the silicon dioxide layer is patterned by a photolithography and etching process. As a result, a [0066] silicon dioxide pattern 405 is formed on the p-type InP layer 404.
Next, referring to FIG. 7D, an n-[0067] type InP layer 4061, an MQW active layer 4062 consisting of six periods of one about 5 nm thick 1.0% compression-strained In_0.881Ga_0.119As_0.567P_0.433well layer and one about 10 nm thick In_0.810Ga_0.190As_0.405P_0.595barrier layer and a p-type InP layer 4063 are selectively and sequentially grown by an MOVPE process using the silicon dioxide pattern 405 as a mask. In this case, the MQW active layer 407 has a photoluminescence wavelength of 1.29 μm. Then, the silicon dioxide pattern 405 is removed.
Next, referring to FIG. 7E, a silicon dioxide layer is deposited by a CVD process on the entire surface, and the silicon dioxide layer is patterned by a self-alignment process. As a result, a [0068] silicon dioxide pattern 408 is formed only on the p-type InP layer 4063, i.e., only on a mesa structure.
Next, referring to FIG. 7F, in the same way as in FIG. 3F, a p-[0069] type InP layer 409, an n-type InP layer 410 and a p-type InP layer 411 are sequentially grown by an MOVPE process using the silicon dioxide pattern 408 as a mask. Note that p-type InP layer 409, the n-type InP layer 410 and the p-type InP layer 411 form a current blocking layer. Then, the silicon dioxide pattern 408 is removed.
Next, referring to FIG. 7G, in the same way as in FIG. 3G, a p-type InP clad [0070] layer 412 and a p-type InGaAs cap layer 413 are sequentially grown by an MOVPE process.
Finally, referring to FIG. 7H, in the same way as in FIG. 3H, a p-[0071] side electrode 414 and an n-side electrode 415 are formed on the front and back surfaces, respectively, thus completing a semiconductor laser device as illustrated in FIG. 7.
The semiconductor laser device of FIG. 8 is cut so that its length is 300 μm. Also, a 90 percent high reflection layer (not shown) is coated on a rear end facet, and an AlN heat sink (not shown) is adhered to the semiconductor laser device of FIG. 8. In this case, the following laser characteristics were obtained: [0072]
1) The threshold currents at 25° C. and 85° C. were 4 mA and 10 mA, respectively. The slope efficiencies at 25° C. and 85° C. were 0.60 W/A and 0.50 W/A, respectively. [0073]
Thus, at a high temperature such as 85° C., a low threshold current and a high slope efficiency were obtained. [0074]
2) A drive current in a 15 mW light output operation mode at 85° C. was 41 mA, which exhibited an excellent output characteristic. [0075]
FIG. 9A through 9H are cross-sectional views for explaining a fifth embodiment of the method for manufacturing a semiconductor laser device according to the present invention. [0076]
First, referring to FIG. 9A, an about 0.10 μm thick i-type InGaAsP [0077] carrier recombination layer 502 having a bandgap wavelength of about 1.20 μm is grown by an MOVPE process on a (100) n-type InP substrate 501. Then, a silicon dioxide layer is deposited by a CVD process on the entire surface, and the silicon dioxide layer is patterned by a photolithography and etching process. As a result, a silicon dioxide pattern 503 having an about 3 μm wide-striped space is formed along the direction [011] of the n-type InP substrate 501.
Next, referring to FIG. 9B, the i-type InGaAsP [0078] carrier recombination layer 502 is etched by a wet etching process using the silicon dioxide pattern 503 as a mask. Then, the silicon dioxide pattern 503 is removed.
Next, referring to FIG. 9C, a silicon dioxide layer is deposited by a CVD process on the entire surface, and the silicon dioxide layer is patterned by a photolithography and etching process. As a result, a [0079] silicon dioxide pattern 504 having an about 1.5 μm wide-striped space is formed along the direction [011] of the n-type InP substrate 501.
Next, referring to FIG. 9D, an n-[0080] type InP layer 5051, an MQW active layer 5052 consisting of six periods of one about 5 nm thick 1.0% compression-strained In_0.881Ga_0.119As_0.567P_0.433well layer and one about 10 nm thick In_0.810Ga_0.190As_0.405P_0.595barrier layer and a p-type ItiP layer 5053 are selectively and sequentially grown by an MOVPE process using the silicon dioxide pattern 504 as a mask. In this case, the MQW active layer 505 has a photoluminescence wavelength of 1.29 μm. Then, the silicon dioxide pattern 504 is removed.
Next, referring to FIG. 9E, in the same way as in FIG. 1C, a silicon dioxide layer is deposited by a CVD process on the entire surface, and the silicon dioxide layer is patterned by a self-alignment process. As a result, a [0081] silicon dioxide pattern 506 is formed only on the p-type InP layer 5053, i.e., only on a mesa structure.
Next, referring to FIG. 9F, in the same way as in FIG. 1E, a p-[0082] type InP layer 507, an n-type InP layer 508 and a p-type InP layer 509 are sequentially grown by an MOVPE process using the silicon dioxide pattern 506 as a mask. Note that p-type InP layer 507, the n-type InP layer 508 and the p-type InP layer 509 form a current blocking layer. Then, the silicon dioxide pattern 506 is removed.
Next, referring to FIG. 9G, in the same way as in FIG. 1F, a p-type InP clad [0083] layer 510 and a p-type InGaAs cap layer 511 are sequentially grown by an MOVPE process.
Finally, referring to FIG. 9H, in the same way as in FIG. 1G, a p-[0084] side electrode 512 and an n-side electrode 513 are formed on the front and back surfaces, respectively, thus completing a semiconductor laser device as illustrated in FIG. 10.
The semiconductor laser device of FIG. 10 is cut so that its length is 300 μm. Also, a 90 percent high reflection layer (not shown) is coated on a rear end facet, and an AlN heat sink (not shown) is adhered to the semiconductor laser device of FIG. 10. In this case, the following laser characteristics were obtained: [0085]
1) The threshold currents at 25° C. and 85° C. were 4 mA and 10 mA, respectively. The slope efficiencies at 25° C. and 85° C. were 0.60 W/A and 0.50 W/A, respectively. [0086]
Thus, at a high temperature such as 85° C., a low threshold current and a high sloane efficiency were obtained. [0087]
2) A drive current in a 15 mW light output operation mode at 85° C. was 41 mA, which exhibited an excellent output characteristic. [0088]
FIG. 11A through 11G are cross-sectional views for explaining a sixth embodiment of the method for manufacturing a semiconductor laser device according to the present invention. [0089]
First, referring to FIG. 11A, in the same way as in FIG. 1A, an about 0.10 μm thick i-type InGaAsP [0090] carrier recombination layer 602 having a bandgap wavelength of about 1.20 μm and a p-type InP layer 603 are sequentially grown by a MOVPE process on a (100) n-type InP substrate 601. Then, a silicon dioxide layer is deposited by a CVD process on the entire surface, and the silicon dioxide layer is patterned by a photolithography and etching process. As a result, a silicon dioxide pattern 604 having an about 1.5 cm wide-striped space is formed along the direction [011] of the n-type InP substrate 601.
Next, referring to FIG. 11B, in the same way as in FIG. 1B, the P-[0091] type InP layer 603 and the i-type InGaAsP carrier recombination layer 602 are etched by a wet etching process using the silicon dioxide pattern 604 as a mask.
Next, referring to FIG. 11C, in a similar way to that of FIG. 1C, an n-[0092] type InP layer 6051, an MQW active layer 6052 consisting of four periods of one about 4 nm thick In_0.767Ga_0.233As_0.808P_0.192well layer and one about 10 nm thick In_0.760Ga_0.240As_0.511P_0.489barrier layer and an n-type InP layer 6053 are selectively and sequentially grown by an MOVPE process using the silicon dioxide pattern 604 as a mask. In this case, the MQW active layer 606 has a photoluminescence wavelength of 1.45 μm. Then, the silicon dioxide pattern 604 is removed.
Next, referring to FIG. 11D, in the same way as in FIG. 1D, a silicon dioxide layer is deposited by a CVD process on the entire surface, and the silicon dioxide layer is patterned by a self-alignment process. As a result, a [0093] silicon dioxide pattern 607 is formed only on the p-type InP layer 6053, i.e., only on a mesa structure.
Next, referring to FIG. 11E, in the same way as in FIG. 1E, a p-[0094] type InP layer 608, an n-type InP layer 609 and a p-type InP layer 610 are sequentially grown by an MOVPE process using the silicon dioxide pattern 607 as a mask. Note that the p-type InP layer 608, the n-type InP layer 609 and the p-type InP layer 610 form a current blocking layer. Then, the silicon dioxide pattern 607 is removed.
Next, referring to FIG. 11F, in the same way as in FIG. 1F, a p-type InP clad [0095] layer 611 and a p-type InGaAs cap layer 612 are sequentially grown by an MOVPE process.
Finally, referring to FIG. 11G, in the same way as in FIG. 1G, a p-[0096] side electrode 613 and an n-side electrode 614 are formed on the front and back surfaces, respectively, thus completing a semiconductor laser device as illustrated in FIG. 12.
The semiconductor laser device of FIG. 12 is cut so that its length is 1200 μm. Also, a 96 percent high reflection layer (not shown) is coated on a rear end facet, and a 4 percent low reflection layer is coated on a front end facet. Further, an AlN heat sink (not shown) is adhered to the semiconductor laser device of FIG. 12. In this case, the following laser characteristics were obtained: [0097]
1) The threshold current at 25° C. was 22 mA and the slope efficiency at 25° C. was 0.53 W/A. [0098]
2) The light output at 500 mA current infection mode was 240 mW, and the maximum light output was 395 mW at 1600 mA current injection mode, which exhibited a large light output. [0099]
Although the above-described embodiments relate to InGaAsP semiconductor laser devices, the present invention can applied to III-V semiconductor laser devices and II-VI semiconductor laser devices such as InGaAlAs, GaN, InSb and ZnSSe semiconductor laser devices. Also, the present invention can be applied to buried heterostructured (BH) optical waveguide devices such as optical modulators, optical amplifiers and optical switches. [0100]
As explained hereinabove, according to the present invention, since the structure of the carrier recombination layer is different from that of the active layer, the energy gap of the carrier recombination layer can be wider than that of the active layer. As a result the leakage current to the carrier recombination layer can be suppressed, which can decrease the leakage current at a high temperature and a high bias condition. Thus, a low threshold current operation and a high efficient operation can be carried out. [0101]

Claims

1. An optical semiconductor device comprising:

a semiconductor substrate;

an active layer formed on said semiconductor-substrate;

a pnpn-type current blocking layer formed on a side of said active layer; and

a carrier recombination layer on said semiconductor substrate on the side of said active layer,

a structure of said active layer being different from a structure of said carrier recombination layer.

2. The device as set forth in claim 1, wherein said carrier recombination layer is beneath said pnpn-type current blocking layer.

3. The device as set forth in claim 1, wherein said carrier recombination layer is in contact with said active layer.

4. The device as set forth in claim 1, wherein said semiconductor substrate is an n-type InP substrate,

said device further comprising a p-type InP clad layer on said active layer and said pnpn-type current blocking layer.

5. The device as set forth in claim 4, further comprising an n-type InP clad layer between said n-type InP substrate and said active layer.

6. The device as set forth in claim 1, wherein a bandgap of said carrier recombination layer is larger than a bandgap of said active layer.

7. The device as set forth in claim 1, wherein said active layer comprises a multiple quantum well layer consisting of a plurality of periods each formed by one well layer and one barrier layer, and said carrier recombination layer comprises a single layer.

8. The device as set forth in claim 7, wherein said carrier recombination layer is made of i-type InGaAsP.

9. An optical semiconductor device comprising:

an n-type InP substrate;

an n-type InP clad layer on said n-type InP substrate;

a multiple quantum well active layer formed on said n-type InP clad layer,

a pair of i-type carrier recombination layers, each formed on said n-type InP substrate on one side of said n-type InP clad layer; and

a pair of pnpn-type current blocking layers, each formed on one of said i-type carrier recombination layers on one side of said multiple quantum well active layer.

10. The device as set forth in claim 9, wherein said i-type carrier recombination layers are made of i-type InGaAsP.

11. The device as set forth in claim 9, further comprising a p-type InP clad layer on said multiple quantum well active layer and said pnpn-type current blocking layers.

12. A method for manufacturing an optical semiconductor device, comprising the steps of:

sequentially growing an i-type carrier recombination layer and a first semiconductor layer of a first conductivity type by a metal-organic vapor epitaxy (MOVPE) process on a semiconductor substrate of a second conductivity type;

forming a first mask pattern having a striped space on said first semiconductor layer;

etching said first semiconductor layer and said i-type carrier recombination layer by using said first mask pattern;

sequentially growing a second semiconductor layer of said second conductivity type, a multiple quantum well active layer and a third semiconductor layer of said first conductivity type by an MOVPE process using said first mask pattern on said semiconductor substrate;

removing said first mask pattern after said second semiconductor layer, said multiple quantum well active layer and said third semiconductor layer are grown;

forming a second mask pattern only on said third semiconductor layer after said first mask pattern is removed;

sequentially growing a fourth semiconductor layer of said first conductivity type, a fifth semiconductor layer of said second conductivity type and a sixth semiconductor layer of said first conductivity type by an MOVPE process using said second mask pattern;

removing said second mask pattern after said fourth, fifth and sixth semiconductor layers are grown; and

sequentially growing a seventh semiconductor layer of said first conductivity type and a semiconductor cap layer of said first conductivity type by an MOVPE process after said second mask pattern is removed.

13. The method as set forth in claim 12, wherein said semiconductor substrate and said second and fifth semiconductor layers are made of n-type InP,

said first, third, fourth, fifth, sixth and seventh semiconductor layers being made of p-type InP,

said i-type carrier recombination layer being made of i-type InGaAsP,

said semiconductor cap layer being made of p-type InGaAs.

14. A method for manufacturing an optical semiconductor device, comprising the steps of:

forming a first mask pattern having a striped space on a semiconductor substrate of a second conductivity type;

sequentially growing a first semiconductor layer of said second conductivity type, a multiple quantum well active layer and a second semiconductor layer of a first conductivity type by a metal-organic vapor epitaxy (MOVPE) process using said first mask pattern on said semiconductor substrate;

removing said first mask pattern after said first semiconductor layer, said multiple quantum well active layer and said second semiconductor layer are grown;

forming a second mask pattern on said second semiconductor layer and said semiconductor substrate near said multiple quantum well active layer after said first mask pattern is removed;

growing an i-type carrier recombination layer by an MOVPE process using said second mask pattern on said semiconductor substrate;

removing said second mask pattern after said i-type carrier recombination layer is removed;

forming a third mask pattern only on said second semiconductor layer after said second mask pattern is removed;

sequentially growing a third semiconductor layer of said first conductivity type, a fourth semiconductor layer of said second conductivity type and a fifth semiconductor layer of said first conductivity type by an MOVPE process using said third mask pattern;

removing said third mask pattern after said third, fourth and fifth semiconductor layers are grown; and

sequentially growing a sixth semiconductor layer of said first conductivity type and a semiconductor cap layer of said first conductivity type by an MOVPE process after said third mask pattern is removed.

15. The method as set forth in claim 14, wherein said semiconductor substrate and said first and fourth semiconductor layers are made of n-type InP,

said second, third, fifth and sixth semiconductor layers being made of p-type InP,

said i-type carrier recombination layer being made of i-type InGaAsP,

said semiconductor cap layer being made of p-type InGaAs.

16. A method for manufacturing an optical semiconductor device, comprising the steps of:

forming a second mask pattern only on said second semiconductor layer after said first mask pattern is removed;

sequentially growing an i-type carrier recombination layer, a third semiconductor layer of said first conductivity type, a fourth semiconductor layer of said second conductivity type and a fifth semiconductor layer of said first conductivity type by an MOVPE process using said second mask pattern;

removing said second mask pattern after said i-type carrier recombination layer, said third, fourth and fifth semiconductor layers are grown; and

sequentially growing a sixth semiconductor layer of said first conductivity type and a semiconductor cap layer of said first conductivity type by an MOVPE process after said second mask pattern is removed.

17. The method as set forth in claim 16, wherein said semiconductor substrate and said first and fourth semiconductor layers are made of n-type InP,

said i-type carrier recombination layer being made of i-type InGaAsP,

said semiconductor cap layer being made of p-type InGaAs.

18. A method for manufacturing an optical semiconductor device, comprising the steps of:

sequentially growing an i-type carrier recombination layer and a first semiconductor layer of a first conductivity type by a metal-organic vapor epitaxy (MOVPE) process using the first mask pattern;

removing said first mask pattern after said i-type carrier recombination layer and said first semiconductor layer are grown;

forming a second mask pattern on said first semiconductor layer after said first mask pattern is removed;

sequentially growing a second semiconductor layer of said second conductivity type, a multiple quantum well active layer and a third semiconductor layer of a first conductivity type by a MOVPE process using said second mask pattern on said semiconductor substrate;

removing said second mask pattern after said second semiconductor layer, said multiple quantum well active layer and said third semiconductor layer are grown;

forming a third mask pattern only on said third semsemiconductor layer after said second mask pattern is removed;

sequentially growing a fourth semiconductor layer of said first conductivity type, a fifth semiconductor layer of said second conductivity type and a sixth semiconductor layer of said first conductivity type by an MOVPE process using said third mask pattern;

removing said third mask pattern after said fourth, fifth and sixth semiconductor layers are grown; and

sequentially growing a seventh semiconductor layer of said first conductivity type and a semiconductor cap layer of said first conductivity type by an MOVPE process after said third mask pattern is removed.

19. The method as set forth in claim 18, wherein said semiconductor substrate and said second and fifth semiconductor layers are made of n-type InP,

said first, third, fourth and sixth semiconductor layers being made of p-typo InP,

said i-type carrier recombination layer being made of i-type lnGaAsP,

said semiconductor cap layer being made of p-type InGaAs.

20. A method for manufacturing an optical semiconductor device, comprising the steps of:

growing an i-type carrier recombination layer by a metal-organic vapor epitaxy (MOVPE) process on a semiconductor substrate of a second conductivity type;

forming a first mask pattern having a first striped space on said i-type carrier recombination layer;

etching said i-type carrier recombination layer by suing said first mask pattern;

removing said first mask pattern after said i-type carrier recombination layer is etched;

forming a second mask pattern having a second striped space smaller than said first striped space on said semiconductor substrate and said i-type carrier recombination layer after said first mask pattern is removed;

growing a first semiconductor layer of said second conductivity type, a multiple quantum well active layer and a second semiconductor layer of a first conductivity type by an MOVPE process using said second mask pattern on said semiconductor substrate;

removing said second mask pattern after said first semiconductor layer, said multiple quantum well active layer and said second semiconductor layer are grown;

sequentially growing a third semiconductor layer of said first conductivity type, a fourth semiconductor layer of said second conductivity type and a fourth semiconductor layer of said first conductivity type by an MOVPE process using said third mask pattern;

21. The method as set forth in claim 20, wherein said semiconductor substrate and said first, fourth and sixth semiconductor layer are made of n-type InP,

said i-type carrier recombination layer being made of i-type InGaAsP,

said semiconductor cap layer being made of p-type InGaAs.