US20020018703A1

US20020018703A1 - Semiconductor manufacturing apparatus with an improved wafer cassette

Info

Publication number: US20020018703A1
Application number: US09/785,848
Authority: US
Inventors: Takashi Kyouno
Original assignee: NEC Corp
Current assignee: NEC Electronics Corp
Priority date: 2000-02-16
Filing date: 2001-02-16
Publication date: 2002-02-14
Also published as: KR20010082688A; TW492132B; JP2001230312A; GB0103869D0; GB2365623A

Abstract

The first present invention provides a wafer cassette mechanism comprising: a plurality of wafer tray sets, each set storing a single semiconductor wafer; a supporting mechanism for mechanically supporting the wafer tray sets which are laminated together with each other, and so that adjacent two of the wafer tray sets are in contact directly with each other, the supporting mechanism adjusting level of the laminated wafer trays; and a locking mechanism for locking selected ones of the wafer tray sets so that a target one of the wafer trays is distanced from adjacent underlying and overlying ones of the wafer tray sets.

Description

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor manufacturing apparatus or processing semiconductor wafers, and more particularly to a wafer cassette for carrying semiconductor wafers in the semiconductor manufacturing apparatus.

FIG. 1 is a schematic plane view illustrative of a conventional semiconductor manufacturing apparatus for processing semiconductor wafers. The conventional semiconductor Manufacturing apparatus comprises a body 11 for processing semiconductor devices, a cassette stage 21, on which wafer cassettes 22 for accommodating semiconductor wafers, and a water carrier robot 31 for carrying the semiconductor wafers between the body 11 and the cassette stage 21. The body 11 further composes two load lock chambers 12 connected to the cassette stage through the wafer carrier robot 31 for isolating the body 11 from an external atmosphere, five process chambers 13 for processing the semiconductor devices, and a single carrying chamber 14 which is connected through the two load lock chambers 12 to the cassette stage, and also connected with the process chambers 13 whereby the process chambers 13 and the two load lock chamber 12 arc connected through the carrying chamber 14 to each other. Each of the load lock chambers 12 is provided with a wafer cassette 1 for temporarily storing the semiconductor wafer The wafer carrier robot 31 carries the semiconductor wafers between the wafer cassettes 1 in the two load lock chambers 12 and the wafer cassettes 22 on the cassette stage 21. The carrier chamber 14 has a wafer carrier robot 15 for carrying the semiconductor wafers between the load lock chambers 12 and the process chambers 13 and also between the process chambers 13. Each of the load lock chambers 12 has a first gate valve at a boundary to the wafer carrier robot 31 and a second gate valve at another boundary to the carrier chamber 14. Each of the process chambers 13 has a gate valve at a boundary to the carrier chamber 14. Each of the load lock chambers 12, the process chambers 13 and the carrier chamber 14 is tightly sealed by the gate valve.

Sequential processes for the semiconductor wafers by the above conventional semiconductor manufacturing apparatus will subsequently be described. The semiconductor wafers are stored in the

wafer cassettes

22 on the cassette stage 21. The wafer carrier robot 31 carries the semiconductor wafer from the wafer cassette 22 on the cassette stage 21 to the wafer cassette 1 in the load lock chamber 12, whereby the semiconductor wafer is stored in the wafer cassette 1 in the load lock chamber 12. The wafer carrier robot 15 in the carrier chamber 14 further carries the semiconductor wafer in the wafer cassette 1 in the load lock chamber 12 to the process chamber 13, whereby the semiconductor wafer is then subjected to a predetermined process, for example, a sputtering process, an etching process, or a chemical vapor deposition process. The wafer carrier robot 15 further carries the semiconductor wafer to the other process chamber 13 for a different process After the semiconductor wafer is subjected to the necessary processes, then the wafer carrier robot 15 in the carrier chamber 14 carries the completely processed semiconductor wafer to the wafer cassette 1 in the load lock chamber 12. The wafer carrier robot 31 carries the semiconductor wafer from the wafer cassette 1 in the load lock chamber 12 to the wafer cassette 22 on the cassette stage 21. The gate valves of the load lock chambers 12 and the process chambers 13 are closed for placing the carrier chamber 14, the load lock chambers 12 and the process chambers 13 in individual vacuum states prior to the predetermined processes. After the processes are completed, the load lock chambers 12 are released from the vacuum state for carrying the processed semiconductor wafer in the wafer cassette 1 in the load lock chamber 12 to the wafer cassette 22 on the cassette stage 21 FIG. 2A is a schematic view illustrative of the conventional wafer cassette in the load lock chamber in the semiconductor manufacturing apparatus of FIG. 1. FIG. 2B is a fragmentary enlarged view illustrative of storage grooves of the conventional wafer cassette of a elliptical-shaped broken line marked with “A” in FIG. 2A. The wafer cassette 1 b has a pair of storage trays 8 having plural storage grooves 9 for storing semiconductor wafer 41 The wafer cassette 1 b is elevated by a driving motor 4, so that one pair of the storage grooves 9 is leveled to a predetermined level for storing the semiconductor wafer 41 into the paired storage grooves 9 or picking up the semiconductor wafer 41 from the paired storage grooves 9.

The wafer cassette 1 b provided in each of the load lock chambers 12 of the body 11 has a united structure. The wafer cassette 1 b has the plural storage grooves 9 aligned at a constant pitch “P2”. The pitch “P2” of the wafer cassette 1 b is intentionally designed to be wide so as to avoid the semiconductor wafer 41 from receiving any mechanical damage by hitting with the wafer cassette 1 b in consideration of the accuracy in carrying the semiconductor wafer 41 by the wafer carrying robots 15 and 31. This increases the size of the wafer cassette 1 b. This needs to increase the volume of the load lock chamber 12. This makes longer the necessary time for obtaining the vacuum state. This also makes longer the necessary time for processing the wafer lot.

If the pitch “P 2” of the wafer cassette 1 b is narrowed as avoiding tho above problem as possible for the purpose of the size-reduction wafer cassette 1 b, and for the volume-reduction of the load lock chamber and for shortening the necessary time for making the vacuum state in the load lock chamber then this makes narrowed the acceptable accuracy range in positioning of the wafer carrier robots 15 and 31.

In the above circumstances, it had been required to develop a novel semiconductor manufacturing apparatus with an improved wafer cassette free from the above problem.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to provide a novel semiconductor manufacturing apparatus with an improved wafer cassette free from the above problems.

It is a further object of the present invention to provide a novel semiconductor manufacturing apparatus with an improved wafer cassette which is size-reduced and has a storage groove structure which is narrowed in pitch.

It is a still further object of the present invention to provide a novel wafer cassette free from the above problems.

It is yet a further object of the present invention to provide a novel wafer cassette which is size-reduced and has a storage groove structure which is narrowed in pitch.

The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. [0013]
FIG. 1 is a schematic plane view illustrative of a conventional semiconductor manufacturing apparatus for processing semiconductor wafers. [0014]
FIG. 2A is a schematic view illustrative of the conventional wafer cassette in the load lock chamber in the semiconductor manufacturing apparatus of FIG. 1. [0015]
FIG. 2B is a fragmentary enlarged view illustrative of storage grooves of the conventional wafer cassette of a elliptical-shaped broken line marked with “A” in FIG. 2A. [0016]
FIG. 3 is a schematic plane view illustrative of a semiconductor manufacturing apparatus for processing semiconductor wafers in a first embodiment in accordance with the present invention. [0017]
FIG. 4 is a schematic view illustrative of the novel wafer cassette in the load lock chamber in the semiconductor manufacturing apparatus of FIG. 3. [0018]
FIG. 5 is a fragmentary enlarged view illustrative of storage grooves of the novel wafer cassette in FIG. 4. [0019]

DISCLOSURE OF THE INVENTION

The first present invention provides a wafer cassette mechanism comprising: a plurality of wafer tray sets, each set storing a single semiconductor wafer; a supporting mechanism for mechanically supporting the wafer tray sets which are laminated together with each other, and so that adjacent two of the wafer tray sets are in contact directly with each other, the supporting mechanism adjusting level of the laminated wafer trays; and a locking mechanism for locking selected ones of the wafer tray sets so that a target one of the wafer trays is distanced from adjacent underlying and overlying ones of the wafer tray sets. [0020]
It is preferable that the wafer cassette mechanism is provided in a load lock chamber. [0021]
It is also preferable that the supporting mechanism further comprises: a driving motor; an elevation rod connected with the driving motor; a stacking stage connected through the elevation rod to the driving motor for allowing the wafer trays to be stacked over the stacking stage, and a guide mechanism supporting the wafer trays and the stacking stage for allowing the wafer trays and the stacking stage to be elevated by a driving force of the driving motor. [0022]
It is preferable that the locking mechanism further comprises: at least two sets of locking members provided different in level by a first pitch which is larger than a second pitch which is defined between adjacent laminated two of the wafer trays in contact directly with each other. [0023]
It is preferable that each of the locking members comprises a locking pin. [0024]
It is further preferable that each of the wafer trays further comprises: a body having a flat top surface and a flat bottom face and a thickness as well as having a locking holes into which the locking pin is inserted; and a contact portion inwardly extending from the body for allowing an edge of semiconductor wafer to be in contact with an upper surface of the contact portion. [0025]
It is preferable that the contact portion is tapered. [0026]
The second present invention provides a wafer cassette mechanism comprising: a plurality of wafer tray sets, each set storing a single semiconductor wafer; a supporting mechanism for mechanically supporting the wafer tray sets which are laminated together with each other, and so that adjacent two of the wafer tray sets are in contact directly with each other; the supporting mechanism adjusting level of the laminated wafer trays; and a locking mechanism for locking selected ones of the wafer tray sets so that a first pitch defined between a target one of the wafer trays and an adjacent overlying one of the wafer tray as well as a second pitch defined between the target wafer tray and an adjacent underlying one of the wafer tray are larger than a third pitch defined between laminated adjacent two of the wafer trays. [0027]
It is preferable that the wafer cassette mechanism is provided in a load lock chamber [0028]
It is preferable that the supporting mechanism further comprises: a driving motor; an elevation rod connected with the driving motor; a stacking stage connected through the elevation rod to the driving motor for allowing the wafer trays to be stacked over the stacking stage; and a guide mechanism supporting the wafer trays and the stacking stage for allowing the wafer trays and the stacking stage to be elevated by a driving force of the driving motor. [0029]
It is preferable that the locking mechanism further comprises: at least two sets of locking members provided different in level by the first pitch. [0030]
It is preferable that each of the locking members comprises a locking pin. [0031]
It is further preferable that each of the wafer trays further comprises: a body having a flat top surface and a flat bottom face and a thickness as well as having a locking hole, into which the locking pin is inserted; and a contact portion inwardly extending from the body for allowing an edge of semiconductor wafer to be in contact with an upper surface of the contact portion. [0032]
It is further preferable that the contact portion is tapered. [0033]
The third present invention provides a semiconductor manufacturing apparatus comprising a plurality of process chambers; at least a load lock chamber having a first type wafer cassette; a carrier chamber connected with all of the process chambers load lock chamber, and the carrier chamber having a first carrier robot arm; a cassette stage having a plurality of second type wafer cassettes; and a second carrier robot arm between the cassette stage and the at least load lock chamber, wherein the wafer cassette further comprises: a plurality of wafer tray sets, each set storing a single semiconductor wafer; a supporting mechanism for mechanically supporting the wafer tray sets which are laminated together with each other, and so that adjacent two of the wafer tray sets are in contact directly with each other, the supporting mechanism adjusting level of the laminated wafer trays; and a locking mechanism for locking selected ones of the wafer tray sets so that a target one of the wafer trays is distanced from adjacent underlying and overlying ones of the wafer tray sets. [0034]
It is also preferable that the wafer cassette mechanism is provided in a load lock chamber. [0035]
It is also preferable that the supporting mechanism further comprises a driving motor; an elevation rod connected with the driving motor; a stacking stage connected through the elevation rod to the driving motor for allowing the wafer trays to be stacked over the stacking stage; and a grease mechanism supporting the wafer trays and the stacking stage for allowing the wafer trays and the stacking stage to be elevated by a driving force of the driving motor. [0036]
It is also preferable that the locking mechanism further comprises; at least two sets of locking members provided different in level by a first pitch which is larger than a second pitch which is defined between adjacent laminated two of the wafer trays in contact directly with each other. [0037]
It is preferable that each of the locking members comprises a locking pin. [0038]
It is further preferable that each of the wafer trays further comprises: a body having a flat top surface and a flat bottom face and a thickness as well as having a locking hole, into which the locking pin is inserted; and a contact portion inwardly extending from the body for allowing an edge of semiconductor wafer to be in contact with an upper surface of, the contact portion. [0039]
It is further, preferable that the contact portion is tapered. [0040]
The fourth present invention provides a semiconductor manufacturing apparatus comprising: a plurality of process chambers; at least a load lock chamber having a first type wafer cassette; a carrier chamber connected with all of the process chambers load lock chamber, and the carrier chamber having a first carrier robot arm; a cassette stage having a plurality of second type wafer cassettes; and a second carrier robot arm between the cassette stage and the at least load lock chamber, wherein the wafer cassette further comprises: a plurality of wafer tray sets, each set storing a single semiconductor wafer; a supporting mechanism for mechanically supporting the wafer tray sets which are laminated together with each other, and so that adjacent two of the wafer tray sets arc in contact directly with each other, the supporting mechanism adjusting level of the laminated wafer trays; and a locking mechanism for locking selected ones of the wafer tray sets so that a first pitch defined between a target one of the wafer trays and an adjacent overlying one of the wafer tray as well as a second pitch defined between the target wafer tray and an adjacent underlying one of the wafer tray are larger than a third pitch defined between laminated adjacent two of the wafer trays. [0041]
It is preferable that the wafer cassette mechanism is provided in a load lock-hamber. [0042]
It is preferable that the supporting mechanism further comprises: a driving motor; an elevation rod connected with the driving motor; a stacking stage connected through the elevation rod to the driving motor for allowing the wafer trays to be stacked over the stacking stage; and a guide mechanism supporting the wafer trays and the stacking stage for allowing the wafer trays and the stacking stage to be elevated by a driving force of the driving motor. [0043]
It is also preferable that the locking mechanism further comprises: at least two sets of locking members provided different in level by the first pitch. [0044]
It is also preferable that each of the locking members comprises a locking pin. [0045]
It is also preferable that each of the wafer trays further comprises: a body having a flat top surface and a flat bottom face and a thickness as well as having a locking hole, into which the locking pin is inserted; and a contact portion inwardly extending from the body for allowing an edge of semiconductor wafer to be in contact with an upper surface of the contact portion. [0046]
It is also preferable that the contact portion is tapered. [0047]

PREFERRED EMBODIMENT

A first embodiment according to the present invention will be described in detail with reference to the drawings. FIG. 3 is a schematic plane, view illustrative of a semiconductor manufacturing apparatus for processing semiconductor wafers in a first embodiment in accordance with the present invention The present invention is in the improvement in structure of the wafer cassette in the load lock chamber in the semiconductor manufacturing apparatus, for which reason the general structure of the semiconductor manufacturing apparatus is the same as describe in the above prior art. The semiconductor manufacturing apparatus comprises a body [0048] 11 for processing semiconductor devices, a cassette stage 21, on which wafer cassettes 22 for accommodating semiconductor wafers, and a wafer carrier robot 31 for carrying the semiconductor wafers between the body 11 and the cassette stage 21. The body 11 further comprises two load lock-chambers 12 connected to the cassette stage through the wafer carrier robot 31 for isolating the body 11 from an external atmosphere, five process chambers 13 for processing the semiconductor devices, and a single carrying chamber 14 which is connected through the two load lock chambers 12 to the cassette stage, and also connected with the process chambers 13, whereby the process chambers 13 and the two load lock chambers 12 are connected through the carrying chamber 14 to each other. Each of the load lock chambers 12 is provided with a wafer cassette 1 for temporarily storing the semiconductor wafer. The wafer carrier robot 31 carries the semiconductor wafers between the wafer cassettes 1 in the two load lock chambers 12 and the wafer cassettes 22 on the cassette stage 21. The carrier chamber 14 has a wafer carrier robot 15 for carrying the semiconductor wafers between the load lock chambers 12 and the process chambers 13 and also between the process chambers 13. Each of the load lock chambers 12 has a first gate valve at a boundary to the wafer carrier robot 31 and a second gate valve at another boundary to the carrier chamber 14. Each of the process chambers 13 has a gate valve at a boundary to the carrier chamber 14. Each of the load lock chambers 12, the process chambers 13 and the carrier chamber 14 is tightly sealed by the gate valve.
Sequential processes for the semiconductor wafers by the above conventional semiconductor manufacturing apparatus will subsequently be described. The semiconductor wafers are stored in the [0049] wafer cassettes 22 on the cassette stage 21. The wafer carrier robot 31 carries the semiconductor wafer from the wafer cassette 22 on the cassette stage 21 to the wafer cassette 1 in the load lock chamber 12, whereby the semiconductor wafer is stored in the wafer cassette 1 in the load lock chamber 12. The wafer carrier robot 15 in the carrier chamber 14 further carries the semiconductor wafer in the wafer cassette 1 in the load lock chamber 12 to the process chamber 13, whereby the semiconductor wafer is then subjected to a predetermined process, for example, a sputtering process an etching process, or a chemical vapor deposition process. The wafer carrier robot 15 further carries the semiconductor wafer to the other process chamber 13 for a different process. After the semiconductor wafer is subjected to the necessary processes, then the wafer carrier robot 15 in the carries chamber 14 carries the completely processed semiconductor wafer to the wafer cassette 1 in the load lock chamber 12. The wafer carrier robot 31 carries the semiconductor wafer from the wafer cassette 1 in the load lock chamber 12 to the wafer cassette 22 on the cassette stage 21. The gate valves of the load lock chambers 12 and the process chambers 13 are closed for placing the carrier chamber 14, the load lock chambers 12 and the process chambers 13 in individual vacuum states prior to the predetermined processes. After the processes are completed, the load lock chambers 12 are released from the vacuum state for carrying the processed semiconductor wafer in the wafer cassette 1 in the load lock chamber 12 to the wafer cassette 22 on the cassette stage 21.
FIG. 4 is a schematic view illustrative of the novel wafer cassette in the load lock chamber in the semiconductor manufacturing apparatus of FIG. 3, FIG. 5 is a fragmentary enlarged view illustrative of storage grooves of the novel wafer cassette in FIG. 4. The novel wafer cassette [0050] 1 a provided in each of the load lock chamber 12 has plural pairs of wafer trays 2 for storing semiconductor wafers 41. Each pair of the wafer trays 2 stores the single semiconductor wafer. Each pair of the wafer trays 2 has a symmetrical shape. Each of the wafer trays 2 has a tapered-shape inside extending portion 2 d which extends toward the center region, wherein an edge portion of the semiconductor water is in contact with an upper surface of the tapered-shape inside extending portion 2 d of each of the wafer trays 2. The wafer trays 2 extend in lateral direction. The novel wafer cassette 1 a also has a single pair of liner guides 6 extending in a vertical direction to the lateral direction along which the wafer trays 2 extend. The outside edges of the wafer trays 2 are coupled to the paired liner guides 6, wherein the paired wafer trays 2 are movable along the liner guides 6 or in the vertical direction. The novel wafer cassette 1 a also has a stacking stage 5, on which the plural wafer trays 2 are stacked by self-weight. The stacking stage 5 extends in the lateral direction. The opposite side edges of the stacking stage 5 are also coupled to the paired liner guides 6, wherein the stacking stage 5 is movable along the liner guides 6 or in the vertical direction. The stacking stage 5 has a bottom face which is mechanically connected to an elevator mechanism 4 The elevator mechanism 4 elevates the stacking stage 5 along the liner guides 6 or in the vertical direction. The elevator mechanism 4 further comprises a driving motor 4-1 and an elevation rod 4-2 connected between the stacking stage 5 and the driving motor 4-1. Each of the wafer trays 2 has a fixing groove 3 which extends from the outside edge of the wafer tray 2 to an inside thereof. First and second a of locking devices 7 are provided for locking the selected pairs of the wafer trays 2. The cach locking device 7 comprises a cylinder portion 7A or 7B and a lock pin 7C. The lock pin 7C of the locking device 7 inserts into the fixing groove 3 of the wafer tray 2 to lock the wafer tray 2. Once the wafer trays 2 are locked by the locking devices 7, then the wafer trays 2 become unmovable. The first and second pairs of the locking device 7 are inserted from the outside of the side walls of the load lock chamber 12 through the loaner guides 6 to the wafer trays 2. The two sets of the locking devices 7 have predetermined levels different from each other by a larger level difference than the thickness of the wafer trays 2. Assuming that the first selected wafer tray set is locked by the bottom set of the locking devices 7 and the second selected wafer tray set is locked by the top set of the locking devices 7, wherein the wafer tray sets under the first selected wafer tray set are stacked on the stacking stage 5, and further the wafer tray sets over the second selected wafer tray set are stacked on the second selected wafer tray set. Namely, a difference in level between the first selected wafer tray set and the second selected wafer tray set is defined by the distance in level between the top and bottom sets of the locking devices 7 and also is larger than the thickness of the wafer tray set. A difference in level between the second selected wafer tray sot and the top one of the underlying wafer tray sets being positioned under the second selected wafer tray and being stacked over the stacking stage 5 is also larger than the thickness of the wafer tray set.
Operations of storing the wafers into the wafer cassette [0051] 1 a and also picking up the wafers from the wafer cassettes 1 a will be described. The driving motor 4 is driven to move or elevate the stacking stage 5 in the vertical direction along the loaner guides 6, so that the selected wafer tray set 2A of the wafer tray sets 2 stacked over the stacking stage 5 is adjusted to the predetermined level The directly over wafer tray set 2B adjacent to the selected or target wafer tray sot 2A is locked by the top set 7B of the locking devices 7, wherein the locking pins 7C of the locking devices 7 are inserted into the wafer tray sot 2B. The wafer tray sets 2 overlying the wafer tray set 2B are stacked over the wafer tray set 2B. The remaining wafer tray sets 2 underlying the wafer tray set 2B are stacked over the stacking stage 5, wherein the top one of the remaining wafer tray sets 2 underlying the wafer tray set 2B is the target wafer tray 2A. Thereafter, the driving motor 4 is driven to have the stacking stage 5 leveled down in the vertical direction and along the linear guides 6, so that the target wafer tray 2A is adjusted to the predetermined level of the bottom locking device set 7A. Subsequently the target wafer tray 2A is locked by the bottom locking device set 7A, wherein the locking pins 7C of the locking device set 7A arc inserted into the target wafer tray set 2A. The remaining wafer trays 2 underlying the target wafer tray set 2A are stacked over the stacking stage 5 further, the driving motor 4 is driven to have the stacking stage 5 further leveled down in the vertical direction and along the linear guides 6, so that the remaining wafer trays 2 underlying the target wafer tray 2A are further leveled down together with the stacking stage 5. The top one 2C of the wafer tray sets 2 stacked over the stacking stage 5 is made separated from the target wafer tray set 2A. The stacked wafer tray sets 2 have a first pitch “p1 a” which is defined by the thickness of the each stacked wafer tray set 2. A second pitch “p1 b” is defined between the target wafer tray set 2A and the just overlying the wafer tray set 213 A third pitch “p1 c” is defined between the target wafer tray set 2A and the just underlying the wafer tray set 2C The second pitch “p1 b” is wider than the first pitch “p1 a”. The third pitch “p1 c” is wider than the first pitch “P1 a”. Namely, the bottom faces of the target wafer tray set 2A are made separated from the top surfaces of the wafer tray set 213.
A [0052] carrier arm 16 of the wafer earner robot 31 is connected with a blade 17, on which the semiconductor wafer 15 is placed to be moved The carrier am 16 of the wafer carrier robot 31 is operated, so that the semiconductor wafer 41 is moved from the wafer cassette 22 to the wafer cassette 1 in the load lock chamber 12, wherein the semiconductor wafer 41 is stored in the storage tray portions 2 d of the wafer tray set 2A. The wafer carrier robot 15 is operated to extend the carrier arm 16 to pick up the semiconductor wafer 41 in the storage tray portions 2 d of the wafer tray set 2A, so that the semiconductor wafer 41 is further moved to the predetermined process chamber 13. The operations to the wafer carrier robot 15 for carrying the semiconductor wafer 41 to the wafer tray set 2A in the load lock chamber 12, and operations to the wafer carrier robot 16 for carrying the semiconductor wafer 41 are the same as described above.
Thereafter, the driving [0053] rotor 4 is driven to elevate the stacking stage 5 so that the wafer tray set 2C is made into contact with the wafer tray set 2A. The bottom locking device set 7A is released from the wafer tray set 2A so that the wafer tray set 2A is placed into the locking free state, whereby the wafer tray set 2A is then stacked directly on the wafer tray set 2C and over the stacking stage 5.
The driving [0054] motor 4 is driven to further elevate the stacking stage 5, so that the wafer tray set 2A is made into contact with the wafer tray set 2B. The top locking device set 7B is released from the wafer tray set 2B so that the wafer tray set 2B is placed into the locking free state, whereby the wafer tray set 2B is then stacked directly on the wafer tray set 2A and over the stacking stage 5. As a result, all of the wafer tray sets are staked over the stacking stage 5.
The wafer cassette in the load lock chamber comprises a plurality of wafer tray sets, each set storing a single semiconductor wafer, wherein all of the wafer tray sets are laminated together with each other, except for at least selected one of the wafer tray sets and wherein the at least selected one is distanced from adjacent underlying and overlying ones of said wafer tray sets by a wafer tray set locking mechanism to avoid the problems engaged with the prior art and realize reducing the wafer cassette size [0055]
Whereas modifications of the present invention will be apparent to a person having ordinary skill in the art, to which the invention pertains, it is to be understood that embodiments as shown and described by way of illustrations are by no means intended to be considered in a limiting sense. Accordingly, it is to be intended to cover by claims all modifications which fall within the spirit and scope of the present invention. [0056]

Claims

What is claimed is:

1. A wafer cassette mechanism comprising:

a plurality of wafer tray sets, each set storing a single semiconductor wafer;

a supporting mechanism for mechanically supporting the wafer tray sets which are laminated together with each other, and so that adjacent two of the wafer tray sets are in contact directly with each other, said supporting mechanism adjusting level of the laminated wafer trays; and

a locking mechanism for locking selected ones of the wafer tray sets so that a target one of the wafer trays is distanced from adjacent underlying and overlying ones of said wafer tray sots.

2. The wafer cassette mechanism as claimed in claim 1, wherein the wafer cassette mechanism is provided in a load lock chamber.

3. The wafer cassette mechanism as claimed in claim 1, wherein said supporting mechanism further comprises:

a driving motor;

an elevation rod connected with the driving motor;

a stacking stage connected through the elevation rod to the driving motor for allowing the wafer trays to be stacked over the stacking stage and

a guide mechanism supporting the wafer trays and the stacking stage for allowing the wafer trays and the stacking stage to be elevated by a driving force of the driving motor.

4. The wafer cassette mechanism as claimed in claim 1, wherein the locking mechanism further comprises:

at least two sets of locking members provided different in level by a first pitch which is larger than a second pitch which is defined between adjacent laminated two of said wafer trays in contact directly with each other.

5. The wafer cassette mechanism as claimed in claim 4, wherein each of said locking members comprises a locking pin.

6. The wafer cassette mechanism as claimed in claim 5, wherein each of said wafer trays further comprises;

a body having a flat top surface and a flat bottom face and a thickness as well as having a locking hole, into which said locking pin is inserted and

a contact portion inwardly extending from the body for allowing an edge of semiconductor wafer to be in contact with an upper surface of the contact portion.

7. The wafer cassette mechanism as claimed in claim 6, wherein the contact portion is tapered.

8. A wafer cassette mechanism comprising;

a plurality of wafer tray sets, each set storing a single semiconductor wafer;

a locking mechanism for locking selected ones of the wafer tray sets so that a first pitch defined between a target one of the wafer trays and an adjacent overlying one of the wafer tray as well as a second pitch defined between the target wafer tray and an adjacent underlying one of the wafer tray are larger than a third pitch defined between laminated adjacent two of the wafer trays.

9. The wafer cassette mechanism as claimed in claim 8, wherein the wafer cassette mechanism is provided in a load lock chamber.

10. The wafer cassette mechanism as claimed in claim 8, wherein said supporting mechanism further comprises:

a driving motor;

an elevation rod connected with the driving motor;

a stacking stage connected through the elevation rod to the driving motor for allowing the wafer trays to be stacked over the stacking stage; and

11. The wafer cassette mechanism as claimed in claim 8, wherein the locking mechanism further comprises;

at least two sets of locking members provided different in level by the first pitch.

12. The wafer cassette mechanism as claimed in claim 11, wherein each of said locking members comprises a locking pin.

13. The wafer cassette mechanism as claimed in claim 12, wherein each of said wafer trays further comprises:

a body having a flat top surface and a flat bottom face and a thickness, well as having a locking hole, into which said locking pin is inserted and

14. The wafer cassette mechanism as claimed in claim 13, wherein the contact portion is tapered.

15. A semiconductor manufacturing apparatus comprising:

a plurality of process chambers;

at least a load lock chamber having a first type wafer cassette;

a carrier chamber connected with all of the process chambers load lock chamber, and the carrier chamber having a first carrier robot arm;

a cassette stage having a plurality of second type wafer cassettes; and

a second carrier robot arm between the cassette stage and the at least load lock chamber,

wherein the wafer cassette further comprises;

a plurality of wafer tray sets, each set storing a single semiconductor wafer;

is a supporting mechanism for mechanically supporting the wafer tray sets which are laminated together with each other, and so that adjacent two of the wafer tray sets are in contact directly with each other, said supporting, mechanism adjusting level of the laminated wafer trays; and

a locking mechanism for locking selected ones of the wafer tray sets so that a target one of the wafer trays is distanced from adjacent underlying and overlying ones of said wafer tray sets.

16. The semiconductor manufacturing apparatus as claimed in claim 15, wherein the wafer cassette mechanism is provided in a load lock chamber.

17. The semiconductor manufacturing apparatus as claimed in claim 15 wherein said supporting mechanism further comprises

driving motor.

an elevation rod connected with the driving motor;

18. The semiconductor manufacturing apparatus as claimed in claim 15, wherein the locking mechanism further comprises:

19. The semiconductor manufacturing apparatus as claimed in claim 18, wherein each of said locking members comprises a locking pin.

20. The semiconductor manufacturing apparatus as claimed in claim 19, wherein each of said wafer trays further comprises:

a body having a flat top surface and a flat bottom face and a thickness as well as having a locking hole, into which said locking pin is inserted; and

21. The wafer cassette mechanism as claimed in claim 20, wherein the contact portion is tapered.

22. A semiconductor manufacturing apparatus comprising:

a plurality of process chambers;

at least a load lock chamber having a first type wafer cassette,

a carrier chamber connected with all of the process chambers load look chamber, and the carrier chamber having a first carrier robot arm;

a cassette stage having a plurality of second type wafer cassettes; and

wherein the wafer cassette further comprises

a plurality of wafer tray sets, each set storing a single semiconductor wafer;

23. The semiconductor manufacturing apparatus as claimed in claim 22, wherein the wafer cassette mechanism is provided in a load lock chamber.

24. The semiconductor manufacturing apparatus as claimed in claim 22, wherein said supporting mechanism further comprises:

a driving motor;

an elevation rod connected with the driving motor;

a guide, mechanism supporting the wafer trays and the stacking stage for allowing the wafer trays and the stacking stage to be elevated by a driving force of the driving motor.

25. The semiconductor manufacturing apparatus as claimed in claim 22, wherein the locking mechanism further comprises:

at least two sets of locking members provided different in level by the fir&t pitch.

26. The semiconductor manufacturing apparatus as claimed in claim 25, wherein each of said locking members comprises a locking pin.

27. The semiconductor manufacturing apparatus as claimed in claim 26, wherein each of said wafer trays further comprises:

body having a flat Lop surface and a flat bottom face and a thickness as well as having a locking hole, into which said locking pin is inserted; and

28. The semiconductor manufacturing apparatus as claimed in claim 27, wherein the contact portion is tapered.